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For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L G =25nm featuring record high I ON =508 µA/µm at I OFF =100nA/µm and V DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D IT and N IT for s-Si 0.4 Ge 0.6 channel, (b) record high hole mobility= 450 cm2/Vs owing to compressive strain imparted by Si 0.7 Ge 0.3 strain relaxed buffer (SRB), (c) low R EXT =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I OFF . Additionally, the impact of operating temperature on GIDL and I OFF is comprehensively studied to prescribe optimal V CC range of operation for this technology.

We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28 Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

Wetting on a corrugated surface that is formed via wrinkling of a hard skin layer formed by UV oxidation (UVO) of a poly(dimethylsiloxane) (PDMS) slab is studied using advancing and receding water contact angle measurements. The amplitude of the wrinkled pattern can be tuned through the pre-strain of the PDMS prior to surface oxidation. These valleys and peaks in the surface topography lead to anisotropic wetting by water droplets. As the droplet advances, the fluid is free to move along the direction parallel to the wrinkles, but the droplet moving orthogonal to the wrinkles encounters energy barriers due to the topography and slip-stick behavior is observed. As the wrinkle amplitude increases, anisotropy in the sessile droplet increases between parallel and perpendicular directions. For the drops receding perpendicular to the wrinkles formed at high strains, the contact angle tends to decrease steadily towards zero as the drop volume decreases, which can result in apparent hysteresis in the contact angle of over 100°. The wrinkled surfaces can exhibit high sessile and advancing contact angles (>115°), but the receding angle in these cases is generally vanishing as the drop is removed. This effect results in micrometer sized drops remaining in the grooves for these highly wrinkled surfaces, while the flat analogous UVO-treated PDMS shows complete removal of all macroscopic water drops under similar conditions. These wetting characteristics should be considered if these wrinkled surfaces are to be utilized in or as microfluidic devices.

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.

The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.

Elastic constants and cross-sectional dimensions of imprinted nanolines of poly(methyl methacrylate) (PMMA) on silicon substrates are determined nondestructively from finite-element inversion analysis of dispersion curves of hypersonic acoustic modes of these nanolines measured with Brillouin light scattering. The results for the cross-sectional dimensions, under the simplifying assumption of vertical sides and a semicircular top, are found to be consistent with dimensions determined from critical-dimension small-angle x-ray scattering measurements. The elastic constants C(11) and C(44) are found to be, respectively, 11.6% and 3.1% lower than their corresponding values for bulk PMMA. This result is consistent with the dimensional dependence of the quasi-static Young's modulus determined from buckling measurements on PMMA films with lower molecular weights. This study provides the first evidence of size-dependent effects on hypersonic elastic properties of polymers.