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We demonstrate ultralow ohmic contact resistance to antimonide-based, p-channel quantum-well field-effect transistor (QW-FET) structures using a new p[superscript ±]-InAs/InAsSb cap structure. The incorporation of a p[superscript ±]-InAsSb layer enables the use of a thicker cap with lower sheet resistance, resulting in an improved contact resistivity. Using a Pd-based ohmic scheme, the composite cap structure resulted in a 4x reduction in contact resistance compared with a standard p[superscript ±]-InAs cap. This translates into nearly 3x improvement in the gm of fabricated InGaSb p-channel QW-FETs. Furthermore, Ni contacts on the composite cap were fabricated and a contact resistance of 45 Ω · μm was obtained. An accurate contact resistivity extraction in this very low range is possible through nanotransmission line models with sub-100 nm contacts. In devices of this kind with Ni-based contacts, we derive an ultralow contact resistivity of 5.2 · 10[superscript -8] Ω · cm[superscript 2]., Samsung (Firm), Intel Corporation

We have investigated the impact of high-power (HP) stress on the dynamic ON-resistance (RON) in high-voltage GaN High-Electron-Mobility Transistors (HEMTs). We use a newly proposed dynamic RON measurement methodology which allows us to observe RON transients after an OFF-to-ON switching event from 200 ns up to any arbitrary length of time over many decades. We find that HP-stress results in much worsened dynamic RON especially in the sub-ms range with minor changes on a longer time scale. We attribute this to stress-induced generation of traps with relatively short time constants. These findings suggest that accumulated device operation that reaches out to the HP state under RF power or hard-switching conditions can result in undesirable degradation of dynamic RON on a short time scale., United States. Advanced Research Projects Agency-Energy. Agile Delivery of Electrical Power Technology, Semiconductor Research Corporation, United States. Office of Naval Research. Design-for-Reliability Initiative for Future Technologies. Multidisciplinary University Research Initiative (ONR Grant)

This paper reports an extensive analysis of the physical mechanisms responsible for the failure of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). When stressed under high applied electric fields, the traps at the dielectric/III-N barrier interface and inside the III-N barrier cause an increase in dynamic on-resistance and a shift of threshold voltage, which might affect the long term stability of these devices. More detailed investigations are needed to identify epitaxy- or process-related degradation mechanisms and to understand their impact on electrical properties. The present paper proposes a suitable methodology to characterize the degradation and failure mechanisms of GaN MIS-HEMTs subjected to stress under various off-state conditions. There are three major stress conditions that include: VDS = 0 V, off, and off (cascode-connection) states. Changes of direct current (DC) figures of merit in voltage step-stress experiments are measured, statistics are studied, and correlations are investigated. Hot electron stress produces permanent change which can be attributed to charge trapping phenomena and the generation of deep levels or interface states. The simultaneous generation of interface (and/or bulk) and buffer traps can account for the observed degradation modes and mechanisms. These findings provide several critical characteristics to evaluate the electrical reliability of GaN MIS-HEMTs which are borne out by step-stress experiments.

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at V[subscript ds]= 0.3 V is obtained over 2 decades of current. On the same device, I[subscript on]= 0.27 μA/μm is extracted at V[subscript dd]= 0.3 V with a fixed I[subscript off]= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials., National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514)

The PowerChip research program is developing technologies to radically improve the size, integration, and performance of power electronics operating at up to grid-scale voltages (e.g., up to 200V) and low-to-moderate power levels (e.g., up to 50W) and demonstrating the technologies in a high-efficiency light-emitting diode driver, as an example application. This paper presents an overview of the program and of the progress toward meeting the program goals. Key program aspects and progress in advanced nitride power devices and device reliability, integrated high-frequency magnetics and magnetic materials, and high-frequency converter architectures are summarized.

An Online Lab is a multi-university shared laboratory environment, where students can exercise their knowledge as they would do in a physical lab. The idea is to have maximum resource utilization and collaboration between universities by sharing of ideas. This kind of remote laboratory negates the economic issues to set up a laboratory and allows every student to have an experience of real laboratory. As part of Ministry of Human Resource Development (MHRD) Robotics Lab project a study on state of art of remote labs was conducted. This paper discusses some key issues in the design and operation of such remote labs. The lab should be remotely usable by a large student body, with varied levels of sophistication, all the way from elementary learners, to PhD students doing research. In addition, the high design load implies that the architecture should be highly parallel, and structurally reliable.

This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations., Semiconductor Research Corporation. (Grant Number 2007-HJ-1661)

In this work, we investigate the time evolution of electrical degradation of GaN high electron mobility transistors under high voltage stress in the OFF state. We found that the gate current starts to degrade first, followed by degradation in current collapse and eventually permanent degradation in I[subscript D]. We also found that the time evolution of gate current degradation is unaffected by temperature, while drain current degradation is thermally accelerated.

We have performed V[subscript DS] = 0 V and OFF-state step-stress experiments on GaN-on-Si and GaN-on-SiC high electron mobility transistors under UV illumination and in the dark. We have found that for both stress conditions, UV illumination decreases the critical voltage for the onset of degradation in gate current in GaN-on-Si HEMTs in a pronounced way, but no such decrease is observed on SiC. This difference is attributed to UV-induced electron detrapping, which results in an increase in the electric field and, through the inverse piezoelectric effect, in the mechanical stress in the AlGaN barrier of the device. Due to the large number of traps in GaN-on-Si, this effect is clearer and more prominent than in GaN-on-SiC, which contains fewer traps in the fresh state., United States. Defense Advanced Research Projects Agency, United States. Office of Naval Research (MURI)

12th Biennial International Conference on Engineering, Construction, and Operations in Challenging Environments; and Fourth NASA/ARO/ASCE Workshop on Granular Materials in Lunar and Martian Exploration Honolulu, Hawaii, United States March 14-17, 2010, The MIT iLab Project is dedicated to the goal of increasing laboratory experimentation opportunities for engineering students worldwide. Since its inception in 1998, the project has furthered this goal through the development of individual remote laboratories, or iLabs, as well as a distributed software infrastructure designed to streamline the implementation and sharing of remote laboratories. iLabs are designed to complement traditional, hands-on laboratories by providing practical educational experiences where they would not otherwise be available. Such remote labs, developed and hosted by MIT and other institutions within the iLab Consortium, have been successfully used by instructors at schools across the educational spectrum and around the world. While certainly valuable, many of the original experiments available through the iLab platform provide a limited experience in that they are observational in nature. They only provide students the ability to study the behavior of a pre-defined system under test. Such labs have proven to be valuable additions to engineering curricula, but do not have the flexibility that is inherent in a traditional laboratory experience. To address this, the MIT iLab Project has begun focusing on the development of iLabs that provide students with the ability to design or troubleshoot experimental systems. Through two particular remote labs, focusing on electronic control system analysis and basic electronics test and measurement respectively, the project is designing remote labs that provide a more flexible learning experience for students and are more attractive to instructors in a broad set of disciplines., National Science Foundation (U.S.) (award 0702735), Singapore-MIT Alliance for Research and Technology Center, Microsoft Corporation, Carnegie Corporation of New York, Maricopa County Community College District. Maricopa Advanced Technology Education Center

The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range., Semiconductor Research Corporation, Intel Corporation

A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp[superscript 3]d[superscript 5]s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass-based ballistic quantum transport model is employed to simulate three-terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage current of the QWFETs, i) the geometry of the gate contact (curved or square) and ii) the Schottky barrier height at the gate metal contact. In addition to pushing the threshold voltage toward an enhancement mode operation, a higher Schottky barrier at gate metal contact can help suppress the gate leakage and enable aggressive insulator scaling., Semiconductor Research Corporation, Microelectronics Advanced Research Corporation (MARCO) (Focus Center on Materials, Structures, and Devices), National Science Foundation (U.S.)

We have comprehensively investigated the degradation mechanism of AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (PHEMTs) under operation in high humidity conditions. PHEMTs degradation under high humidity with bias consists of a decrease in maximum drain current (Imax) caused by a corrosion reaction at the semiconductor surface at the drain side. The decrease in Imax is markedly accelerated by the external gate–drain bias (Vdg). This originates from a reduction in the actual activation energy (Ea0) by Vdg. The degradation depends on the surface treatment prior to deposition of the SiNx passivation film. The reduction of As-oxide at the SiNx/semiconductor interface suppresses the corrosion reaction.