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Event-based dynamic vision sensors (DVS), inspired by biological vision systems, lead to new sensing and computing paradigms. The novel sensors output the sensed signal alone with many noise events asynchronously. Data-preprocessing for filtering these noises is significant before utilizing the data in applications such as classification, tracking and motion-data extraction. This paper describes a fully spike-based and neuromorphic-hardware-implementable neural network with a signal-oriented self-adaptive filtering time window for filtering the noise events robustly in the data captured by DVS. In particular, the simple leaky integrate-and-fire (LIF) neuron model is adopted as the basic elements of the network out of the purpose of hardware-friendly. Experiments based on both synthesized data and authentically-captured data are designed for quantitative comparison with traditional DVS noise filters to verify the outperformance of the proposed filter. The main contribution of this work is that the proposed spiking neural network (SNN) based filter achieves higher signal-noise-ratio (SNR) compared to traditional noise filters and performances more robust in the tolerance for changing signals.

To address the security challenge of integrated circuits, the Physical Unclonable Function (PUF) is of great concern as the root of trust. However, the PUF circuits are suffering from the modeling attacks in recent years. The design of anti-modeling-attack PUF is still an open issue. The XbarPUF with both column swapping and XORing was reported as an anti-modeling-attack PUF in 2017. This work proposes a two-step attack method. The first step transforms the target PUF into the XbarPUFs with XORing only, based on the column swapping states. The second step attacks the XbarPUFs with XORing only by the intentionally designed Artificial Neural Network (ANN) model. This method can predict the challenge response pairs (CRPs) of the XbarPUF with both column swapping and XORing successfully. To enhance the anti-modeling-attack capability, an improved XbarPUF is further proposed, which uses the dynamic column swapping technique. The results show that the prediction accuracy of attacks for the XbarPUF with both column swapping and XORing and the proposed XbarPUF reaches 98.96% and 70%, respectively, if the training CRPs account for one millionth of the total CRPs. The proposed XbarPUF has a better anti-attack capability than the XbarPUF with both column swapping and XORing.

Graphics rendering is a compute-intensive work and a major source of energy consumption on battery-driven mobile devices. Unlike the existing works that degrade user experience or reuse rendering results coarsely, we propose ReTriple, a fine-grained scheme to reduce rendering workload by reusing the past rendering results at the UI element level. This fine-grained reuse mechanism can explore more opportunities to reduce the workload of the rendering process and save energy. The experiments tested with popular apps show that ReTriple achieves an average speedup of 2.6x and per-frame energy saving of 32.3% for the rendering process while improving user experience.

An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (MISR)-based response compactor, and both the n-stage LFSR and MISR are implemented by n + 2 in-array RRAM cells. The proposed LFSR/MISR circuit has better performance than the IMPLY-based counterpart, due to the application of the proposed three-cycle XOR gate and two-cycle shift gate with the in-array RRAM cells. And it is more area efficient comparing with the memristor ratioed logic (MRL)-based counterpart. The proposed n-stage LFSR/MISR circuit is tested by the scan chain method. The test method only has the linear time complexity. For the best of our knowledge, it is the first attempt to design the in-array BIST circuit for the RRAM array.

The channel doping effects in negative capacitance field-effect transistors (NCFETs) of the metal-ferroelectric-insulator-semiconductor (MFIS) structure are analysed in this work, and an analytical model is developed. The NCFET threshold voltage with channel doping is defined, and a nonmonotonic dependence on the doping concentrations is predicted. A unified charge formulation is developed for the current–voltage characteristics of double gate MFIS structures. Statistical modelling for NCFETs is further developed. Standard deviations of four parameters are extracted, reproducing the distributions of NCFET current–voltage characteristics. Experimental calibrated TCAD simulations validate the analytical model for wide ranges of device parameters, allowing its application to devices and circuits.

In conventional HfO2-based resistive random access memory (RRAM), SiO2 is usually adopted as side wall spacer (low-k spacer) to define the device feature size. It is found that the forming voltage of the conventional HfO2 RRAM with SiO2 spacer rises when the device size is scaling down from 16.0 μm2 to 0.16 μm2, which is detrimental for application of high density HfO2-based RRAM. In this study, a high permittivity side wall spacer (high-k spacer) Ta2O5 is introduced to replace SiO2 spacer. The Ta2O5 side wall effectively suppress the forming voltage rising issues during RRAM device scaling without introducing costly processing steps. Moreover, compared to the conventional HfO2-based RRAM, the side wall enhanced device exhibits faster switching speed, smaller operation voltage, and higher reliabilities, including endurance and retention. As a result, the use of Ta2O5 side wall significantly enhances the overall switching characteristics of the HfO2-based RRAM device.

With the leakage power becoming a most important concern in deep sub-micron designs, the advent of FinFET offers promising options due to its superior electrical properties and design flexibility. To support the VLSI digital system design flow based on the standard cells in FinFET, the building method of optimized FinFET standard cells is proposed. This method is derived on the basis of jointly optimizing the back-gate voltages and the width to length ratio of the transistors in the stacked structure in each standard cell under the premise of maintaining the performance. By employing this design method, optimized standard cells are generated and form a low-power high-performance standard cell library. Simulation results of the standard cells designed with our proposed method demonstrate that the leakage power can be reduced by a factor of 47.99 at most while the worst-case delay can achieve a maximum reduction of 10.17%. Monte Carlo simulation results illustrate that the optimized cells can gain more dependability to process variations and environmental changes. The 16-bit ripple carry adder implemented with this optimized FinFET library can obtain a maximum leakage power reduction of 59.6% and a worst-case delay reduction of 21.8%.

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a $3 \times 3$ TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

A further leakage reduction of AlGaN/GaN HEMTs with cap gate (CG-HEMTs) has been achieved by optimizing the gate structure and the gate etching process. The optimized CG-HEMTs single finger power HEMTs deliver I DSmax = 533 mA/mm at least with gate length of 0.5um and show a median gate leakage current of 20 nA/mm 25 °C measured at a drain voltage of 200 V. The breakdown voltage (BV) of CG-HEMTs was evaluated by the variation of drain-to-gate spacing (L DG ) larger than 8 μm. Furthermore, we show that the forward voltage of CG-HEMTs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance.

Elliptic curve cryptography (ECC) is one of the most popular public key cryptosystems in recent years due to its higher security strength and lower resource consumption. However, the noninvasive side-channel attacks (SCAs) have been proved to be a big threat to ECC systems in many previous researches. In this paper, we propose a low-area-time-product ECC coprocessor for GF(2 m ) with the ability to resist most of the existing noninvasive SCAs. The basic countermeasures are relied on the underlying finite field arithmetics in randomized Montgomery domain, which can blind the intermediate value in the iterations of scalar multiplication to prevent the adversaries from cracking the private key by statistical methods. Meanwhile, we optimize the modular division and modular multiplication algorithms to fix the operating time to resist some certain timing attacks, and the Montgomery Ladder algorithm makes the coprocessor immune against simple SCAs. To efficiently implement our coprocessor, we present a hybrid operation sequence which merely needs one multiplication module and one division module to complete the entire operations. The synthesis results indicate that our design is superior to other related works in area-time product (ATP) and the extra overhead paid for the countermeasures is less than 5%.

Aiming at the dynamic attitude tracking system of vehicle motion, the vehicle attitude measurement and calculation are performed using a combination of three-axis accelerometer and three-axis gyroscope. Proposed a quaternion Extended Kalman Filter (EKF) algorithm for dynamic attitude tracking system. Through the Euler angle and quaternion transformation method, the attitude quaternion of the gyroscope is used as the state quantity of the EKF algorithm. The attitude quaternion calculated by the accelerometer is used as the observation quantity. And corrected by adaptive measurement noise covariance matrix. Established Kalman equation to obtain a high-precision attitude quaternion to solve the attitude angle. The experimental results show that the algorithm effectively solves the shortcomings of low accuracy and large error of MEMS sensors, and improves the accuracy of vehicle attitude tracking system.

Polymorphic gates are reconfigurable devices that deliver multiple functionalities at different temperature, supply voltage or external inputs. Capable of working in different modes, polymorphic gate is a promising candidate for embedding secret information such as fingerprints. In this paper we report five polymorphic gates whose functionality varies in response to specific control input and propose a circuit fingerprinting scheme based on these gates. The scheme selectively replaces standard logic cells by polymorphic gates whose functionality differs with the standard cells only on Satisfiability Don't Care conditions. Additional dummy fingerprint bits are also introduced to enhance the fingerprint's robustness against attacks such as fingerprint removal and modification. Experimental results on ISCAS and MCNC benchmark circuits demonstrate that our scheme introduces low overhead. More specifically, the average overhead in area, speed and power are 4.04%, 6.97% and 4.15% respectively when we embed 64-bit fingerprint that consists of 32 real fingerprint bits and 32 dummy bits. This is only half of the overhead of the other known approach when they create 32-bit fingerprints.

Heart Rate Variability (HRV) refers to such a quantitative scale measurement, which can reflect the regularity of heart rate changes. Taking two common cardiovascular diseases as an example, this paper obtained 14 eigenvalues by analyzing the HRV data taken from PhysioNet in the time domain and frequency domain through the “normperiod” code. Accordingly, disease classification was carried out using an improved K-Nearest Neighbor (KNN) algorithm, including module of removing boundary, uniform density and distance weighting. Finally, we obtained an accuracy of up to 98% and a sensitivity of up to 100%. The results illustrate that this approach with low computational cost enables surveillance and early warning of a large group of cardiovascular diseases effectively.

In integrated circuit (IC) burn-in, it is desirable to produce efficient input patterns to assist heating for circuit under test. This study proposes and demonstrates an approach which uses the genetic algorithm incorporating with a BACK-like procedure to generate the patterns which produce the maximal and/or uniform node transition as well as power dissipation for burn-in application. A multi-step strategy is applied in the algorithm, and a transition measure is defined to guide the backtracing of the BACK-like procedure, improving the efficiency in searching the target patterns. Experimental results show that the approach generates better pattern pairs which produce either the maximal transition count or the maximal power dissipation than that of all the other published results. It is also able to generate the pattern sequence which achieves more uniformly stressing, by 30% improvement statistically, for each gate of the circuit under test. The computation time, because of using a divide-and-conquer strategy in this approach, is also reasonable, making it useful in the practical IC burn-in application.

The development of large-scale networks with artificial neurons and adaptive synapses has suggested new avenues of exploration for brain-like cognitive computing. Spiking neural networks (SNNs), highly inspired from natural computing in the brain and recent advances in neurosciences, are often referred to as the 3th generation of neural network, and become a new research hotspot in the era of artificial intelligence. SNN architecture supports simpler category of biologically-inspired neuron models and more complex large-scale interconnection in on-chip network of neurosynaptic cores. This paper introduces the design of router used in a spiking neural network, which is able to send and receive spiking information in network properly, as well as perfectly dealing with network anomaly such as data race or traffic congestion. This router is designed for the network at a scale of 64 ∗ 64 neurosynaptic cores at the most, with 256 neurons in each cores. Both the area and estimated power consumption is acceptable. This router could also be applied to larger scale of SNN architecture networks effectively.

In cold boot attacks, attackers attempt to retrieve encryption keys from the memory after the system is powered off. One representative cold boot attack, known as HMM algorithm, can break RSA with success probabilities as high as 82%. However, it, like other cold boot attacks, uses the symmetric memory decay model, which assumes that a bit is equally likely to change from 1 to 0 and from 0 to 1. It also requires that the bit error probability to be relatively small, which means that the attack must be launched within seconds of system power off. In this paper, we first show that under more realistic assumptions, HMM's success probability drops to 2.3%. We then propose a practical improvement of HMM algorithm with a proven lower bound on success probability and low runtime complexity. We conduct simulation and the results confirm that our approach improves HMM's chance of breaking RSA to 49.96%.

The traditional random multi-byte fault model in AES fault attack only uses the faulty ciphertexts with diagonal-fault distributions to implement differential fault analysis. When there are not enough exploitable faulty ciphertexts, the round key could not be confirmed directly, and a comparatively large search space is still left for brute-force attack. In this paper, an improved differential fault analysis (DFA) using all-fault ciphertexts on AES was proposed. The all-fault ciphertexts could be used to optimize the selection of the brute-force space, which is helpful to recover the secret key quickly and improves the analysis efficiency. The experiment result demonstrated that by applying the DFA with all-fault ciphertexts, the time consumed on the brute-force attack can be reduced 60.81% on average, which significantly accelerated the process of cracking AES.

Differential fault analysis (DFA) aiming at the advanced encryption standard (AES) hardware implementations has become a widely research topic. Unlike theoretical model, in real attack scenarios, popular and practical fault injection methods like supply voltage variation will introduce faults with random locations, unknown values and multibyte. For analyzing this kind of faults, the previous fault model needed six pairs of correct and faulty ciphertexts to recover the secret round-key. In this paper, on the premise of accuracy, a more efficient DFA attack with unknown and random faults is proposed. We introduce the concept of theoretical candidate number in the fault analysis. Based on this concept, the correct round-key can be identified in advance, so the proposed attack method can always use the least pairs of correct and faulty ciphertexts to accomplish the DFA attacks. To further support our opinion, random fault attacks based on voltage violation were taken on an FPGA board. Experiment results showed that about 97.3% of the attacks can be completed within 3 pairs of correct and faulty ciphertexts. Moreover, on average only 2.17 pairs of correct and faulty ciphertexts were needed to find out the correct round-key, showing significant advantage of efficiency compared with previous fault models. On the other hand, less amount of computation in the analyses can be realized with a high probability with our model, which also effectively improves the time efficiency in DFA attacks with unknown and random faults.

This study presents a test scheduling strategy for multi-tower three dimensional (3D) stacked ICs (SICs). Towards the given complete stack, a session-less based test scheduling method is proposed. Experimental results show that the proposed method minimizes the total test time under the constraints of the number of test TSVs and test pins. Besides, it is found out that the 3D-SIC configuration in which complex dies integrating on the lower layer of each tower results in shorter test time.

The neuromorphic computing is an emerging paradigm for multimedia applications due to the features of massive parallelism, adaptivity to the complex input information, and its tolerance to errors. The oxide-based resistive switching device is a promising candidate to implement the synapse functions of neuron network due to the extra-low energy loss per spike. This work implements a simplified circuit system of neuromorphic visual system using the real RRAM devices with spike tuning scheme, and its capability of learning is validated.

The TSV(Through-Silicon Via) plays an important role of inter-layer interconnection in 3D ICs. However, TSV is defect prone. This paper proposes a new scheme based on oscillator to monitor the defects of TSV at the prebond stage.

The pre-bond through silicon via (TSV) probing tests and fault localization are important for yield assurance in 3D-SICs. This paper proposes an optimization algorithm to generate the preferable set of test sessions for pre-bond TSV probing tests. Test sessions generated by the optimization algorithm can not only get localization of faulty TSVs in TSV network, but also reduce test time and cost of the pre-bond TSV test. By using the proposed optimization algorithm, the reduction in pre-bond TSV test time is 10% for the pinpointing of four faulty TSVs in 13-TSV network and even 20.5% for one faulty TSV in 6-TSV network compared to the original one [4].

In the VLSI, the crosstalk is a crucial problem for the circuit performance improvement. Both the crosstalk avoidance code (CAC) and shielding wire technique can effectively eliminate the crosstalk noise. But the CAC consumes too much codec area and codec power with the increase of the bus width, and the shielding wire technique costs too much system overhead. This work tries to combine the CAC technique and the shielding method into a bus partitioning scheme. It can effectively eliminate crosstalk, and simultaneously reduce codec area and codec power, as well as the system overhead. The forbidden pattern free (FPF) CAC, which is based on the Fibonacci Numeral System (FNS), is applied to the partitioned sub-buses. The experimental results show that the codec area and codec power of the partitioned bus are 7.8% and 25.67%, respectively, of the non-partitioned bus in 30-bit bus.

Through-silicon vias (TSVs) play an important role as the vertical connections in three dimensional (3D) integrated circuit (IC). However, the 3D IC suffers from the increasing crosstalk noise between TSVs as the working frequency gets higher. The crosstalk in TSV arrays is more complicated than that of 2D IC because more aggressors have to be considered. This paper proposes a crosstalk avoidance method combining the crosstalk avoidance code (CAC) with the shielding wire technique by dividing the TSV array into some 3×3 sub-arrays. This method can suppress the crosstalk in TSV array below 4.5C level, which elevates the performance of 3D IC effectively.

A high-efficient fault attack on AES S-box is proposed in this paper. Faults are introduced in the encryption process by changing the mapping relationship of S-box. Based on the round in which the faults are introduced, two fault models are presented. Attack results show that the first model only needs 16 faulty ciphertexts to recover the 128-bit secret key. The second fault model is more efficient. In this model, two rounds of attacks are enough to find out the 4-byte round-key based on DFA on the 9th round S-box. For covering all the possible fault situations, influence of multi-byte faults are considered, which effectively improves the attack accuracy and reduces the attack rounds. Compared with previous fault models, our work in this paper shows significant advantage of efficiency.

Random fault attacks against Advanced Encryption Standard (AES) hardware implementation are widely researched. In the previous fault analysis, 6 rounds of attacks are required to recover the correct round-key, which is not efficient enough for extensive analysis. In this paper, a more efficient fault model is proposed. Based on the analysis of theoretical key candidate number, the proposed attack method can complete the analysis as few as 3 rounds. Experiment results shows that nearly 90% of the attacks recover the correct round-key with 3 rounds and in average only 3.125 rounds are required with our proposed attack method.

Phase change memory (PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The March test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.

Through Silicon Vias (TSVs) are the transmission lines between different bonding layers and are indispensable elements in three-dimensional integrated circuits (3D-ICs). But because of process problems, kinds of defects exist in TSVs, including open defects and short defects. A variety of test methods have been proposed for open defects, but few can deal with both open defects and short defects. In this work, a post-bond method is presented for both defects by using voltage division. TSVs with defects can be located by testing the output pulses. HSPICE simulations including process parameter variations show the effectiveness of the method.

Series structures are inevitable and common in the design of digital logic gates. In this paper, to reduce the leakage power, we transplant the technique of mixed forward and reverse back-gate bias (mixed FBB/RBB) from FinFET forced stacks to the more widely-used series structures in FinFET logic gates. By employing the mixed FBB/RBB technique, the goal of leakage reduction is achieved without speed penalty. Performance of series structures of NMOS/PMOS transistors are studied. Simulation results based on the Predictive Technology Model 32nm FinFET model indicate that the speed can be maintained the same while reducing the leakage up to a factor of 18.3 compared with the structure without mixed back-gate biasing. This approach provides us a new viewpoint in designing low stand-by circuits without any sacrifice in the speed. The 16-bit ripple carry adder based on this methodology can acquire at least 51.8% leakage reduction.

Three-dimensional integrated circuits (3D-ICs) using Through-silicon Vias (TSVs) allow the stacking multiple dies to manufacture chips with many benefits, such as high density and high bandwidth. Unfortunately, the yield of 3D dies, stacking with a large number of TSVs is significantly impacted by the reliability of TSVs. In order to improve the yield of 3D-ICs, TSVs must be reparable. In practice, the faulty TSVs may cluster because of the imperfect bonding quality of TSVs. A right trapezoidal grouping based method was proposed to repair clustered faulty TSVs in this paper. Experimental results show that the yield of the proposed method is 99.80% with 50% area reduction compared to that of the router-based method.

Setup time variation fault attacks that aim straightly at the FPGA devices have become hot spots nowadays. A high-efficient and accurate fault model aiming at FPGA-based cryptographic applications is proposed in this paper. Multi-diagonal faults are considered in this paper, thus more exploitable faulty ciphertexts can be gathered compared with the previous model. Multi-fault analysis is introduced due to the existence of multi-fault injection, which guarantees the accuracy of the result. Experiment result shows that the fault model brings a significant increase up to 36.5% of the exploitable faults compared with the previous method. Within 24 pairs of correct and faulty ciphertexts, the complete round key can be retrieved by this model.

The impact of channel line-edge roughness (LER) on Junctionless FinFET device (JL-FinFET) is investigated by using the 3-D statistical simulation. Then the substantial influence of its narrowest width of the JL-FinFET is defined and presented. The results show that JL-FinFET is more sensitive to LER than inversion-mode FinFET. Further, the performance including the threshold voltage and on-state current is observed to be determined by the narrowest width of channel. The narrower channel has smaller on-state current and larger threshold voltage. The variations of on-state current caused by LER increase as the place of the narrowest channel width moving from drain to source. These imply that it is important to reduce the LER near the source side to suppress performance variations.

It is desirable for an uniform power distribution in the chip during the dynamic burn-in, in which stimuli are inputted into the circuit under test. This paper uses the genetic algorithm to get an optimized input order of burn-in patterns for IP cores to approximate the uniformity of the power distribution in the SoC under the constraints of peak power and TAM width. The experimental results shows that the proposed method is effective on power uniformity for the fixed-width TAM SoC.

A power-optimized Programmable Gain Amplifier (PGA) for low power UWB receivers is presented. The PGA consists of a buffer and three gain cells which have additional input stages in parallel. By enhancing the current in additional input stage which is applied in programmed gain level, larger gain is acquired and the area cost is reduced theoretically at the same time. The PGA is programmable in the 0–40dB range with 5dB step and its 3dB bandwidth is greater than 250MHz. The current consumption (1.9mA at 0dB gain up to 2.5mA at 40dB gain) is optimized according to the selected gain level.

A low-voltage bandgap reference implemented in circuit is optimized by adjusting the ratio of the resistors, and reducing the working voltage of operational amplifier. It achieves the performance of a temperature coefficient of 25 ppm/oC in the range of 0∼100"C which works under the voltage of 0.8V. The simulated power supply rejection ratio is 46.3dB @1Hz and the line regulation is 1.5mV/V in the range from 0.8V to 1.8V.

High Efficient Video Coding (HEVC) is the latest coding standard with superior compression efficiency while its encoding complexity is much higher compared with H.264/AVC. Motion estimation is one of the most time-consuming parts in video coding. In the reference software of HEVC, TZ (Test Zone) search method is adopted as the fast motion estimation method. However, its complexity is still high. There are many other fast motion estimation methods, for example, the hexagon search method, but their performance loss is larger than TZ search. In order to balance coding speed and performance, a new context-adaptive fast motion estimation algorithm is proposed in this paper. In this the proposed, motion intensity is defined in block-level, motion vectors and motion vector differences of neighbor blocks are utilized to measure the motion intensity. When motion intensity is large, TZ search method is used; otherwise, hexagon search method is used. Experimental results show that the proposed method can save 39% ∼ 60% of motion estimation time with average 0.5% of BD-rate loss.

Elliptic Curve Cryptography is a popular algorithm since it can achieve good security level with a small key size. However, the ECC hardware is suffering from some side channel attacks, such as Differential power-analysis (DPA), which can retrieve secret keys by analyzing power consumption of the attacked devices. In this paper, a countermeasure to secure the modular multiplication, an important operation of Elliptic Curve Cryptography, with randomization method is studied. The experiment results show that unprotected device reveal the secret key within 1000 power traces, while the protected one can defend DPA attack with 105 power traces, with only 8% additional area cost.

A SPICE model of Phase Change Memory (PCM) is developed based on a proposed analytical resistance model, which enables the PCM circuit simulation adaptable to different device geometry for the first time. The model agrees with experimental data and results show it is able to predict device characteristics with different geometry.

A low phase noise wideband LC VCO is designed and presented. In this VCO, a symmetrical LC tank with proper arrangement of varactors is used to extend its tuning range. Results from the post layout simulation show that the VCO achieved a wide tuning range from 2.34GHz to 3.29GHz. Moreover, a noise cancellation technique is adopted to achieve better phase noise performance. The VCO exhibits that phase noise is lower than −120.1dBc/Hz at 1-MHz offset frequency. The circuit consumes 2.38mA of power from a 1.8V supply.

An symmetric double-heater structure is proposed into the traditional stacked layer phase-change memory (PCM) for the first time. It contains no barrier layer. The superior multi-level storage (MLS) is verified in this structure by numerical simulation. Temperature at the interface of two phase-change materials is greatly reduced by reasonably choosing the heater radius, which is beneficial for less atomic interdiffusion at the interface, thus more stable MLS. Device performance can be optimized through material thickness trade-off. Hence, this structure is a candidate utility for the future MLS device

The impact of junction formed by the electrode and bulk in phase change memory to conduction at the amorphous high resistance state is studied in this paper. Analytical model deduced from basic physical equation elucidates that the current changes from junction barrier limited to bulk barrier limited when the applied voltage increases. The currents deduced from the model are in highly consistent with the measurement data at different temperatures. It is also found that the junction barrier becomes non-negligible when the radius of bottom electrode is scaled down to 20 nm.

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.

This paper proposes two Design-for-Test (DfT) architectures for three-dimensional stacked ICs (3D-SICs) with a wireless test port. The two architectures use different test wrappers and TAMs, while the stack is partitioned into two subsets in both schemes. By testing the subsets simultaneously using the wired test port and the wireless test port, considerable test time can be saved. Optimization strategies of the two DfT architectures are discussed, and the total test time is estimated. Experimental results of both proposed optimal DfT architectures show that almost half of the total test time can be saved comparing with that of IEEE p1838 architecture.

Differential Power Analysis (DPA) reveals the secret key from the cryptographic device by side channel power leakage. Masking and Random Delay Insertion (RDI) are two countermeasures against DPA attack. But masking or RDI alone does not prevent DPA attack, they only enhance the difficulty of the attack. This paper proposes a novel countermeasure which associating masking with RDI. Furthermore, multi-masking instead of transformed masking is proposed in order to defend DPA attack based on hamming distance model. The combined countermeasure is implemented and verified on Data Encryption Standard (DES) algorithm. The results show that the combined countermeasure defends DPA attack with 105 power traces, and increases 40% ability against DPA with only 28% performance penalty.

This paper proposes a low-voltage power amplifier for the 3.0–5.0 GHz ultra-wideband applications. Based on the classical current-reused technique, it adopts a folded topology to achieve the low-voltage working with acceptable output linearity. Its two-stage amplifying configuration consists of only one NMOS and one PMOS transistors. Implemented in the 0.18 µm CMOS technology, it obtains a gain as high as 16 dB with only ±0.5 dB flatness over the full working band, and consumes only 23.2 mW with 0.75mm2 size under 1.2 V.