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We present, in this paper, a non-conservative approach for building reliable magnetic field sensors based on the resistive and magnetoresistive responses of a varistor diode. These sensors can be built on a ceramic platform of a material which is a solid solution of the ilmenite–hematite consisting of 55 moles% ilmenite, FeTiO3, and 45 mole% of hematite, Fe2O3. This material is abbreviated as IHC 45. These sensors would be suitable for many applications in which a semiconductor Hall effect sensor is currently used. In addition, our ceramic sensors would be suitable for applications in high temperature, energy exploration and well logging, and radiation-dominant environments. The resistive mode sensor is expected to operate reliably and efficiently over the range of 0 $\text{m}\Omega $ /Oe at 0.5 mA which drops to a value of 24.2 $\text{m}\Omega $ /Oe at 2 mA. In the magnetoresistive mode, the sensor has the sensitivity of $142.6~\Omega $ /ln(Oe) and it is 15.6 $\text{m}\Omega $ /Oe at 2 mA. The magnetoresistive mode device also exhibits at room temperature a relatively large magnetoresistive ratio (MR%) of 57% at the modest field of just 4000 Oe making it potentially an attractive candidate for applications in spintronics and magneto-electronics.

A large-signal circuit model is used to compute the switching time for double-barrier resonant-tunneling diodes. The model consists of linear circuit elements plus a nonlinear $I$ – $V$ characteristic. The linear elements include a series resistor, a capacitor, and an inductor. The capacitance considers the charge accumulation, depletion in spacer layers, as well as charging-discharging of the quantum-well (QW) region. The inductance accounts for the delay of the current with respect to the voltage across the QW during the abrupt switching transition through the negative differential resistance region. A second-order Runge–Kutta method is used to solve for the switching transient, and then fit to experimental data for a high-quality InGaAs/AlAs resonant tunneling diode (RTD) using the QW inductance as a fitting parameter. Excellent agreement is found for the 10%–90% switching time with a calculated capacitance of 98 fF and a fitted inductance of 1300 pH. This large-signal inductance is approximately $7\times $ greater than the small-signal inductance that has been successfully used to predict the fmax of RTDs such as the one tested here.

We report on the use of SrTiO3 films on GaAs(001) substrates grown by molecular beam epitaxy (MBE) as intermediate buffer layers for the heteroepitaxial growth of ferromagnetic La0.7Sr0.3MnO3 (LSMO) and room temperature multiferroic (ferroelectric/antiferromagnetic) BiFeO3 (BFO) thin films using the pulsed laser deposition technique. The exchange bias coupling effect in the BFO/LSMO heterostructure has been investigated. The magnetization measurements with field cooling exhibit a surprising increment in the magnetic moment with enhanced magnetic hysteresis squareness. This we believe is the consequence of exchange interactions between the antiferromagnetic BFO and the ferromagnetic LSMO at the interface. The integration of BFO materials with LSMO on GaAs substrates facilitated the demonstration of resistive switching based non-volatile memory (NVM) devices which can be faster with lower energy consumption compared to present commercial technologies. Ferroelectric switching observations using piezoresponse force microscopy show polarization switching demonstrating its potential for read–write operation in NVM devices. The ferroelectric and electrical characterization exhibits strong resistive switching with low set/reset voltages. Furthermore, we demonstrate a prototypical epitaxial field effect transistor based on multiferroic BFO as the gate dielectric and ferromagnetic LSMO as the conducting channel. The device exhibits a modulation in channel conductance with a high ON/OFF ratio. This work also demonstrates the first step towards the development of magneto-electronic devices integrated with a compound semiconductor.

Display Omitted Single crystal ferroelectric oxides deposited GaAs.Molecular beam epitaxy of crystalline SrTiO3 and BaTiO3 on GaAs.Crystalline PZT was deposited on STO/Si and STO/GaAs using solution spin coating.DFT calculations were used to determine properties of oxide/semiconductor interfaces. The integration of ferroelectric oxides on semiconductors has been achieved through the use of molecular beam epitaxy and solution spin coating. The oxide layers were determined to be single phase and crystalline and were oriented with the (100) along the growth direction. Epitaxial SrTiO3 and BaTiO3 buffer layers were grown on GaAs and Si using a unique MBE process for nucleation that suppressed the formation of interfacial oxide. The deposition of ferroelectric Pb(Zr)TiO3, on STO buffered Si and GaAs was carried out using solution spin coating. The nucleation of the oxide growth by solution spin coating was promoted by the crystallinity of the surface structure of the SrTiO3 buffer layer. Ab initio Density Functional Theory calculations were used to determine the interfacial structure and band alignments for the STO/GaAs and BTO/GaAs interfaces. Initial electrical characterization of the PZT grown on GaAs was determined by measuring the polarization versus electric field which suggests evidence of ferroelectricity.

β-Ga2O3 thin films were grown on c-plane sapphire substrates by plasma-assisted molecular beam epitaxy. The films were grown using an elemental gallium source and oxygen supplied by an RF plasma source. Reflection high-energy electron diffraction (RHEED) was used to monitor the surface quality in real time. Both in situ RHEED and ex situ X-ray diffraction confirmed the formation of single crystal β-phase films with excellent crystallinity on c-plane sapphire. Spectroscopic ellipsometry was used to determine the film thicknesses, giving values in the 11.6–18.8 nm range and the refractive index dispersion curves. UV-Vis transmittance measurements revealed that strong absorption of β-Ga2O3 starts at ∼270 nm. Top metal contacts were deposited by thermal evaporation for I-V characterization, which has been carried out in dark, as well as under visible and UV light illumination. The optical and electrical measurements showed that the grown thin films of β-Ga2O3 are excellent candidates for deep-ultraviolet detection and sensing.

In an era of power-constrained transistor scaling, III-V semiconductors, with high electron velocities, appear promising as the n-channel solution in post-Si CMOS technologies [1]. To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs [1,2]. InGaAs, in particular, has been the centre of extensive research effort. This has led to the development of surface passivation measures capable of significantly minimizing the defects at the gate dielectric/III-V interface [3,4], ultra-low resistance source/drain contact technology [5], III-V heterointegration capability on Si substrates [6] and demonstration of record performing planar MOSFETs suited for high-performance and low-power logic [7-9]. Currently, InGaAs is being primed for entry into CMOS at the 7nm technology node and beyond. However, given the transition to FinFETs in CMOS technology [10], there is a need to develop dry etch processes capable of nanometer-scale fin definition in III-Vs. Key requirements of the dry etch process are vertical sidewalls and minimum etch damage. The former provides for efficient device electrostatics while the latter is required for a high quality sidewall MOS interface [11]. However, satisfying both criteria is challenging. Highly anisotropic dry etching required for sidewall verticality is more damaging due to the physical nature of the process. Unlike Si, the induced damage cannot be cured by post etch annealing in III-Vs [1]. In this talk we will first report on the dry etch processing systematically investigated for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. Fins were etched in InGaAs, masked with HSQ of nanometric linewidths, for a variety of dry etch gas chemistries using either a RIE or an ICP process. A fin profile within 3¢ª of vertical was achieved with an ICP etch process based around Cl2/CH4/H2 gas chemistry (Fig. 1a). Highly vertical 10nm fins with 16:1 aspect ratio, perhaps the highest aspect ratio, smallest critical dimension fins to date in InGaAs, have also been demonstrated using this chemistry (Fig. 1b). Impact of the various ICP processes were assessed on Al2O3/InGaAs(100) MOS capacitors subject to blanket etch processing prior to (NH4)2S wet treatment and ALD gate dielectric. Despite the promising fin profile, the Cl2/CH4/H2 based ICP process yielded a severely degraded CV characteristic, featuring a peak Dit that is ~5x higher than the control (unetched) sample (Fig. 2). TEM and AFM were used to further elucidate the impact of the various ICP etch processes on the physical properties of the Al2O3/InGaAs interface. The second part of the talk will focus on the mitigation of etch-induced sidewall damage via dry etch process optimization and sidewall passivation techniques. It will be demonstrated that the modification of Cl2/CH4/H2 gas chemistry to include O2 results in the substantial reduction of etch-induced damage, due to the lowering of the ICP power. A near-vertical sidewall profile similar to that obtained for the etch chemistry without O2 is further retained. Some examples of nanowires realized using this gas chemistry will also be shown. The sidewall damage arising from Cl2/CH4/H2/O2 etch chemistry will be assessed on both (100) and (110) oriented InGaAs. To alleviate the damage two post-etch sidewall passivation schemes were explored. The first was based on a photon-assisted hydrogenation process developed by Amethyst Research Inc., applied post-etch or post ALD high-k, and was investigated on Al2O3/InGaAs(100) MOS capacitors subject to Cl2/CH4/H2 blanket etch. The CV results indicated a larger reduction of etch damage for hydrogenation done post ALD high-k (Fig. 3). In the second approach, a wet “digital” etch surface clean was applied following a Cl2/CH4/H2/O2 blanket etch, resulting in a complete recovery of etch damage as determined from CV characteristics of Al2O3/InGaAs(100) MOS capacitor. The process was also investigated for (110) oriented InGaAs. Details of the passivation schemes and the associated results will be discussed further. References [1] J. del Alamo, Nature, 479, 317 (2011). [2] S. Oktyabrsky et al., IJHSES, 18, 761 (2008). [3] P.K. Hurley et al., IEEE T-DMR, 13, 429 (2013). [4] V. Chobpattana et al., JAP, 116, 124104 (2014). [5] R. Oxland et al., IEEE EDL, 33, 501 (2012). [6] R.J.W. Hill et al., IEEE IEDM, 2010. [7] S. Lee et al., VLSI Symp., 2014. [8] C.Y. Huang et al., IEEE IEDM, 2014. [9] S.W. Chang et al., IEEE IEDM, 2013. [10] C.C. Wu et al., IEEE IEDM, 2010. [11] X. Zhao et al., IEEE EDL, 35, 521 (2014). Figure 1

The impact of scaling on off-state current of p-i-n diodes is studied. A sub-micron p-i-n diode exhibits a dominating surface component of leakage current. Variation in i-layer thickness has an impact on bulk leakage. Bulk leakage scales with cross-sectional area of the diode and surface leakage has been controlled using surface treatments to give ultra low leakage currents of 210 fA for a device of cross sectional area of 0.44 μ m2. Devices of 100 nm i-layer thickness show an average bulk and surface current densities of 100 mA/cm2 and 150 fA/ μ m, respectively.

The integration of III–V compound semiconductors with Si can combine the cost advantage and maturity of Si technology with the superior performance of III–V materials. We have achieved the heteroepitaxial growth of III–V compound semiconductors on a crystalline SrTiO 3 buffer layer grown on Si(0 0 1) substrates. A two-step growth process utilizing a high temperature nucleation layer of GaAs, followed by a low-temperature GaAs layer at a higher growth rate was employed to achieve highly crystalline thick GaAs layers on the SrTiO 3 /Si substrates with low surface roughness as seen by AFM. The effect of the GaAs nucleation layer on different surface terminations for the SrTiO 3 layer was studied for both on axis and miscut wafers, which led to the conclusion that the Sr terminated surface on miscut substrates provides the best GaAs films. Using GaAs/STO/Si as virtual substrates, we have optimized the growth of high quality GaSb using the interfacial misfit (IMF) dislocation array technique. This work can lead to the possibility of realizing infrared detectors and next-generation high mobility III–V CMOS within the existing Si substrate infrastructure.

In0.53Ga0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In0.53Ga0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III–V on Si sample and the control that perform similarly below $8.6 \times 10^{-10}$ cm $^{2}$ . The existence of a critical device area suggests the potential to utilize III–V on Si for other deeply scaled tunnel devices.

Frequency (100 ${\rm Hz}\le f \le 1$ MHz) and temperature ( $- 50 \le T \le 20^{\circ }\text{C}$ ) characteristics of low interface state density $D_{\rm {it}}$ high- $\kappa $ gate-stacks on n-InAs have been investigated. Capacitance–voltage ( $C$ – $V$ ) curves exhibit typical accumulation/depletion/inversion behavior with midgap $D_{\rm {it}}$ of $2\times 10^{11}$ and $4\times 10^{11}$ cm $^{-2}$ eV $^{-1}$ at −50 °C and 20 °C, respectively. Asymmetry of low-frequency s $C$ – $V$ curves and $C$ – $T$ dependence for negative voltage showing a sharp transition of $\cong -20$ dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length $L_{g} =$ 1 $\mu \text{m}$ , channel thickness = 10 nm, and equivalent oxide thickness (EOT) $1 \le {\rm EOT} \le 1.6$ nm have been fabricated. For ${\rm EOT} = 1$ nm, a subthreshold swing $S = 65$ mV/decade, transconductance $g_{m} =1.6$ mS/ $\mu \text{m}$ , and ON-current $I_{{\mathrm{{\scriptscriptstyle ON}}}} =$ 426 $\mu \text{A}/\mu \text{m}$ at an OFF-current $I_{{\mathrm{{\scriptscriptstyle OFF}}}} =100$ nA/ $\mu \text{m}$ (supply voltage $V_{\rm {dd}} =$ 0.5 V) have been measured. Peak electron field-effect mobilities of 6000–7000 cm $^{2}$ /Vs at sheet electron densities of 2– $3\times 10^{12}$ cm $^{-2}$ were obtained for EOT as small as 1 nm.

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

We investigate the effects of pre- and postatomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial capability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is correlated with a significant hysteresis. This appears to be caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. On the other hand, intentional air exposure of the InGaAs surface prior to Al2O3 ALD increases the initial interface trap density (Dit) but considerably lowers the hysteresis. Fil: Tang, Kechao. University of Stanford; Estados Unidos Fil: Palumbo, Félix Roberto Mario. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica. Gerencia del Área Investigaciones y Aplicaciones no Nucleares; Argentina. Universidad Tecnológica Nacional; Argentina Fil: Zhang, Liangliang. University of Stanford; Estados Unidos Fil: Droopad, Ravi. University of Texas; Estados Unidos Fil: McIntyre, Paul C.. University of Stanford; Estados Unidos

A major obstacle facing III-V semiconductor based metal oxide semiconductor field effect transistors (MOSFETs) is the large density of trap states that exist at the semiconductor/oxide interface.[1] These trap states can pin the Fermi level preventing the MOSFET from acting as a switch in logic devices. Several sources of Fermi level pinning have been proposed including oxidation of the III-V substrate.[2, 3] In order to minimize the presence of III-V oxides it is crucial to employ either an ex-situ etch or to use an in-situ method such as atomic hydrogen cleaning.[4, 5] Although atomic H cleaning of III-V surfaces is well known, it has never been demonstrated on InGaAs (110) crystallographic faces. Furthermore, tri-gate field effect transistors (finFETs) have recently been employed in commercially available logic chips.[6] This unique device architecture allows for a reduction in short channel effects, minimization of the subthreshold swing, and a higher transconductance.[7] The InGaAs (110) surface would be the sidewalls of a vertically aligned (001) based finFETs.[8] Therefore, it is essential to find an in-situ method to efficiently remove any oxides or contamination from the (110) surfaces that is also compatible with the (001) surface. In this study, STM was employed to determine if atomic hydrogen can be used to remove the native oxide from air exposed InGaAs (110) samples. A post clean anneal was used to restore the surface to molecular beam epitaxy (MBE) levels of cleanliness.

Growing good quality III–V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective way. In this paper, using physical analysis and electrical measurements of Esaki diodes, fabricated using molecular beam epitaxy grown ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ layers on Si substrate, we show that the valley current density is strongly correlated with the underlying epi defect density. Such a strong correlation indicates that the valley characteristics can be used to monitor the epi quality. A model is proposed to explain the experimental observations and is validated using multiple temperature diode $I{-}V$ data. An excess defect density is introduced within the device using electrical and mechanical stress, both of which are found to have a direct impact on the valley current with a negligible change in the peak current characteristics, qualitatively supporting the model predictions.

Oxide multilayer heteroepitaxy combining Mott-insulator vanadium dioxide (VO2) films and functional conducting/ferroelectric/dielectric films opens new opportunities in creating functional devices with applicability in the field of nonvolatile memories for neuromorphic devices. The growth of high quality VO2 films is challenging due to the necessity of precise control of the vanadium cation valence state. In this study, the authors report on electrical and structural properties of VO2 thin films deposited on various single crystal oxide substrates commonly used in oxide electronics and on PbZrxTi(1−x)O3/SrRuO3 ferroelectric heterostructures deposited on SrTiO3 and GaScO3 single crystal substrates. The optimized VO2 films exhibit a metal-to-insulator phase transition on all applied substrate/film combinations.

Single crystal SrTiO3 layers were grown on GaAs using both molecular and atomic oxygen and the interfaces were probed using room temperature photoluminescence and in-situ X-ray photoemission spectroscopy. The increase in PL intensity for the oxide/GaAs structure in which molecular oxygen was used suggest a decrease in the density of interfacial defects resulting in some level of Fermi level unpinning. When atomic oxygen was used during growth the interface appears to have an increase in the density of defects and a pinned Fermi level similar to that of a GaAs layer with a native oxide. X-ray photoemission measurements indicate an increase in the Ga–O bonding at the interface when the plasma source was used with an addition of As–As bonding not present in the sample grown using molecular oxygen. These results suggest the possibility of using a crystalline oxide as a gate dielectric in III–V MOSFET devices.

Graphical abstractDisplay Omitted Single crystal ferroelectric oxides were grown on both Si and GaAs.Molecular beam epitaxy of BaTiO3 using molecular oxygen.STEM reveals oxide/GaAs interface is more stable to reaction with diffused oxygen.PFM and PFS measurements demonstrate ferroelectricity on both Si and GaAs substrates. Epitaxial ferroelectric BaTiO3 layers were deposited on both Si and compound semiconductor substrates using molecular beam epitaxy. The films were grown using molecular oxygen and were found to be c-axis oriented as determined from X-ray diffraction measurements. High resolution transmission electron microscopy indicated the interface between the oxide and GaAs is free of structural defects while a thick layer of amorphous SiO2 layer is present at the interface of the oxide and Si. Ferroelectric properties of the BaTiO3 films were measured using piezoresponse force microscopy and spectroscopy. The BTO films show a piezoresponse amplitude ~5pm/V, and a coercive voltage of Vc=1-2V with an as-grown polarization along the growth direction consistent with TEM observations.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As 4 with a slight increase using As 2 . High structural quality lattice matched AlAs x Sb 1− x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAs x Sb 1− x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100 arcsec. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12–15 nm are demonstrated. I on = 314 µA/µm, and S sat =68 mV/dec was achieved at V dd = 0.5 V (I off = 0.1 µA/µm). Highest g m measured is 2693 µS/µm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g m , R on , and I min are discussed.

Metal oxide semiconductor field effect transistors (MOSFETs) are diverging from the exclusive use of silicon and germanium to the employment of compound semiconductors such as SiGe and InGaAs to further increase transistor performance. A broader range of channel materials allowing better carrier confinement and higher mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Silicon uniquely bonds strongly to all crystallographic faces of InGa1−xAs, InxGa1−xSb, InxGa1−xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may subsequently be passivated by atomic hydrogen. Subsequently, the surface may be functionalized with an oxidant such as HOOH(g) in order to create a UCM terminating Si-OH layer, or a nitriding agent such as N2H4(g) in order to create an Si-Nx diffusion barrier and surface protection layer. This study focuses on depositing saturated Si-Hx, and Si-OH seed layers via two separate self-limiting CVD processes on InGaAs(001)−(2x4), and depositing a Si-Nx seed layer on Si0.5Ge0.5(110) via an ALD process. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of these silicon containing control layers on InGaAs(001)−(2x4) and Si0.5Ge0.5(110) surfaces. MOSCAP device fabrication was performed on n-type InGaAs(001) substrates with and without a Si-Hx passivation control layer deposited by self-limiting CVD in order to determine the effects on Cmax, frequency dispersion, and midgap trap states.

Electrical interface quality of various high- k dielectrics on GaSb, including Al2O3, HfO2, LaAlO3, GdScO3, and HfO2/Ga2O3 bilayer has been studied and compared with reference low (AlGaSb) and high Dit (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al2O3 and HfO2/Ga2O3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×104 cm/s) and consequently Dit integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low Dit AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

The suitability of oxide/GaAs interfaces for MOSFET applications has been investigated. Electrical properties of Ga2O3/GaAs interfaces, dielectric stacks utilizing the Ga2O3/GaAs interface, and Al2O3/GaAs interfaces have been studied using a set of independent techniques, including admittance-voltage (ac C-V and G-V at 25°C and 150°C), quasi-static static C-V, photoluminescence intensity (PL-I), and MOSFET I-V measurements. The side-by-side comparison reveals the fundamental differences in their respective data sets. The GdGaO/Ga2O3/GaAs system has been found to exhibit a U-shaped Dit distribution with a midgap Dit plateau of 2 - 3 × 1011 cm-2 · eV-1, which has allowed manufacturing GaAs MOSFETs with dc performance close to ideal model predictions. Some other ternary oxides such as GdScO3 and LaAlO3 can also be deposited on a Ga2O3 template without disrupting the Ga2O3/GaAs interface. Beyond GaAs bulk, the use of a surface heterostructure has been investigated, which shifts, in energy space, the mobile charge distribution in the channel layer away from a branch of rising Dit in the vicinity of Ec at the Ga2O3/GaAs interface. In contrast, Al2O3/GaAs(100) interfaces show a typical GaAs native oxide behavior with a

We study the reliability of Al2O3/InGaAs metal-oxide-semiconductor gate stacks by investigating the effect of bias temperature stress on the charge trap density at the Al2O3/InGaAs interface and in the bulk oxide. Under extended negative biasing at 100 °C, the gate stacks display a notable increase in the interface trap density (Dit), but little change in the border trap density. This phenomenon is more prominent for samples exposed to a H2/N2 forming gas anneal (FGA) than for the as-deposited samples. Negative gate bias applied during 100 °C thermal stress negates the FGA-induced passivation of interface states and causes convergence of the Dit of the post-FGA and as-deposited gate stacks with increasing biasing time. This appears to be caused by hydrogen depassivation of interface traps under bias temperature stress, which is further supported by an observed hydrogen isotope effect when comparing the rate of Dit increase after annealing in hydrogenated versus deuterated forming gas. A N2 anneal control ...

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) (1) to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. A wide range of high electron mobility channel materials, device architectures and gate oxides are currently being considered, and in this review, key performance metrics of III-V MOSFETs will be compared.

Enhancement mode, high electron mobility PHEMT-based metal oxide semi conductor field effect transistor (MOSFET) devices have been fabricated using an oxide high- κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga 2 O 3 , initially deposited on the surface of the III–V device unpins the GaAs Fermi level while the deposition of a bulk ternary ( Gd x Ga 1 - x ) 2 O 3 layer forms the highly resistive layer to reduce leakage current through the dielectric stack. The use of molecular beam epitaxy allows for the control and uniformity of the oxide layers along the growth direction and deposition conditions were optimized for oxide surface morphology and interface quality. A midgap interface state density for the high- κ stack on GaAs of ≅ 2 × 10 11 cm - 2 eV - 1 and a dielectric constant of κ ≅ 20 are determined using electrical measurements. Enhancement-mode n -channel MOSFETs with a gate length of 1 μ m and a source-drain spacing of 3 μ m show a threshold voltage, saturation current, transconductance, and on-resistance of 0.11 V, 380 mA mm - 1 , 250 mS mm - 1 , and 4.5 Ω mm , respectively.

Based on sulphur passivation (10% (NH 4 ) 2 S, 20min), the interface of MOS capacitors between atomic-layer-deposited Al 2 O 3 and (110)-oriented p-type In 0.53 Ga 0.47 As layers indicate the capability of Fermi level movement and minority carrier inversion. C ox has effectively extracted by G m /ω & − ωdC/dω. Forming gas annealing (N 2 :H 2 5%:95% at 350°C, 30min) improves minority carrier response and the interface trap density around the midgap estimated to be 4.4×1012(1.6×1012) cm−2 eV−1 before (and after) FGA. Moreover, Fowler-Nordheim (FN) tunneling current provides the conduction band offset at the surface between Al 2 O 3 and In 0.53 Ga 0.47 As (110)-oriented layer is ∼1.81eV and the barrier height is estimated to be the same after FGA. Finally, the band parameter of Al 2 O 3 and In 0.53 Ga 0.47 As (110)-oriented layer has been firstly reported

In-situ atomic imaging of cleaning and passivation of several systems has been studied. (1) For InGaAs (001), a low temperature in-situ cleaning process has been combined with low temperature HfO 2 ALD to reduce the EOT below 0.4 nm. (2) For InGaAs (110), STM/STS studies have shown that both a metal precursor (TMA) and an oxidant (H2O) are required to remove trap states. (3) To assist in utilizing similar gate and contact processing on group IV and InGaAs surfaces, a silicon monolayer ALD process has been developed for InGaAs (001). (4) SiGe combines the most challenging components of cleaning Si and Ge; using a reaction with HOOH (g) and post deposition annealing, SiGe (001) becomes terminated with Si-OH which is nearly ideal for ALD nucleation.

In 0.53 Ga 0.47 As contains an intrinsically high electron mobility making it an attractive alternative semiconductor material for use in the channel region of MOSFET devices[1]. The semiconductor/oxide interface can degrade device performance through interfacial roughness or formation of surface defects containing electronic trap states that act to pin the surface Fermi level[2]. Tri-gate structured field effect transistors (finFETs) are currently being implemented into commercialized logic chips, making defect reduction and passivation of the semiconductor planar and sidewall crystallographic faces critical in order to create an ideal interface between the semiconductor and the gate oxide. For InGaAs(001) based finFETs to become potential for commercial implementation, in-situ III-V surface cleaning or defect passivation techniques must be compatible with both the InGaAs (001) and (110) surfaces. STM was employed to show air exposed InGaAs (001) and (110) samples can be restored to the cleanliness of MBE grown samples through atomic hydrogen dosing and thermal annealing. STM was also employed to characterize the in-situ self-limiting CVD of a silicon hydride control layer used to passivate the missing dimer defect unit cells of the arsenic rich InGaAs(001)-(2×4) surface. Surface defect densities are compared and quantified throughout several STM images following the surface cleaning and passivation techniques.

The role of ferroelectric LiNbO3 (LNB) in altering the frequency dependence of the capacitance of CaCu3Ti4O12 (CCTO) thin films has been investigated. A cost effective spin coating deposition process was used to integrate the oxide heterostructures onto silicon substrates. This study showed that the frequency stability of the CCTO/LNB structure was much improved when the crystallization conditions and physical dimension of each layer were optimized. To integrate this structure with current silicon technology, heterostructures of CCTO and LNB thin films were fabricated on HF terminated Si using chemical solution deposition. It was found that the order of deposition of the two layers was important for the structural quality of the heterostructures with the CCTO layer followed by the LNB layer being the preferred structure. In addition to improvement of the capacitance variation with frequency, the heterostructures also provide a path to tuning the frequency of operation.

This letter introduces the first enhancement-mode GaAs n-channel MOSFETs with a high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The NMOSFETs feature an In0.3Ga0.7 As channel layer, a channel mobility of up to 6207 cm2/Vmiddots, and a dielectric stack thickness of 13.1-18.7 nm. Enhancement-mode NMOSFETs with a gate length of 1 mum, a source/drain spacing of 3 mum, and a threshold voltage of 0.05 V show a saturation current, transconductance, on-resistance, and subthreshold swing of 243 mA/mm, 81 mS/mm, 8.0 Omegamiddotmm, and 162 mV/dec, respectively

Principles of operation of implant-free enhancement-mode MOSFETs (flatband MOSFET) are discussed. Epitaxial-layer structures designed for use in implant-free enhancement-mode devices and employing a high-kappa dielectric (kappacong20) and a strained InGaAs channel layer with a thickness of 10 nm have been manufactured on GaAs substrate. Proceeding from measured electron mobility mu as a function of the sheet-carrier concentration, enhancement-mode design considerations, saturation current IDss, and mobility requirements are discussed using two-dimensional device simulations. For the flatband MOSFET to compete successfully with other device designs, certain minimum channel mobilities are required. For RF applications, mu should exceed 5000 cm2/Vs while high-performance MOSFETs for digital applications may require even higher mobility for optimum operation. Finally, measured data of first 1-mum-GaAs-flatband enhancement-mode MOSFETs are presented; the saturation velocity of the InGaAs channel layer is derived; and measured IDss data are compared to the results obtained by simulations

Heteroepitaxy of thin films of perovskite type oxides have been demonstrated on silicon (100) substrates by molecular beam epitaxy. RHEED has been used extensively to calibrate the relative fluxes and also to monitor the growing surface and adjust the stoichiometry during deposition. SrTiO 3 (STO) grows epitaxially on silicon with SrTiO 3 (001)//Si(001) and SrTiO 3 [l 00]//Si[1 10]. By optimising the deposition parameters, a crystalline transition across the oxide/Si interface can be obtained. An amorphous SiO 2 interfacial layer can also be formed between the oxide and silicon substrate during the deposition as a result of oxygen diffusion through the oxide layer. By adjusting the deposition parameters, the thickness of the amorphous layer can be controlled. The SrTiO3/Si substrate can be used as a pseudo-substrate for deposition of a number of other oxides or semiconductors for multifunctional device applications.

The growth of high quality epitaxial beta-gallium oxide (β-Ga2O3) using a compound source by molecular beam epitaxy has been demonstrated on c-plane sapphire (Al2O3) substrates. The compound source provides oxidized gallium molecules in addition to oxygen when heated from an iridium crucible in a high temperature effusion cell enabling a lower heat of formation for the growth of Ga2O3, resulting in a more efficient growth process. This source also enabled the growth of crystalline β-Ga2O3 without the need for additional oxygen. The influence of the substrate temperatures on the crystal structure and quality, chemical bonding, surface morphology, and optical properties has been systematically evaluated by x-ray diffraction, scanning transmission electron microscopy, x-ray photoelectron spectroscopy, atomic force microscopy, spectroscopic ellipsometry, and UV-vis spectroscopy. Under optimized growth conditions, all films exhibited pure 2¯01 oriented β-Ga2O3 thin films with six-fold rotational symmetry when grown on a sapphire substrate. The thin films demonstrated significant absorption in the deep-ultraviolet (UV) region with an optical bandgap around 5.0 eV and a refractive index of 1.9. A deep-UV photodetector fabricated on the high quality β-Ga2O3 thin film exhibits high resistance and small dark current (4.25 nA) with expected photoresponse for 254 nm UV light irradiation suggesting that the material grown using the compound source is a potential candidate for deep-ultraviolet photodetectors.

Thin films of perovskite-type oxide SrTiO 3 have been grown epitaxially on Si(001) substrates using molecular beam epitaxy. Using reflection high energy electron diffraction (RHEED) we have determined the optimum growth conditions for these type of oxides directly on silicon. Also, observations of RHEED during growth and X-ray diffraction (XRD) analysis indicate that high quality heteroepitaxy on Si takes place with SrTiO 3 (001)//Si(001) and SrTiO 3 [010]//Si[110]. Thin SrTiO 3 layers grown directly on Si were used as the gate dielectric for the fabrication of MOSFET devices. An effective oxide thickness < 10 A has been obtained for a 110 A thick SrTiO 3 dielectric film with interface state density around 6.4 x 10 10 cm -2 eV -1 , and the inversion layer carrier mobilities of 220 and 62 cm 2 V -1 s -1 for NMOS and PMOS devices, respectively.

Recently, we have grown epitaxial BaTiO3 films directly on a Si (001) substrate using molecular beam epitaxy (MBE). The films have been characterized both physically (RHEED, XRD, AFM, SE) and electrically (CV & IV). The films show streaky RHEED patterns and sharp X-ray diffraction patterns, indicating epitaxial BTO growth. The leakage current is below 1E-8 A/cm2 at 2V. The CV results show good interface properties. The films exhibit a 0.5V hysteresis in the CV curves.

Photoluminescence intensity (PL-I) data are presented for 22 dielectric/GaAs systems investigated for MOSFET applications. The PL-I technique has been identified as a most useful and reliable tool for screening dielectric/GaAs interfaces and has been instrumental in the identification of a device quality dielectric/GaAs interface: in situ deposited Ga2O3 on GaAs. The early discovery of such an interface has allowed us to focus resources and to succeed to manufacture GaAs MOSFETs which perform in line with theoretical model predictions after more than 40 years of failed attempts. It is strongly recommended to extend the technique to the investigation of CMOS relevant channel materials such as InGaAs.

Contactless electroreflectance at 300 K has been used to characterize an InGaAs/GaAs/AlGaAs vertical-cavity surface-emitting laser test structure, i.e. three InGaAs quantum wells (QWs) placed in a GaAs/AlGaAs resonant cavity. The three observed resonances from the InGaAs QWs have made it possible to evaluate the well width and In composition. The 1020 nm lasing spectrum correlates very well with the energy of the lowest lying QW feature. Also, the built-in electric field in the structure has been determined from the Franz-Keldysh oscillations in the GaAs signal. Furthermore, there is some evidence for Be interdiffusion into the QW region.

Hetero-epitaxy of single-crystal perovskite SrTiO3 on GaAs(001) was achieved using molecular beam epitaxy. The growth was accomplished by deposition of a submonolayer of titanium on GaAs(001), followed by the co-deposition of strontium and titanium initiated at a low-temperature, low-oxygen-pressure condition. X-ray photoelectron spectroscopy showed that the Ti prelayer reacted with As and formed TiAs-like species on the As terminated GaAs(001) surface. Reflection-high-energy-electron diffraction showed that SrTiO3 grew coherently on the GaAs(001) at early stage of growth. This coherent behavior began to degrade when SrTiO3 thickness exceeded 20A. Cross-sectional transmission electron microscopy revealed an abrupt interface between SrTiO3 and GaAs and good crystallinity of the SrTiO3 film. An epitaxial relationship between SrTiO3 and GaAs was further confirmed by x-ray diffraction. The success of growth of SrTiO3 on GaAs paves the way for integration of various functional perovskite oxides with GaAs.

The paper deals with the integration of well-known bismuth ferrite (BiFeO3) multiferroic oxide with GaAs semiconductor. First 5 nm ultrathin SrTiO3 films were grown on GaAs (001) substrates as an intermediate buffer layer by molecular beam epitaxy. Then, room temperature multiferroic BiFeO3 (BFO) thin films were deposited by pulsed laser deposition. X-ray diffraction measurement showed high quality epitaxial BFO films with pure (00l) orientation. The dielectric loss has been effectively suppressed and the saturated polarization–voltage (P–V) hysteresis loops were obtained. The ferroelectric domains switching was affirmed by piezo-response force microscopic studies. A large remnant polarization P r (~80 μC cm−2) combined with the enhanced magnetization (72 emu cm–3) at 300 K was achieved for the optimal growth conditions. The optical properties were measured using the ellipsometry technique for the BFO thin films. The thickness and optical constants of the BFO films were obtained by taking into consideration the dielectric parameters as described by the Tauc-Lorentz model. Finally, direct bandgap was estimated at 2.70 eV which is highly comparable to BFO films grown on different substrates.

Spectroscopic ellipsometry’s (SE’s) strength as an in situ semiconductor crystal growth process diagnostic lies in the fact that the material’s dielectric properties (pseudodielectric functions) are dependent upon temperature and alloy composition. These dependencies can be exploited to monitor and control epitaxial growth in real time. This article reviews several aspects of growth and control of III–V semiconductors grown at Arizona State University by molecular beam epitaxy (MBE) using SE. Chamber and manipulator design considerations for implementing SE on a MBE and a gas source MBE with substrate rotation will first be discussed. A commercially available ‘‘ellipsometer‐ready’’ MBE system will then be described. It will then be shown that a MBE process can be established without conventional analysis tools such as reflection high energy electron diffraction. Measurement and control of substrate temperature by SE will be shown. This is possible by using the temperature‐dependent pseudodielectric functions for GaAs and AlGaAs which we have measured. Calibration of MBE growth will be discussed including in situ measurement of oxide desorption, V/III flux ratio, growth rate, and alloy composition measurements. Tracking the growth of the epitaxial layer provides information on thickness, alloy composition, and surface roughness. Algorithms for deconvoluting these effects from the data will be discussed. Finally, examples of structures used in optoelectronic devices will be presented including quantum well thickness control and microcavity laser device growth.

A low resistance PdGe nonalloyed ohmic contact has been successfully formed to epitaxially lifted-off n-type GaAs films. The contact is made by lifting off partially metallized n-type GaAs films using the epitaxial lift-off method and bonding them to metallized Si substrates by natural intermolecular Van Der Waals forces. Low temperature sintering (200°C) of this contact results in metallurgical bonding and formation of the ohmic contact. We have measured specific contact resistances of 5 × 10−5 Ω-cm2 which is almost half the value obtained for pure Pd contacts. Germanium forms a degenerately doped heterojunction interfacial layer to GaAs. Our experimental results show that germanium diffuses to the interface and acts as a dopant layer to n-GaAs film surface. Therefore, for epitaxially lifted-off n-type GaAs films, PdGe is a low resistance ohmic metal contact to use.

The superior transport properties of III–V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III–V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj

The integration of functional oxide thin-films on compound semiconductors can lead to a class of reconfigurable spin-based optoelectronic devices if defect-free, fully reversible active layers are stabilized. However, previous first-principles calculations predicted that SrTiO3 thin films grown on Si exhibit pinned ferroelectric behavior that is not switchable, due to the presence of interfacial vacancies. Meanwhile, piezoresponse force microscopy measurements have demonstrated ferroelectricity in BaTiO3 grown on semiconductor substrates. The presence of interfacial oxygen vacancies in such complex-oxide/semiconductor systems remains unexplored, and their effect on ferroelectricity is controversial. Here, we use a combination of aberration-corrected scanning transmission electron microscopy and first-principles density functional theory modeling to examine the role of interfacial oxygen vacancies on the ferroelectric polarization of a BaTiO3 thin film grown on GaAs. We demonstrate that interfacial oxygen ...

This study entails a comparison of the broken-gap InAs/GaSb heterojunction system on two different substrates, including Si and native GaSb as a control. Through the use of different integration schemes such as AlSb and SrTiO3 buffer layers, GaSb was grown on miscut Si substrates using solid-source molecular beam epitaxy. The InAs/GaSb p+-i-n+ heterostructures were grown on the GaSb/Si virtual substrates and compared in terms of their surface morphology and crystalline quality. Esaki tunnel diodes were fabricated, and their performance compared across the different integration platforms. The control sample shows the best peak current density of 336 kA/cm2 and a conductance slope of 274 mV/decade compared to the broken-gap junction on SrTiO3/Si and AlSb/Si virtual substrates. These results show the possibility of integrating the InAs/GaSb system in ultralow power tunnel field-effect transistors logic applications with the cost-effectiveness and maturity of the silicon technology.

In this letter, self-switching nanochannels have been proposed as an enabling technology for energy gathering in the terahertz (THz) regime. Such devices combine their diode-like behavior and high-speed of operation in order to generate DC electrical power from high-frequency signals. By using finite-element simulations, we have improved the sensitivity of L-shaped and V-shaped nanochannels based on InAlAs/InGaAs samples. Since those devices combine geometrical effects with their rectifying properties at zero-bias, we have improved their performance by optimizing their shape. Results show nominal sensitivities at zero-bias in the order of 40 V−1 and 20 V−1, attractive values for harvesting applications with square-law rectifiers.

We present the growth and properties of asymmetric triangular quantum wells (ATQWs) involving GaAs/Al 0.3 Ga 0.7 As and strained In x Ga 1-x As by molecular beam epitaxy. Compositional grading was approximated using a superlattice technique and varying the thickness of the ternary material in each «cell». GaAs/AlGaAs ATQWs exhibit narrow low temperature photoluminescence (PL) linewidths of 2 meV for an 11 period 675 A well width. Sub-meV linewidths are obtained for both InGaAs/GaAs rectangular and asymmetric triangular single QWs, indicative of high quality InGaAs material as well as smooth heterointerfaces