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The implementation of current deep learning training algorithms is power-hungry, due to data transfer between memory and logic units. Oxide-based resistive random access memories (RRAMs) are outstanding candidates to implement in-memory computing, which is less power-intensive. Their weak RESET regime is particularly attractive for learning, as it allows tuning the resistance of the devices with remarkable endurance. However, the resistive change behavior in this regime suffers from many fluctuations and is particularly challenging to model, especially in a way compatible with tools used for simulating deep learning. In this work, we present a model of the weak RESET process in hafnium oxide RRAM and integrate this model within the PyTorch deep learning framework. Validated on experiments on a hybrid CMOS/RRAM technology, our model reproduces both the noisy progressive behavior and the device-to-device (D2D) variability. We use this tool to train binarized neural networks (BNNs) for the MNIST handwritten digit recognition task and the CIFAR-10 object classification task. We simulate our model with and without various aspects of device imperfections to understand their impact on the training process and identify that the D2D variability is the most detrimental aspect. The framework can be used in the same manner for other types of memories to identify the device imperfections that cause the most degradation, which can, in turn, be used to optimize the devices to reduce the impact of these imperfections.

Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of the RRAM, switching variability and cycling endurance need to be addressed. This paper presents extensive characterizations of multi-kb RRAM arrays during forming, set, reset, and cycling operations. The relationships among programming conditions, memory window, and endurance features are presented. The experimental results are then used to perform variability-aware simulations of a 128-bit RRAM-based ternary content-addressable-memory (TCAM) macro. The tradeoff among endurance, search latency, and reliability in terms of match/mismatch detection is explored, identifying the programming conditions that allow to obtain a searching speed comparable to static random access memory-based TCAMs (2 ns on average and 3 ns at $3\sigma $ ) while guaranteeing good reliability metrics (with a time ratio of 3000 on average and 150 at $3\sigma $ ).

Phase-Change Memory (PCM) demonstrated to be a mature Non- Volatile Memory technology to address Storage Class Memory (SCM) applications that can be distinguished in memory-type (M-SCM) and storage-type (S-SCM). In this work, we present how aGeSbTe (aGST) alloy can address both SCM types, in particular using Si doping. Thanks to the electrical characterization of 4 kb PCM arrays, we show how Si doping in aGST helps tuning the crystallization dynamic during the programming operations, leading to highly reliable intermediate resistance states. We support our results by TEM analyses and finally we present improved multi-level cell (MLC) operations in Si-doped devices, achieved already with a simple double-step protocol. We demonstrate the aGST alloy suitability for SCM applications: undoped alloy allows targeting M-SCM thanks to its high endurance and high programming speed, whereas Si-doped aGST featuring MLC capability and improved data retention can address S-SCM specifications.

International audience; In this paper, we demonstrate at array level and in industrial like devices, the extreme scaling down to nanometric dimensions of the Phase-Change Memory technology thanks to an innovative Self-Nano-Confined PCM device (SNC PCM). We show how such solution based on an optimized GeN/GeSbTe stack enables programming down to 50 $\mu$A and endurance up to more than 10$^8$ cycles in 4 kb arrays, with the huge advantage of having no dependency on the critical lithography dimension used. We further demonstrate that the high thermal confinement achieved in such extremely confined PCM makes the engineering of the SET pulse becoming fundamental in order to assure a reduced SET resistance drift. Moreover, thanks to physico-chemical analyses and 3D TCAD electro-thermal simulations we demonstrate the Self-Nano-Confined phenomenon, revealing an effective scaling of the PCM down to around 12 nm and how it improves the thermal efficiency of the device thanks to a reduced current density and thermal stress in the system.

International audience; Scaling of planar HfO2-based ferroelectric capacitors is investigated experimentally by varying the capacitor area within 5 orders of magnitude, under the scope of limited thermal budget for crystallization. Both Hf0.5Zr0.5O2 (HZO) and Si-doped HfO2 (HSO) based metal/ferroelectric/metal (MFM) capacitors with 10 nm dielectric film thickness and TiN electrodes are demonstrated to be ferroelectric when integrated in a back-end of line (BEOL) of 130 nm CMOS technology, with a maximum thermal budget below 500°C. When the area of the ferroelectric capacitors is scaled down from 7850 µm² to 0.28 µm², no degradation of the remanent polarization (2•PR > 10 µC/cm² for HSO, > 30 µC/cm² for HZO) or of the switching kinetics (down to 100 ns at 3V) is observed. Significant improvement of the field cycling endurance is demonstrated upon area scaling, consistent with the reduction of the total number of defects when devices are shrunk. The results pave the way to future BEOL demonstrations in 130 nm and more advanced nodes with record endurance similar to perovskite ferroelectrics.

International audience; 1S1R operation behavior and read margin variability are elucidated for the first time to our knowledge. To this aim, an extensive experimental study is performed on HfO2 OxRAM technology co-integrated with GSSN-based Ovonic Threshold Selector (OTS) in 4kb memory arrays, supported by deep theoretical analysis. A semi-analytical dynamic model is developed for selector operation, describing OTS switching variability. The voltage repartition in the 1S1R stack during the switching operation is clarified. The 1S1R read voltage margin is quantified statistically, based on OTS switching voltage dispersion, OxRAM variability and margin degradation during endurance. Based on this theoretical and experimental study, 1S1R figures of merit (overall functionality, reliability, and maximum bank size) are optimized based on OTS and OxRAM devices' features and programming conditions.

In this work, we have investigated the structural properties of Germanium (Ge)-Antimony (Sb)-Tellurium (Te) (GST) and Ge-rich GST thin film samples. The structural properties of the films are studied after annealing temperatures from room temperature to 450 degrees C. We performed the annealing procedure using a heat rate of 10 degrees C/min to achieve the target temperature for a duration of 10 min under N2 flow. After heat treatment, we carried out X-Ray Diffraction (XRD), Fourier Infra-Red Spectroscopy (FTIR), Raman Spectroscopy and Scanning Electron Microscopy (SEM) equipped with Energy-dispersive X-ray spectroscopy (EDS) to investigate the evolution of the structure in the samples.

IEEE transactions on nuclear science 68(8), 1542 - 1547 (2021). doi:10.1109/TNS.2021.3085962, Published by IEEE, New York, NY

10nm Si-implanted HfO 2 is demonstrated to be ferroelectric for the first time when integrated in a Back- End-Of - Line (BEOL) 130nm CMOS. Scaled $.28\mu \mathrm{m}^{2}$ . capacitors demonstrate excellent endurance (109 cycles measured at 4 V, extrapolated to be 1012 at 3V), with tight coercive field distributions at wafer scale and excellent data retention at 85°C. To extend the ferroelectric BEOL compatibility of 10nm or thinner HfO 2 - based films, but also to understand their crystallization dynamics, nanosecond laser anneal is demonstrated to be very appealing, even for undoped HfO 2 .

This work explores a new method to reduce the energy consumption during the writing of process-spread resistive-based memories (RRAM), based on setting an initial electrical charge into a writing capacitor rather than applying constant voltage over a fixed time. By connecting a charged capacitor (constant charge source, CQS) to a RRAM device, we benefit of a lower energy requirement for setting the memory cells, for a given success rate. We propose a RRAM set circuit model, where switching conditions were extrapolated from experimental data. We then benchmark our proposed writing procedure with respect to the constant voltage source (CVS) scheme. Finally, we give experimental proof of concept by realization of a circuit interface that integrates the CQS protocol and is connected to a RRAM load. Results support the fact that setting the initial charge is a better choice to efficiently control the variability of the filamentary process in RRAM.

The advent of deep learning has considerably accelerated machine learning development. The deployment of deep neural networks at the edge is however limited by their high memory and energy consumption requirements. With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network. In this work, after presenting our implementation employing a hybrid CMOS - hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements. We investigate the memory-accuracy trade-off when binarizing whole network and binarizing solely the classifier part. We also discuss how these results translate to the edge-oriented Mobilenet V1 neural network on the Imagenet task. The final goal of this research is to enable smart autonomous healthcare devices.

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.

International audience; We demonstrate successful scalability of conventional 100µm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40µC/cm², endurance > 10 11 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. Presented results pave the way to < 10fJ/bit ultra-low power FeRAM for IoT applications.

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown $\text {N}_{c\,\text {max}}$ . It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on $\text {N}_{c\,\text {max}}$ statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled $\text {N}_{c\,\text {max}}$ distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred.

A nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon (L-Si) is demonstrated, which combines the superior programmability of general-purpose computing devices (e.g. FPGA) and the high power efficiency of do-main-specific accelerators. Besides the general computing applications, L-Si is particularly well suited for AI/machine learning and big data applications, which not only pose high computational/memory demand but also evolves rapidly. L-Si is fabricated by monolithically integrating HfO 2 resistive RAM on top of commercial 130nm Si CMOS. Our measurement confirmed the fabricated chip operates reliably at low voltage of 650 mV. It achieves 60.9 TOPS/W in performing neural network inferences and 480 GOPS/W in performing content-based similarity search (a key big data application) at nominal voltage supply of 1.2V, showing >$3\times $ and ∼$100\times $ power efficiency improvement over the state-of-the-art domain-specific CMOS-/RRAM-based accelerators. In addition, it outperforms the latest nonvolatile FPGA in energy efficiency by ∼$3\times $ in general compute-intensive applications.

International audience; A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with a slight decrease of endurance performance. Switching signal engineering demonstrates a wide range of performance achievable with HfO2:Si ferroelectric layer.

In this paper we present the optimization of the thermal confinement of a heater-based Phase-Change Memory (PCM) integrating a Ge-rich Ge-Sb-Te alloy (GGST) by the engineering of the encapsulation dielectric layer. Lower thermal conductivity of a SiC-based encapsulation layer wrt SiN, is demonstrated to improve the thermal confinement during programming operations in the PCM cell. Thanks to electrical characterization of 4Kb PCM arrays, we investigate the performance of thermally improved PCM devices, showing higher programming efficiency, higher SET programming speed and data retention higher than 250°C. The results are supported by 3D electro-thermal simulations, highlighting the effects of the higher thermal confinement achieved. These results confirm the outstanding improvement of the performances achievable in state-of-the-art PCM thanks to the thermal engineering of the cell.

In this paper we present the engineering of highly Sb-rich Ge-Sb-Te phase-change materials integrated in state-of-the-art Phase-Change Memory devices in 4Kb arrays. Thanks to an innovative composition called “delta” or $\delta$ -GST, high speed performance and high material stability under cycling is achieved in arrays and demonstrated by both physicochemical analysis and electrical characterization. Finally, the origin of the outstanding high speed in our innovative compound is revealed.

Thermal conductivity (kth) of Ge-rich Ge-Sb-Te phase-change material (GGST) is here investigated at temperatures up to $400\ ^{\circ}\mathrm{C}$ through “3ω method”. We present the engineering of the test vehicle, with the optimization of the metal-based heater to achieve a reliable measurement even at high temperature. Finally, we compare the results from four different approaches, showing which method is more accurate for the kth evaluation in phase-change materials.

Limited endurance of resistive RAM (RRAM) is a major challenge for future computing systems. Using thorough endurance tests that incorporate fine-grained read operations at the array level, we quantify for the first time temporary write failures (TWFs) caused by intrinsic RRAM cycle-to-cycle and cell-to-cell variations. We also quantify permanent write failures (PWFs) caused by irreversible breakdown/dissolution of the conductive filament. We show how technology-, RRAM programing-, and system resilience-level solutions can be effectively combined to design new generations of energy-efficient computing systems that can successfully run deep learning (and other machine learning) applications despite TWFs and PWFs. We analyze corresponding system lifetimes and TWF bit error ratio. Nanyang Technological University Accepted version This work was supported in part by Defense Advanced Research Projects Agency, in part by NSF-SRC/Nanoelectronics Research Initiative/Global Research Collaboration Energy-Efficient Computing: From Devices to Architectures, in part by STARnet SONIC, in part by NSF, in part by the Stanford SystemX Alliance, in part by NTU Startup Grant (M4082035), and in part by the AME Programmatic Hardware Software Co-Optimization for Deep Learning (M4070301). The review of this paper was arranged by Editor Y.-H. Shih. (Corresponding author: Mohamed M. Sabry.)

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages, and resistance levels. The programming conditions of memory elements (e.g., pulse widths and amplitudes) must cover the tail bits to avoid programming failures. Switching time of ReRAMs shows wide distributions. Therefore, fast cells are subjects for electrical stress after their switching and energy waste since programming currents are typically large for this technology (tens of $ {\mu }\text{A}$ ). In this brief, we present a write termination (WT) circuit to stop the programming operation when the switching event occurs in the selected memory element. The proposed design is sensitive to current variations that take place when the memory element switches between two different resistance states (low resistance state and high resistance state). This WT scheme reduces the power consumption by 97+%, 93+%, and 65+% during Forming, RESET and SET operations respectively. Our estimations show that area efficiency of 70% for a memory array is achievable when the presented WT circuit is integrated in near-memory peripheries. The demonstrated WT circuit is suitable for different ReRAM technologies with small overhead penalty and shows robustness against CMOS and ReRAM variabilities.

International audience; RRAM-based in-Memory Computing is an exciting road for implementing highly energy efficient neural networks. This vision is however challenged by RRAM variability, as the efficient implementation of in-memory computing does not allow error correction. In this work, we fabricated and tested a differential HfO 2-based memory structure and its associated sense circuitry, which are ideal for in-memory computing. For the first time, we show that our approach achieves the same reliability benefits as error correction, but without any CMOS overhead. We show, also for the first time, that it can naturally implement Binarized Deep Neural Networks, a very recent development of Artificial Intelligence, with extreme energy efficiency, and that the system is fully satisfactory for image recognition applications. Finally, we evidence how the extra reliability provided by the differential memory allows programming the devices in low voltage conditions, where they feature high endurance of billions of cycles.

International audience; In this paper, the impact of copper and oxygen vacancy balance in filament composition as a key factor for oxide-based CBRAM (Hybrid RRAM) performances is investigated. To this aim, several RRAM technologies are studied using various resistive layers and top electrodes. Material analyses allow to highlight the hybrid aspect of HRRAM conductive filament. Density functional theory simulations are used to extract microscopic features and highlight differences from a material point of view. Integrated RRAM technology performances such as window margin, endurance and retention are then measured to analyze copper and oxygen vacancy influence on device characteristics. A new RRAM classification correlating filament composition and memory performances is proposed.

Brain-inspired computing systems are attracting considerable attention due to their high energy efficiency with respect to conventional computing systems when applied to problems in artificial intelligence, sensing and robotics. This is attributed to the spike-based computational mechanism and architectural co-localization of processing and memory. To realize this neuron circuits must be integrated with further circuits modelling synapses. Synapses require to exhibit plasticity, that is modulation in their efficacy, to support online learning algorithms, manifesting in changes in their conductivity. Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) can be used as synaptic elements thanks to tunable conductivity, compatibility with advanced CMOS fabrication process and scalability. In this work, we present recent advances in implementing synaptic plasticity using both OxRAM and PCM arrays. We demonstrate that certain properties of these devices, usually considered non-idealities (i.e. conductance variability and non-linear change of conductance upon identical programming pulses), can improve the performance of Spiking Neural Networks (SNNs) trained with a bio-inspired, on-line and spike based unsupervised learning algorithm called Spike-Timing Dependent Plasticity (STDP).

International audience; In this work, we propose a reliability analysis targeting the evaluation of the suitability of a Phase-Change Memory (PCM) device for Storage Class Memory (SCM) applications. Thanks to the analysis of programming and endurance characteristics in single devices and 4kb arrays we compare two different GeTe and GeSbTe ($\alpha$GST) based PCM. The evolution of the phase-change material along cycling is explained by the analysis of subthreshold characteristics and analytical equations based on experimental data for the description of electrical parameters evolution are given. An extrapolation method to evaluate endurance at more than 10$^9$ cycles required for SCM is described and applied, showing the intrinsic high endurance capability and suitability for SCMapplications of $\alpha$GST wrt GeTe.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the leading candidates for embedded memory convergence in advanced technology nodes. It is particularly adapted to low-power applications, requiring a decent level of performance. However, it also have interests for secured applications. The PRESENT cipher is a lightweight cryptographic algorithm targeting ultra-low power applications such as the Internet of Things or RFID. This paper aims to combine this low power cryptographic algorithm with the STT-MRAM which main feature is its low consumption. This new generation of ciphers is very interesting for normally-off applications. Actually, for these specific applications hybrid CMOS/STT-MRAM ciphers consume less power than pure CMOS cryptographic algorithms.Although the performance of STT-MRAM is much better than standard non-volatile technologies like flash, it suffers from limitations for high-speed applications. A new MRAM technology based on Spin-Orbit Torque (SOT) was recently discovered and offers better performance in terms of speed and endurance, at the expense of a slightly degraded density. In this paper, we also propose a comparative study of several architectures of SOT-MRAM memories for evaluating the possible advantages of this NV technology for high-speed applications.

International audience; Spin Orbit Torque Magnetic RAM (SOT-MRAM) approach represents a new way to overcome over Spin Transfer Torque (STT) memory limitations by separating the reading and the writing paths. It is particularly interesting for high speed applications that do not require very high density because of two transistors per bit cell. This paper presents a high density SOTMRAM memory array based on a single transistor and a unidirectional diode. There are three advantages of this approach. The number of transistors for 32kb memory array is decreased by factor of 45% which leads to an improved cell density by 20% compared to conventional SOT bit cell. Moreover, it requires less control to read operation and finally high endurance, high speed and high density can be achieved. The key challenge going will be to adjust between sense margin and read energy

International audience; Phase change memory can provide a remarkable artificial synapse for neuromorphic systems, as it features excellent reliability and can be used as an analog memory. However, this approach is complicated by the fact that crystallization and amorphization differ radically: crystallization can be realized in a very gradual manner, very similarly to synaptic potentiation, while the amorphization process tends to be abrupt, unlike synaptic depression. Addressing this non-biorealism of amorphization requires system-level solutions that have considerable energy cost or limit the generality of the approach. This work demonstrates experimentally that an adaptation of the memory structure associated with an initialization electrical pulse followed by a sequence of identical fast pulses can overcome this challenge. A single device can then naturally implement gradual long-term potentiation and depression, much like synapses in biology. This study evidences through statistical measurements the reproducibility of the approach, discusses its physical origin, as well as the importance of the device architecture and of the initial electrical pulse. Through the use of system-level simulation, it is shown that this device is especially adapted to a neuroscience-inspired learning. These results highlight how nanodevices can be suitable for bioinspired applications while retaining the qualities of industrial technology.

International audience; Resistive Random Access Memory (RRAM)-based artificial Neural Networks (NNs) have been shown to be intrin-sically robust to RRAM variability but no study has been done to clearly explain and quantify this robustness. In this paper, we fully characterize a 4kbit RRAM array under different programming conditions. The impact of the electrical characteristics of RRAM (resistance variability, memory window, endurance performance) on the detection rate of a NN designed for object tracking and trained with a stochastic Spike-Timing Dependent Plasticity (STDP) rule is studied. We introduce a new parameter called the Synaptic Window (SW), defined as the ratio between the arithmetic mean conductance values of the low and high resistance distributions. The network performance was found only to be sensitive to the value of the SW (a SW>100 is required to achieve the maximum NN performance). Moreover, we demonstrate that a high resistance variability increases the SW for a given window margin.

International audience; In this paper, programming operations are optimizedfor low energy consumption and short latency time applicationsin RRAM kb arrays. Origin of consumption (role of pulse’stime, programming current and voltage in SET and RESEToperations) is quantified on HfO$_2$ oxide based RRAMtechnology. Specific patterns are evaluated to reduce latencytime and energy consumption in memory devices. Innovativecircuit with $on\ the\ fly$ switching detection is proposed, allowingto reduce programming consumption down to single pJoperation in large memory arrays.

International audience; In this paper we study the reliability of a N-doped Ge-Se-Sb based Ovonic Threshold Switching (OTS) Selector targeting high density Crossbar memory arrays. Through TEM analysis, we investigate the interaction between the TiN electrode and the chalcogenide layer, highlighting that the Ti diffusion appears to be the main mechanism responsible for the degradation of the device performances. In order to prevent this phenomenon, we engineered a thin carbon layer inserted in between the TiN electrode and the OTS material. Selector device performances are then considerably improved, achieving an ultra-low leakage current of 10 pA and an endurance of 10$^9$ cycles. These results are, at our knowledge, among the best reported so far in the literature for a back-end-of-line OTS selector technology.

International audience; In this paper, we investigate RRAM endurance improvement by optimizing programming energy on HfO$_2$/Ti OXRAM 1T1R kb arrays. SET and RESET programming patterns are optimized with programming current of 50^\mu$A, to minimize the energy provided to the system, maintaining sufficient widow margin on resistance distribution tails. Impact of both SET and RESET pattern on window margin is addressed. Programming scheme based on opti mized ramp voltage patterns allows to improve maximum endurance of about 2 decades, to insure stable median window margin at 10$^7$ cycles and to maintain window margin at 2$\sigma$ after 10$^6$ cycles at 50$\mu$A

In this paper, we investigate the impact of Ovonic Threshold Switching (OTS) selector electrical parameters, such as the threshold and the holding current, on the reliability of the reading operation in 1S1R memory devices. Through physico-chemical analysis and electrical characterization of Se-rich Ge-Se-based OTS selectors, performed up to 400 °C, we demonstrate the possibility to reduce the fire voltage as well the leakage current thanks to N- and Sb-doping. Moreover, we describe the correlation that exists between the leakage current and the threshold current in OTS devices. We highlight the subsequent trade-off between the reading window and the array size in an OTS-based Memory Crossbar Array, evaluated up to an operating temperature of 150 °C. Finally, thanks to OTS engineering, we demonstrate how the reading window can be optimized for a target array size and application.

International audience; In this letter, the fundamental variability limits of filament-based OxRRAM are investigated considering different transistor sizes and metal–insulator–metal (MIM) stacks featuring different materials and thicknesses. Cellto-cell variability is analyzed through an extensive characterization of Forming, Set, and Reset operations on 4-kb OxRRAM arrays. The results obtained in terms of switching voltage variability and resistance variability from cell-to-cell are compared and discussed to identify the variability limiting component as a function of the conduction regime and to understand the impact of transistor MIM stack parameters on variability and performances.

International audience; This paper presents an HfO2 based resistive switching memory (RRAM) in series with a GeSe-based Ovonic Threshold Switching (OTS) selector. Detailed investigation of the main memory operations, forming, set, reset and read is presented for the first time to our knowledge. An innovative reading strategy is proposed. The selector switching is performed only if the RRAM cell is in the Low Resistive State (LRS), while the reading of the High Resistive State (HRS) is performed without switching the OTS selector, preventing disruptive reading when the RRAM cell is in HRS. Up to 106 read cycles have been demonstrated with a stable memory window of one decade and a stable OTS OFF state.

Conference of 62nd IEEE International Electron Devices Meeting, IEDM 2016 ; Conference Date: 3 December 2016 Through 7 December 2016; Conference Code:126284; International audience; In this paper, we propose a new circuit architecture and a reading/programming strategy to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile OxRAM cells. For the first time, we show how the intrinsic OxRAM device switching probability at ultra-low power can be exploited to implement STP as well as LTP learning rules. Moreover, we demonstrate the computational power that STP can provide for reliable signal detection in highly noisy input data. A Fully Connected Neural Network incorporating STP and LTP learning rules is used to demonstrate two applications: (i) visual pattern extraction and (ii) decoding of neural signals. A high accuracy is obtained even in presence of significant background noise in the input data.

The quest for the universal memory has been pursued since several years, but as far results from scientific literature do not declare one single technology able to fit all the requirements of the memory hierarchy. Flash and DRAM cover more than 95% of the global sales in the semiconductor memory market [1], but none of the two is able to substitute the other. This appears to be true also for disruptive backend memory technologies, like OxRAM, CBRAM, PCM and MRAM. This paper deals with universal signatures that stand true for such disruptive technologies. A specific analysis on two case examples from the RRAM and the PCM domain, where tradeoffs can be adjusted to target specific applications, is finally proposed. Knowing in advance the tradeoffs of each technology allows us to save precious time in research and development and therefore to accelerate the time-to-market.

While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.

International audience; In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Si-nc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

In this work, we present a detailed investigation of the electrical characteristics of 3D Gate-All-Around (GAA) Silicon nanowire (down to 6nm-diameter) SONOS memories compared to standard planar SONOS devices. In particular, by means of TCAD simulations, the write, erase and retention characteristics under uniform FN stress are explained and the main geometrical and electrostatic effects of 3D cylindrical devices are put in evidence. The physical mechanisms dominating the 3D devices performance and reliability are identified. In particular, the great influence of band-to-band phenomenon in the erase characteristics is underlined.

An alternative solution to standard Flash memories is represented by nitride-trap memories as silicon–oxide–nitride–oxide–silicon (SONOS) or nitrided read only memory (NROM) memories. However these structures are facing retention issues at high temperature and a quantitative analysis of the location of the charge during program and retention is required. This work investigates the location of charge of NROM Nonvolatile memory devices in order to evaluate the trapped charge distribution in program and retention conditions for Si3N4, Al2O3, and HfO2 trapping layers. During programming, the charge is initially injected on a 40–60-nm-length region in the trapping layer, then after reaching a trapped charge saturation level, it broadens. The charge saturation level is explained through electrostatic considerations and not by a limit of available number of traps. During retention, the lateral migration (inside the trapping layer) and vertical migration (charge loss) of the trapped charge are quantitatively evaluated. Thanks to a one-dimensional (1D) drift model, the characterization of lateral migration at room temperature is put in relation to the trap properties of Si3N4, Al2O3, and HfO2 layers.

This work presents an original semi-analytical model capable to predict the electrical behavior of nanocrystal (NCs) trigate Fin-FET structures programmed under uniform tunneling (NAND scheme). Experimental data from memory devices with different gate stacks are quantitatively fitted, confirming the efficiency of our model. This model allows for a quantitative understanding of the influence of the FinFET geometrical variations on memory performances. The impact of the fin corner rounding appears to be the most critical feature in such 3D structures.

In this paper, we present a semi-analytical model tailored for nitride Charge-Trap TriGate (CT-3G) non-volatile memories under uniform stress: Fowler-Nordheim (FN) program (P) and erase (E) performances are reproduced. This model presents innovations in the tunnelling current calculation at corners through the Hankel function formalism. The validation of the model is operated through extensive comparisons with experimental data obtained on ultra-scaled devices with different aspect ratios and gate stacks. Scaling opportunities of such kind of 3D devices are deeply discussed.

OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (

This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO 2 -based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F2/N is achieved (‘N’ being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 104 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach.

International audience; In this paper we compare the performances of SiN with respect to an optimized SiC encapsulation in Wall based Phase-Change Memory (PCM) integrating a Ge-rich Ge-Sb-Te alloy (GGST) suitable for high temperature stability in automotive applications. Thanks to the electrical characterization of 4kb arrays, 3D electro-thermal simulations and TEM analyses performed on programmed devices, we demonstrate the higher programming efficiency in SiC-based PCM devices, thanks to the lower thermal conductivity of the optimized encapsulation. Indeed, the uniform temperature profile achieved in the active layer of SiC encapsulated PCM leads to a retention of one hour at 250°C. A theoretical model is here proposed to describe the electro-thermal behavior of the device, linking the electrical properties, such as the resistance as a function of current characteristics, to the thermal conductivity of the materials that constitute the device. Finally, thanks to our findings, we provide some guidelines to achieve drastic current reduction via the thermal engineering of the next generation PCM technology.