Search

Though Honokiol was known to have anti‐inflammatory, antioxidant, anticancer, antithrombotic, anti‐viral, metabolic, antithrombotic, and neurotrophic activities, the underlying mechanisms of Honokiol on epithelial–mesenchymal transition (EMT) mediated liver fibrosis still remain elusive so far. Anti‐EMT and antifibrotic effects of Honokiol were explored in murine AML‐12 hepatocyte cells by 3‐(4,5‐dimethylthiazol‐2‐yl)‐2,5‐diphenyl‐2H‐tetrazolium bromide (MTT) assay, wound healing assay, Western blotting and also in CCl4‐induced liver injury mouse model by immunohistochemistry. Honokiol significantly suppressed transforming growth factor β1 (TGF‐β1)‐induced EMT and migration of AML‐12 cells along with decreased EMT phenotypes such as loss of cell adhesion and formation of fibroblast like mesenchymal cells in TGF‐β1‐treated AML‐12 cells. Consistently, Honokiol suppressed the expression of Snail and transmembrane protease serine 4 (TMPRSS4), but not p‐Smad3, and activated E‐cadherin in TGF‐β1‐treated AML‐12 cells. Additionally, Honokiol reduced the expression of β‐catenin, p‐AKT, p‐ERK, p‐p38 and increased phosphorylation of glycogen synthase kinase 3 beta (GSK3β) and JNK in TGF‐β1‐treated AML‐12 cells via TGF‐β1/nonSmad pathway. Conversely, GSK3β inhibitor SB216763 reversed the ability of Honokiol to reduce Snail, β‐catenin and migration and activate E‐cadherin in TGF‐β1‐treated AML‐12 cells. Also, Honokiol suppressed hepatic steatosis and necrosis by reducing the expression of TGF‐β1 and α‐SMA in liver tissues of CCl4 treated mice. These findings provide scientific evidence that Honokiol suppresses EMT and hepatic fibrosis via activation of E‐cadherin/GSK3β/JNK and inhibition of AKT/ERK/p38/β‐catenin/TMPRSS4 signaling axis. [ABSTRACT FROM AUTHOR]

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB. [ABSTRACT FROM AUTHOR]

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future. [ABSTRACT FROM AUTHOR]

A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation–recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to ~3.5 s at 80K, which is ~104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K ($\sim 11~\mu \text{A}$) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance. [ABSTRACT FROM AUTHOR]

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C). [ABSTRACT FROM AUTHOR]

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped ${n}^{+}$ source and drain junctions, nearly intrinsic ${n}^{-}$ channel, 500-nm gate length (${L}_{{{\mathrm {G}}}}$), and 50-nm poly-Si body thickness (${T}_{{{\mathrm {body}}}}$). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of $3.2~{\mu }\text{A}/{\mu }\text{m}$ and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems. [ABSTRACT FROM AUTHOR]

In0.08Al0.92N/GaN fin-type high-electron mobility transistors (fin-HEMTs) with different gate-to-drain lengths (${L} _{\text {gd}}$) are fabricated and characterized by dc and low-frequency noise (LFN) measurements. The fabricated device with the largest ${L} _{\text {gd}}$ exhibits the degradation of the maximum drain current and transconductance with a positive shift of the threshold voltage. LFN measurements of the In0.08Al0.92N/GaN fin-HEMTs reveal clear 1/ ${f}$ behavior of the noise spectra, and the minimum value is observed in the device at ${L} _{\text {gd}} = {20}\,\,\mu \text{m}$. The devices with smaller ${L} _{\text {gd}}$ follow a carrier number fluctuation noise model owing to electron trapping/detrapping into the In0.08Al0.92N barrier layer from the 2-D electron gas (2DEG) channel. In contrast, the device with the largest ${L} _{\text {gd}}$ shows correlated mobility fluctuations due to the large 2DEG mobility fluctuations in the large access area. [ABSTRACT FROM AUTHOR]

Novel AlGaN/GaN omega-shaped nanochannel FinFETs with fin width of 50 nm were successfully fabricated using TMAH lateral wet etching with ALD HfO 2 sidewall spacer. This fin structure apparently exhibited the current spreading in the access region, which results in the suppression of the drain lag effect at high drain voltage and sharp switching performance with subthreshold swing of 57–65 mV/decade. Excellent on- and off-state state performances for the fabricated device prove that the omega-shaped gate structure not only exhibits excellent gate controllability, but also decouples the active nano-channel region from the underlying thick buffer. The proposed device is very promising candidate for high-performance device applications. [ABSTRACT FROM AUTHOR]

Superior device characteristics have been demonstrated with a novel Al(In)N/GaN-based steep fin-type high electron mobility transistor (HEMT) with a fin width ( W\mathrm{ fin} ) of 120 nm, a fin height ( H\mathrm{ fin}) of 250 nm, and a gate length ( LG ) of 200 nm. The proposed device achieved very low drain leakage ( I\mathrm{ off}) < 8 \times 10^{-8} A/mm at 7 V and < 1 \times 10^-6 A/mm at 100 V, which is four orders of improvement over I\mathrm{\scriptscriptstyle OFF} of conventional Al(In)N/GaN HEMTs. In addition, the device exhibits a high ON-state current ( I\mathrm{\scriptscriptstyle ON}) of 1.12 A/mm, a steep sub-threshold swing ( $S$ ) of 63 mV/decade, a low drain-induced barrier lowering of 18.5 mV/V, and a high power-gain cutoff frequency ( f_{T} ) of 21 GHz. [ABSTRACT FROM PUBLISHER]

This study investigated characteristics of the fabricated triangle-type light-emitting diode (T-LED), conventional triangular LED (CT-LED), and conventional square LED (CS-LED). The T-LED is expected to provide uniform current spreading that leads to high output power, low current crowding, and high light extraction in the lateral direction of the LED device, compared to CT-LED and CS-LED. The light extraction of the T-LED in the lateral direction is much higher than that of the CT-LED and the CS-LED due to enhancement of light emission from the sidewalls of the T-LED. [ABSTRACT FROM AUTHOR]

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO2/Si3N4 dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si3N4 single-layer insulator are conducted to the simulation works together. The stacked TiO2/Si3N4 GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO2/Si3N4 than that of a Si3N4 single-layer insulator. However, the electrical field and current density increased by the stacked TiO2/Si3N4 layers make the device's temperature higher. That results in the degradation of the device's performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO2/Si3N4-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; Ron increased from 1.41 mΩ·cm2 to 2.56 mΩ·cm2, and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO2/Si3N4-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si3N4 single-layer insulator. [ABSTRACT FROM AUTHOR]

AlGaN/GaN-based fin-shaped field-effect transistors with very steep side-wall have been fabricated by utilizing electron-beam lithography and subsequent anisotropic side-wall wet etch in tetramethyl ammonium hydroxide solution. The investigate device demonstrated extremely broad transconductance ( gm) ranging from \sim 0 to \sim 8 V at VD = 10 V, which is essential for high linearity device performance. Pulse measurement showed that the device exhibits negligible gate lag, but still suffers from drain lag. The device with L\mathrm {GD} of 17~\mu \textm exhibited excellent OFF-state characteristic with subthreshold swing of \sim 58 mV/decade, low OFF-state leakage current of \sim 10^{-12} A, and breakdown voltage of \sim 400$ V at V_{G}=- 9 V. [ABSTRACT FROM PUBLISHER]

In this work, a high-performance compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction with a tunneling-boost layer is investigated. The tunneling-boost layer in the source-side channel alters the energy band-gap structure between the source and the channel, which affects current drivability considerably. It is shown that controlling the lengths of the boosting layer (thin n+ GaAs layer) and lightly doped p-type channel (p-GaAs) also has substantial effects on adjusting Vth without complications arising from shifting metal workfunction. Furthermore, we evaluate device performances such as on-state current (Ion), subthreshold swing (S), intrinsic delay time (τ), and cut-off frequency (fT). The proposed TFET with an n-GaAs length of 12 nm showed an S of 27 mV/dec and approximately 3 times higher Ion than that of the device without a boosting layer. Moreover, it is confirmed from the extracted excellent radio-frequency (RF) parameters that the proposed device is suitable for RF applications. [ABSTRACT FROM AUTHOR]