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For the time and frequency signals of Beidou satellites, a high-accuracy phase frequency detection technology based on phase group synchronization is proposed. Using the Beidou receiver and satellite signals as the frequency standard and the measured signals, respectively. The Beidou receiver and the satellite signals are sent to the phase coincidence detector of the different frequencies to generate a phase coincidence point pulse, which is sent to the different frequency phase detector as a control signal to generate the phase differences between the Beidou receiver and satellite signals, and then complete the high-accuracy phase synchronization between the Beidou receiver and satellite signals. Experimental results show that when the delay resolution reaches ps level, the phase synchronization accuracy of the system can reach 10 ps, which has the characteristics of small phase noise, low development cost, simple circuit structure, and high synchronization accuracy compared with the traditional phase synchronization technologies. Therefore, it would be widely used in satellite positioning, astrometry, precision navigation, aerospace, satellite launch, power transmission, communications, radar, and other high-tech fields. [ABSTRACT FROM AUTHOR]

This paper introduces a low-complexity start–stop true random number generator (TRNG) utilizing jitter in ring oscillators (ROs). Incorporating phase detectors enhances entropy extraction from the same number of ROs. The raw bits undergo online post-processing using the SHA-1 algorithm, which is widely supported by many programming languages. The output bit streams pass all NIST statistical tests (SP 800-22 and SP-90B). Bits are generated on demand, enhancing security by preventing eavesdropping during continuous bit production. The TRNG maintains its performance regardless of the FPGA manufacturer. [ABSTRACT FROM AUTHOR]

A phasemeter as a readout system for the inter-satellite laser interferometer in a space-borne gravitational wave detector requires not only high accuracy but also insensitivity to amplitude fluctuations and a large fast-acquiring range. The traditional sinusoidal characteristic phase detector (SPD) phasemeter has the advantages of a simple structure and easy realization. However, the output of an SPD is coupled to the amplitude of the input signal and has only a limited phase-detection range due to the boundedness of the sinusoidal function. This leads to the performance deterioration of amplitude noise suppression, fast-acquiring range, and loop stability. To overcome the above shortcomings, we propose a phasemeter based on a tangent phase detector (TPD). The characteristics of the SPD and TPD phasemeters are theoretically analyzed, and a fixed-point simulation is further carried out for verification. The simulation results show that the TPD phasemeter tracks the phase information well and, at the same time, suppresses the amplitude fluctuation to the noise floor of 1 μrad/Hz1/2, which meets the requirements of GW detection. In addition, the maximum lockable step frequency of the TPD phasemeter is almost three times larger than the SPD phasemeter, indicating a greater fast-acquiring range. [ABSTRACT FROM AUTHOR]

This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable. [ABSTRACT FROM AUTHOR]

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s. [ABSTRACT FROM AUTHOR]

In this paper, a frequency discrimination method using a multiplicative-integral and linear transformation network is proposed. In this method, two preset differential frequency signals and frequency modulation signals are transformed by multiplication and integration, and then the instantaneous frequency parameters of the frequency modulation signal are accurately analyzed by the linear transformation network to restore the original modulation signal. Compared with the phase discriminator, the simulation results show that this method has a higher frequency discrimination bandwidth. In addition, this method has better anti-noise performance, and the frequency discrimination distortion caused by noise with a different Signal-to-Noise Ratio is reduced by 33.80% on average compared with the phase discriminator. What is more, the carrier center frequency error has little influence on the frequency discrimination quality of this method, which solves the problem that most common frequency discriminators are seriously affected by the carrier center frequency error. This method requires a low accuracy of carrier center frequency, which makes it extremely suitable for digital frequency discrimination technology and can meet the needs of various frequency discrimination occasions. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator. Post-layout simulations show that phase noise suppression is about 13 dB at 100 MHz offset for a division ratio of 2. [ABSTRACT FROM AUTHOR]

To measure the micro-displacement reliably with high precision, a single-ended eddy current sensor based on temperature compensation was studied in detail. At first, the principle of the eddy current sensor was introduced, and the manufacturing method of the probe was given. The overall design plan for the processing circuit was induced by analyzing the characteristics of the probe output signal. The variation in the probe output signal was converted to pulses with different widths, and then it was introduced to the digital phase discriminator along with a reference signal. The output from the digital phase discriminator was processed by a low-pass filter to obtain the DC component. At last, the signal was amplified and compensated to reduce the influence of temperature. The selection criteria of the frequency of the exciting signal and the design of the signal conditioning circuit were described in detail, as well as the design of the temperature-compensating circuit based on the digital potentiometer with an embedded temperature sensor. Finally, an experimental setup was constructed to test the sensor, and the results were given. The results show that nonlinearity exists in the single-ended eddy current sensor with a large range. When the range is 500 μm, the resolution can reach 46 nm, and the repeatability error is ±0.70% FR. Within the temperature range from +2 °C to +58 °C, the voltage fluctuation in the sensor is reduced to 44 mV after temperature compensation compared to the value of 586 mV before compensation. The proposed plan is verified to be feasible, and the measuring range, precision, and target material should be considered in real-world applications. [ABSTRACT FROM AUTHOR]

This paper presents a low-power multi-rate clock and data recovery (CDR) for receivers of serial links. Its basic structure includes a current-mode logic bang–bang phase detector sampled by low-mismatch half-rate quadrature clocks, which are generated by voltage-controlled delay line (VCDL) and two-stage time-average circuits. The total delay of VCDL can be adjusted to accommodate a wide frequency range by its bias voltage, which is generated by a delay-locked-loop-based bias generator. The quadrature clocks are 64-phase adjustable with high linearity, which is realized by phase interpolator with a compensating structure. The parameters of phase detection loop are well designed to satisfy both high jitter tolerance and low clock jitter. Fabricated in a 40 nm CMOS technology, the CDR occupies an active area of 0.036 mm 2 only. With a wide operating range of 2–20 Gb/s, the chip consumes 62.5 mW, corresponding to an energy efficiency of 3.1 pJ/bit. The measured root-mean-square jitter and peak-to-peak jitter for the recovered clock at 9 GHz are 1.9 and 10.8 ps, respectively. [ABSTRACT FROM AUTHOR]

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure. [ABSTRACT FROM AUTHOR]

Abstarct: In this work, a new Charge Pump (CP) design including a Phase and Frequency Detector (PFD) is presented. The PFD is designed using the common topology of two D Flip Flops, AND gates and a controllable reset delay for the DFFs to compensate for process and tem-perature variations. The Charge Pump is using a bias cell which generates the necessary bias voltages, the clock driving cells which convert the single-ended UP and DOWN signals to differential and the core cell which comprises of six slices, each one contributing the same amount of current to the low pass filter. The output current is programmable with minimum and maximum values of 25 uA and 150 uA respectively. An extra option to double the output current is also added. A new technique has been adopted in terms of layout floorplan of the charge pump slices to eliminate the clock feedthrough mismatch between the differential UP and DOWN sig-nals. The technology used in this work is TSMC 65nm, while the supply voltage is 1 V. The main characteristics of the proposed design are modularity, low power, low noise, great linearity, small area, simplicity and performance. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

An emerging challenge of integrated communication and sensing is the extraction of weak sensing signals transmitted through an unknown non-stationary channel. In this work, we propose a weak signal extraction method with weak measurement. Taking advantage of time division multiplexing, we preliminarily estimate the channel via adjustable finite impulse response filter, further suppressing the interfering signal caused by background noises via spectrum shift. By subsequently using the time-varying phase estimation method via weak measurement, the real-time detection of weak signals in the non-stationary channel is achieved. We demonstrate via theoretical analysis and confirmatory experiment that our method is able to amplify the phase shift, to suppress technical noise and to improve detection resolution limit, while proving robust against light source fluctuations, initial phase differences and detector saturation. The method hence enables weak sensing signal extraction with a low signal-to-noise ratio non-stationary channel. Furthermore, we interface our measurement method to squeezed light sources, offering the possibility of surpassing standard quantum limit. Integrated communication and sensing require high performance, sensing precision and preliminary knowledge of the channel, posing challenges to sensing weak signals from non-stationary channels. In this work, the authors demonstrate a weak signal extraction method with weak measurement, achieving weak signal sensing through a non-stationary channel. [ABSTRACT FROM AUTHOR]

The optical signal propagation used in satellite uplinks and downlinks is influenced by absorption, scattering, and changes in the atmospheric refractive index or turbulence, causing optical signal attenuation. A free space optics (FSO) communications system using coherent communication can improve the link sensitivity and reach higher distances. This article proposes a new architecture for the phase detector in an all-digital optical phase-locked loop (OPLL) for coherent optical detection. Firstly, the performance of the proposed phase detector is evaluated under Gaussian noise, where the best operation point is found for the OPLL working with two sample rates: 625 MSa/s and 10 GSa/s. The system analyses also take a non-negligible delay into account. Then, it will be evaluated and compared with an OPLL using an analog phase detector in the presence of atmospheric turbulence. Finally, in three different atmospheric turbulence conditions, the effect of wind speed on communication quality is investigated through the obtained bit error rate (BER) from the recovered data for a bit rate of 20 Gbps. The results show that the proposed digital phase detector can track a signal under longer feedback loop delays and fading signals. [ABSTRACT FROM AUTHOR]

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ( F o M j i t t e r ) ~−236 dB. [ABSTRACT FROM AUTHOR]

Infrared linear array detectors frequently experience vertical, low-frequency, and periodic stripe noise during imaging, stemming from electro-mechanical interference. Unlike conventional periodic disturbances, this interference showcases long periodicities and is uniquely columnar in orientation. Its presence, especially within the low-frequency domain, renders conventional filtering techniques ineffective and, at times, detrimental to image quality. Addressing this challenge, we introduce Fourier-Assisted Correlative Denoising (FACD), a correlation-centric denoising approach tailored for such unique interference patterns. This mechanism begins with the capture of a pure background image, inclusive of periodic noise, during the non-uniform correction phase of the infrared detector. Leveraging the noise's frequency domain attributes, we extract a one-dimensional single-cycle noise signal. The infrared image is subsequently segmented into parts, and using the detected noise periodicity, the one-dimensional signals for each segment are computed. By leveraging the correlation between these signals and the benchmark one-dimensional noise pattern, we ascertain the noise profile within each segment. This profile is then employed for spatial domain denoising across the entire image frame. Empirical assessments confirm that the FACD outperforms contemporary denoising techniques by augmenting the peak signal-to-noise ratio by approximately 2.5 dB, underscoring its superior robustness. Furthermore, in light of its specificity to this noise model, FACD rapidly denoises high-resolution real infrared linear array scans, thus meeting the stringent real-time and resolution imperatives of advanced infrared linear array scanning apparatuses. [ABSTRACT FROM AUTHOR]

The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL's lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 μ m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 μ W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [ - 2 π , 2 π ]. The PFD occupies an area of 0.0069 mm 2 . The proposed design is well suited to low-power, high-speed PLL applications. [ABSTRACT FROM AUTHOR]

Multi-h continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-h continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-h CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-h CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method. [ABSTRACT FROM AUTHOR]

This paper presents formulations for time-based first-order and second-order high-pass, shelf, and notch filters. These formulations are an extension to the existing literature where low-pass filters are already developed using a multiphase controlled oscillator in conjunction with a phase detector and charge pump. The presented high-pass filter expands the circuit by introducing a current-controlled delay line (CCDL) that provides a direct path from input to output. By combining the high-pass filter with the low-pass filter, we show that shelf and notch filters can be obtained without an increase in circuit complexity compared to the high-pass filter. The results show good matching between the ideal small signal and the simulated time-based large signal frequency response. The simulated of total harmonic distortion for the filters shows an increase in distortion due to the nonlinearities introduced by the CCDL for the high-pass, notch, and shelf filter compared to the existing low-pass filter. The derivation of the new filter types allows the creation of complex high-order time-based filters by combining multiple first- or second-order filters. [ABSTRACT FROM AUTHOR]

The effectiveness of the use of optical calibration in high-precision phase laser rangefinders has been evaluated. In order to ensure the specified accuracy of distance determination in order to establish the optimal frequency of distance measurement modes and optical calibration, an appropriate formula is recommended for estimating the switching frequency of signals at the input of the range finder measuring channel. It has been established that even when using optical calibration, the accuracy of distance measurement is affected by the error of the phase detector, which is part of the rangefinder. To minimize the influence of this error, a new method for the direct measurement of the phase shift in a range finder is proposed, as well as the use of a compensation method for measuring the phase shift. The corresponding block diagrams of rangefinders are considered, in which the proposed methods for measuring phase landslides are implemented, and analytical modeling of the processes that transform them is carried out. [ABSTRACT FROM AUTHOR]

This study describes a non-contact low-cost X-band sensor system for determining the soluble solid content (SSC) of a sugar solution. The system adopts a transmission signal technique with two frequency pairs (10.2 GHz paired with 10.4 GHz and 10.2 GHz paired with 10.6 GHz) from three transceiver modules. Each module has a microstrip patch antenna, mixer circuit, and dielectric resonator oscillator. To simplify the transmission power frequency of each frequency pair, the frequency is down-converted to an intermediate frequency (IF) signal using a frequency mixer. The IF signals are then compared using a gain and phase detector to find their magnitude ratio and phase difference. The measured SSC-level data are randomly divided into three datasets and input to an artificial neural network (ANN) for training. The training output is the SSC level in Brix degree. The proposed ANN structure comprises four input nodes, eight hidden nodes, and four output nodes, affording low complexity and resource savings while providing 92.98% accuracy. Therefore, the proposed low-cost sensor system can achieve precise decision-making and real-time measurement. [ABSTRACT FROM AUTHOR]

Due to reset process of phase frequency detector (PFD), the induced blind zone degrades the acquisition performance of phase-locked loop. Most of reported blind-zone free solutions are based on transistors, which cannot be implemented with field programmable gate array (FPGA). Therefore, a blind zone-suppressed PFD suit for FPGA is proposed in this paper. If any trigger condition of blind zone is met, the proposed reset mask or edge recovery operation is active. Thereafter, the corresponding edge of detected clock is kept or recovered to alleviate the effect of blind zone. At last, the proposed PFD is written by Verilog hardware description language, and implemented with Xilinx Virtex-7 XC7VX330TFFV1157-3. The occupied resources are 9 LUTs and 15 FFs, and the logic delay of critical path is only 0.264ns. The correctness of blind zone-suppressed PFD is also verified by simulation results. [ABSTRACT FROM AUTHOR]

Despite extensive investigations on the mechanism of laser-irradiated solid propellants, formulating an accurate model that characterizes more details of laser-target interactions remains a challenging task. In this paper, a thermal model for nanosecond pulsed laser ablation of aluminum was developed using the finite volume method which considers the instant recession on the propellant surface and the non-Fourier effect during heat conduction. The robust coupling iteration scheme adopted in the model tracks the dynamic boundary condition due to instant propellant removal. In particular, the pre-qualified threshold is used as discriminator for phase explosion and the thermal relaxation time is introduced to quantify the non-Fourier effect on heat conduction. In addition, the temperature-dependent physical and optical parameters of the propellant were also regarded in the proposed model. The numerical implementations for Gaussian laser ablation of aluminum were performed at different laser fluences and thermal relaxation times. The theoretical computation of the ablation depth coincides well with the experimental results to validate the feasibility of the model. • The thermal interaction of an ultra-short pulsed laser with metal was investigated. • The material moving front during heat transfer was modeled using finite volume method. • A modified critical threshold was used as a discriminator for metal phase explosion. • The thermal relaxation time was introduced to quantify the non-Fourier effect. [ABSTRACT FROM AUTHOR]

Robust and reliable multi-modal image matching is an essential and challenging technique in the multi-modality involved scenarios for image fusion, image mosaic, and visual navigation. Existing image matching methods cannot simultaneously solve the scale and rotation distortion caused by different viewpoints and the nonlinear radiation distortion caused by different imaging environments or mechanisms. To address these problems, a multiscale structural feature transform method is proposed for multi-modal image matching, which consists of three blocks: multiscale structural feature detector, symmetric log-polar descriptor, and point matching with position correction. The multiscale structural feature detector constructs the phase congruency map based Difference of Gaussian image pyramid for the scale-invariant feature points detection to tackle the nonlinear radiation distortion. The feature points are detected within 10-neighborhood instead of 26-neighborhood to produce sufficient points on the phase congruency map with very sparse texture. The symmetric log-polar descriptor utilizes the multiscale structure principal direction and symmetric bins to improve the robustness of the descriptor to rotation and nonlinear radiation distortion. At last, the point matching with position correction corrects the position of feature points to compensate the position offset between different images caused by the scale and rotation distortion and the nonlinear radiation distortion, which increases the number of correct matches and improves the transformation consistency between matched points. In the experiment, the proposed method in this paper is compared with seven state-of-the-art methods. Experimental results verify the superiority of the proposed method and its robustness to the scale and rotation distortion and the nonlinear radiation distortion. In addition, we demonstrate the effectiveness of the proposed three blocks by the ablation experiments. • A multiscale structural feature transform is proposed for multi-modal image matching. • The multiscale structural feature detector extracts repeatable and salient points. • The symmetric log-polar descriptor achieves rotation-invariance and robustness. • The offsets of feature points are corrected to produce more correct match pairs. [ABSTRACT FROM AUTHOR]

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ( V DD , w p , and w n ) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V DD , w p , and w n are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are − 1 5 9. 5 6 dBc/Hz, 9.83 μ W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 μ m 2 . The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 μ s. [ABSTRACT FROM AUTHOR]

GPS receivers have a wide range of applications, but are not always secure. A spoofing attack is one source of conscious errors in which the counterfeit signal overcomes the authentic GPS signal and takes control of the receiver's operation. Recently, GPS spoofing attack detection based on computational algorithms, such as machine learning, classification, wavelet transform and clustering, has been developing. This paper proposes multiple clustering algorithms for accurately clustering the authentic and spoofing signals, called subtractive, FCM and DBSCAN clustering. The spoofing attack is recognized using two distinct features: moving phase detector variance and norms of correlators. Spoofing and authentic signals have different patterns in the proposed features. According to the Dunn and Silhouette indexes, the validation of the results is investigated. The Dunn values for the proposed approaches are 0.8592, 0.5285 and 0.6039 for DBSCAN, FCM and subtractive clustering, respectively. Also, the DBSCAN algorithm is implemented at the RTL level because of its highest value for the Dunn index and algorithm verifiability. Using the Vivado tools, this algorithm is implemented and designed on a Xilinx Virtex 7 xc7vx690tffg1930-3 hardware device for two-dimensional data with 32-bit accuracy and 130 data points. [ABSTRACT FROM AUTHOR]

In this article, a half-tangent phase-locked loop (HTan-PLL) is proposed for variable-frequency grids of more electric aircrafts. First, the pros and cons of the synchronous reference frame PLL (SRF-PLL) are discussed in a nonlinear framework. To address the disadvantages, a half-tangent phase detector (PD) is developed and a novel PLL is then proposed. Subsequently, a phase portrait-based analysis and a Lyapunov function-based argument are provided. It is proven that the HTan-PLL has a good performance in terms of steady-state accuracy and fast dynamics, even under large frequency changes. Compared with the conventional SRF-PLL, the proposed HTan-PLL outperforms with the following features: faster dynamics than the SRF-PLL when the frequency varies largely; no unstable equilibrium points, while the SRF-PLL has infinite unstable equilibrium points; and when the grid frequency jumps widely, the HTan-PLL converges to the unique equilibrium point (0,0). By contrast, the SRF-PLL goes to different equilibrium points. Experimental tests are provided, which verify the superior performance of the HTan-PLL. [ABSTRACT FROM AUTHOR]

The paper discusses a multichannel monitoring device with a speed-optimal phase-locked loop system, which, by performing simultaneous measurements of several clock signals against the reference one, processing and transmitting measurement results by an IP-network in real time, increases the accuracy and precision of providing time synchronization signals for SMART Grid energy system. Analytical expressions where established to determine the conditions under which in the optimal system of phase-locked loop has no influence on the transient process of limiting the periodic static characteristic of the phase discriminator. Experimental studies have confirmed meeting the norms of the European standard ETS 300 462-4 for the time parameters of the reference signal generated by the phase-locked loop system, which is optimal in terms of speed, and also demonstrated the effectiveness of the proposed implementation of the device for multi-channel monitoring of time synchronization signals for SMART Grid of power systems. [ABSTRACT FROM AUTHOR]

In phase frequency detector (PFD) phase characteristics, the presence of dead zone fails to turn on the charge pump (CP) of the phase locked loop (PLL). This degrades the phase noise in PLL. To overcome this drawback in PFD, a circuit to eliminate dead zone using pass transistor logic (PTL) and delay cells (DCs) is proposed in this paper. The proposed circuit has been implemented in UMC 0.18 μ m CMOS process and simulated in a cadence spectre environment. From the post layout simulation results, it is noted that for a phase difference of - π to + π , the PFD achieves 100% linearity and is free from the dead zone. The designed PFD consumes power of 28.8 μ W at an operating frequency of 100 MHz. The proposed PFD is also verified across process voltage temperature (PVT) variations for its linearity. The PFD is independent of duty cycle variations of its input clock signals. It occupies an area of 312.4 μ m 2 . [ABSTRACT FROM AUTHOR]

This paper presents an LO phase shifter with frequency tripling for 28-GHz 5G transceivers. The phase shifting and frequency tripling are achieved using an injection-locked oscillator and injection-locked frequency tripler, respectively. A phase detector based on third harmonic mixing is also implemented and is used to detect the applied phase shift, supporting automatic calibration of the phase shifter. Additionally, an algorithm to automatically tune the oscillators to their respective locking frequency is presented. To test the phase shifter, a 24–30-GHz sliding-IF receiver is implemented. Simulations show that a > 360 ∘ tuning range over the full 24–30 GHz span is achieved, with a gain variation of 0.11 dB or less, and that the phase detector has an rms phase error of < 2.5 ∘ . The circuit is implemented in a 28nm FD-SOI CMOS process and the entire chip measures 1080 μ m × 1080 μ m , including pads, and consumes 27–29 mW from a 1 V supply. [ABSTRACT FROM AUTHOR]

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage‐controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase‐frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage‐controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed‐forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide‐by‐47 and divide‐by‐48) that lacks a few extra flip‐flops which save considerable power and improves the frequency difficulties of the multi‐band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1‐μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS‐based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability. [ABSTRACT FROM AUTHOR]

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoMT is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature. [ABSTRACT FROM AUTHOR]

The phase frequency detector/charge pump is a significant source to raise the in-band phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor phase frequency detector (PT-PFD) solves the cycle skipping issue by improving the blind zone which in turn improves the phase noise performance. At the same time, in order to further improve the performance of the PLL, charge pump is integrated with the proposed design. In this case, the reset time has been reduced and thus the proposed PFD/CP functions up to the frequency of 1.5 MHz – 4.2 GHz. In addition, the modified pass transistor PFD architecture contains an advantage of less number of transistor count which consumes low power, i.e., 317.37 μ W . The design is based on standard 0.18 μ m CMOS process technology with the supply voltage of 1.8 V. Moreover, the proposed design has completely eliminated the dead zone, and blind zone is minimized up to 44.23 ps which improves the phase noise to −133.8 dBc/Hz at 1 MHz offset frequency. The PFD/CP proposed herein just requires lower power consumption while producing less noise in charge pump phase-locked loop (CPLL) application. [ABSTRACT FROM AUTHOR]

Sensorless drives of interior permanent magnet synchronous motors (IPMSMs) find a broad range of applications due to their inherent benefits. In practical electrified propulsions, the IPMSM drives are usually working in highly utilized conditions where the performance and stability could deteriorate. Without considerable compensation, this vulnerability causes the existing phase-locked loops (PLLs), estimators, or observers to lose the synchronization with the rotor position. To achieve better performance and reduce the estimation error, in a PLL-type framework for sensorless control, a position error observer (PEO) utilizing the current errors as correction terms plays the role of the phase detector. A reduced-order extended state observer (ESO) is presented to form the loop filter with a switched nonsmooth feedback structure. The outstanding property of the PEO and nonsmooth ESO is verified through experiments. The results demonstrate its strong adaptability for model uncertainties and disturbances along with the quick convergence speed and minimal oscillation. [ABSTRACT FROM AUTHOR]

A metering roundabout where traffic is controlled by traffic lights with phase times influenced by queue detector occupancy might be the solution to enhance performance when there are unbalanced traffic flows at roundabouts. There have, however, been minimal studies on how the distance of the queue detector from the stop line affects signal phase time durations and the queuing lengths. This research, therefore, seeks to develop a Cuckoo Search/Local search Algorithm using parameters such as arrival volumes, conflicting volumes, detector distance and phase time to investigate the relationship of signal setting, detector location and queuing formulations. Also, some additional statistical tests were performed for the fitness of the data. In order to conduct solid model calibrations and validations, model output data was compared against the AIMSUN model. The results from the analyses demonstrated that the queue detector distance can affect phase time durations and vehicle queuing lengths on the controlling approach as well as queuing lengths on the metered approach. This study showed that, based on the study for the Old Belair Road roundabout, the total queue length (controlling + metered) will be minimized from 689 to 499 m by the proposed methods when the detector is relocated at 210 m from the roundabout stop line, giving longer phase green times and resulting in decreased intersection queuing lengths. [ABSTRACT FROM AUTHOR]

A coarse-fine tuning technique with analog enhancement (AE) operation is proposed for the digital low-dropout (DLDO) regulator. Once the undershoot or overshoot is detected, the coarse tuning quickly finds out the coarse control loop in which the load current should be located, with large power PMOS size and high sampling frequency. Then, the fine tuning, with reduced power PMOS size and sampling frequency, regulates the DLDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. By using time-domain comparator instead of voltage-domain comparator, the voltage signal is converted to time signal and the comparison result is obtained through phase discriminator to identify phase difference, so that DLDO can realize low-voltage operation. Meanwhile, the AE operation is introduced to reduce the overshoot/undershoot voltage by increasing the transient current of the power PMOS. The proposed DLDO is designed using a 180 nm 1P6M CMOS process with a 0.09 mm2 active area. The post-simulated undershoot and overshoot voltages are only 50.26 and 34.66 mV, respectively, when the load current changes between 1 and 2.5 mA, and the maximum recovery time is 305.3 ns. [ABSTRACT FROM AUTHOR]

This research presents an improved direct instantaneous torque controller (DITC) for switched reluctance motors (SRMs). It incorporates a novel adaptive real-time commutation mechanism. The proposed method can effectively enhance the torque profile and efficiency of the machine by proper real-time adjustment of both the turn-on and the turn-off angles. First, an initial value of the turn-on angle is selected to achieve the highest torque generation capability. Then, with a real-time adjustment around the pre-selected initial angle, the instantaneous torque error can be further compensated. Hence, the torque ripple is minimized. Regarding the turn-off angle, an initial value is selected to satisfy the minimum required conduction angle of SRM. Then, this value is continuously adjusted at each electrical cycle by utilizing a phase current detector to force the outgoing phase current to decay to a less effective value before the negative slope of the inductance profile. Therefore, this prevents serious negative torque generation. The proposed strategy fully utilizes the torque generation capability of the motor with a minimized torque ripple, besides the phase currents, are generated in optimal conduction range to enhance the motor efficiency. The simulations and experiments have been carried out on a 3-phase 750 W 12/8 SRM to validate the proposed method's feasibility and effectiveness. [ABSTRACT FROM AUTHOR]

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit's robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of − 1 5 9. 1 7 dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25 μ W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275 μ m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc. [ABSTRACT FROM AUTHOR]

This article analyses the effect of noise and nonlinearity in optoelectronic phase-locked loops (OEPLLs). The OEPLL phase-locks a microwave oscillator on the envelope of the optical pulse train from a mode-locked laser (MLL). The phase detector of this type of OEPLL is called a balanced optical microwave phase detector (BOMPD) and operates in a mixed electro-optical domain. The main noise sources in a BOMPD, such as shot noise of photodiodes, generation-recombination noise of photodiodes, relative intensity noise of the laser, and noise of the bias voltage applied to the BOMPD. are discussed. The nonlinear behavior of the BOMPD with respect to the intensity of the optical field and the amplitude of the RF voltage is discussed. An OEPLL that can lock on the harmonics and interharmonics of the MLL repetition rate is demonstrated. The OEPLL has an in-band phase noise of below −150 dBc/Hz at 100-kHz offset frequency for a carrier frequency of 10 GHz. This phase noise level is 10–20 dB better than state-of-the-art commercial frequency synthesizers. [ABSTRACT FROM AUTHOR]

A Mueller-Muller Phase Detector (MM PD) technology based on duo-binary four-level pulse amplitude modulation (DB PAM-4) with low complexity and high phase-detection density is presented. The proposed low complexity includes low phase-detection complexity and low space complexity of data processing. The waveform sifting technology simplifies 175 specific waveform changes into five fuzzy waveform change trends, reducing the complexity of subsequent phase detection. By making the data sample before the waveform sifting, the data bit width is reduced from 8 bit to 3 bit, which realizes data dimensionality reduction, greatly reduces the scale of subsequent auxiliary data, reduces the number of basic devices by 13.7%, and reduces the spatial complexity of data processing. The coherent coding of DB PAM-4 combined with waveform sifting increases the phase-detection density from 50% to 65% and improves both phase-detection density and phase-detection gain by 30%, and improves the jitter tolerance. Through the simulation of the clock and data recovery (CDR) model built by Cadence, the fast locking capability of CDR is verified. [ABSTRACT FROM AUTHOR]

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power consumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of communication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational capacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power consumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum. [ABSTRACT FROM AUTHOR]

Bioimpedance spectroscopy (BIS) is an advanced measurement method for providing information on impedance changes at several frequencies by injecting a low current into a device under test and analyzing the response voltage. Several methods have been elaborated for BIS measurement, calculating impedance with a gain phase detector (GPD), IQ demodulation, and fast Fourier transform (FFT). Although the measurement method has a big influence on the measurement system performance, a systematical comparative study has not been performed yet. In this paper, we compare them based on simulations and experimental studies. To maintain similar conditions in the implementation of all methods, we use the same signal generator followed by a voltage-controlled current source (VCCS) as a signal generator. For performance analysis, three DUTs have been designed to imitate the typical behavior of biological tissues. A laboratory impedance analyzer is used as a reference. The comparison addresses magnitude measurement accuracy, phase measurement accuracy, signal processing, hardware complexity, and power consumption. The result shows that the FFT-based system excels with high accuracy for amplitude and phase measurement while providing the lowest hardware complexity, and power consumption, but it needs a much higher software complexity. [ABSTRACT FROM AUTHOR]

A multiple-frequency continuous-wave (MFCW) agile radar system has the ability to cope with various physiological conditions of a human subject. Following the mathematic model, a favorable carrier frequency for detection is pursued by analyzing the amplitude and composition of the baseband signal. In Experiment-1, a CMOS dual-band transceiver prototype emulate searching a subject from a distance. The frequencies of the dual-band system are 4.26–4.95 GHz and 17.06–19.79 GHz. During the experiment, the respiratory signal could be detected up to 12 m, and the heartbeat signal up to 6 m. Even with a wooden or a brick barrier in the path, the vital-sign detection remained satisfactory. Later, a concurrent MFCW detection is performed in Experiment-2 for more precise analyses. From the concurrent results, the breathing status can be inferred, and by cross-correlating the results after the ensemble empirical mode decomposition (EEMD) and principal component analysis (PCA), the nonlinear effects of respiratory harmonics or intermodulation tones are reduced, resulting in an accurate heart rate extraction. The receiver front-end and the signal source are manufactured using a 180-nm CMOS process, both packaged on an RO4003C printed-circuit board (PCB). [ABSTRACT FROM AUTHOR]

The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as a demodulation algorithm. However, resolver signals often come with quadrature errors and harmonics, which lead to a severe reduction in PLL accuracy. The conventional PLL does not consider the impact of the quadrature error, and the bandwidth of the PLL is much larger than the fundamental frequency of resolver signals for pursuing a low dynamic error. These reasons render the retention of resolver harmonics in the demodulation results. In this paper, a disturbance-compensated PLL (DC-PLL) is proposed, which consists of a phase detector for suppressing quadrature error and harmonics (SQEH-PD) and a second-order observer. Firstly, since the quadrature error does not change with the angle velocity, the pre-estimated quadrature error is used in the SQEH-PD to compensate for the quadrature error in resolver signals. Secondly, although the frequency of the harmonics changes with the velocity, the amplitudes of the harmonics do not change. Therefore, the pre-estimated amplitudes of harmonics and estimated angular position are used in the SQEH-PD to compensate for the harmonics in resolver signals. Thirdly, a second-order observer is designed to estimate the angular position and velocity by regulating the phase detector error. Compared with the conventional PLL, the proposed DC-PLL has a stronger anti-disturbance ability against the quadrature error and harmonics by configurating the phase detector error and the estimated position error, which have a linear relation. Simulation and experimental results prove the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5 Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector's phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit's total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40 nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5 Gb/s. With a pseudo-random bit sequence (PRBS) of 2 3 1 − 1 , the measured result shows that the bit error rate (BER) is < 1 0 − 1 2 , and the root mean square jitter recovered in the output is 0.302 p s rms . The circuit's jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8 mW with a 5.98 pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]