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Silicon-Germanium (SiGe) is a material that possesses a multitude of applications ranging from transistors to eletro-optical modulators and quantum dots. The diverse properties of SiGe also make it attractive to implementations involving superconducting quantum computing. Here we demonstrate the fabrication of transmon quantum bits on SiGe layers and investigate the microwave loss properties of SiGe at cryogenic temperatures and single photon microwave powers. We find relaxation times of up to 100 $\mu$s, corresponding to a quality factor Q above 4 M for large pad transmons. The high Q values obtained indicate that the SiGe/Si heterostructure is compatible with state of the art performance of superconducting quantum circuits., Comment: 5 pages, 3 figures

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

IBM engineers have developed a holographic imaging technique, called dual-lens electron holography, that provides high spatial resolution and field of view without compromising signal-to-noise ratio. This article reviews the basic principles of the new method and provides several examples of its use. The first few examples demonstrate the junction profiling capabilities of the new method which, in one case, helps to explain why shallow junction devices are made with raised source-drain regions. In the other examples, dual-lens holography is used for strain mapping, in one case, to study strain distributions in sigma-shaped SiGe devices, and in another, to provide evidence that stress memorization occurs in dislocations in the source-drain region of nFET devices.

We investigate the determining mechanisms of the inversion-layer capacitance Cinv in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the Cinv dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed Cinv modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the Cinv in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the Cinv is experimentally evaluated.

Strain engineering for pFETs has been conventionally enabled utilizing embedded SiGe in the source/drain regions to continuously boost the transistor current drive and transconductance [1]. Historically, for planar technologies, transconductance was monotonically improved by advancing the technology generations. However, this trend for transconductance, when properly normalized to the effective device width (fin perimeter) is no longer observed when FinFETs were introduced to the mainstream CMOS to improve the short channel effects for sub 30nm gate lengths [2]. The FinFET transconductance saturation or drop be attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Unless there is a strong and reliable method to externally apply gigantic strain to the Si fin channel, using strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Capacitance-Equivalent-oxide-Thickness (CET) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility and current drive. However, epitaxial-defect-driven fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. In particular, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons, from the transport point of view: First, very high level of strain (close to 3GPa) can be achieved when lattice matched to Si [4]. Second, if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the high-performance (HP) device at a lower VDD, i.e. below 0.6V, in line with logic roadmap [4]. Controlling the HFIN, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is associated with the gate stack and interface trap control which is more pronounced in HGC SiGe than Si and pure Ge. In this talk, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent advancement to achieve optimized RMG IL and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In additions, a metal gate work-function tuning solution will be presented utilizing an ultra-thin replacement metal-gate scheme to achieve target high-performance off current down to 15nm gate lengths. References: [1] T. Ghani et al., IEDM, 2003, p. 197. [2] P. Hashemi, et al., IEDM, 2017, p. 824. [3] S. Krishnan et al., IEDM, 2011, p. 634. [4] P. Hashemi et al., IEDM, 2014, p. 402. [5] R. Xie et al., IEDM, 2016, p. 47. [6] P. Hashemi et al., VLSI Tech. Symp., 2017, p. 120.

The backscattered electron (BSE) signal in the scanning electron microscope (SEM) can be used in two different ways. The first is to give a BSE image from an area that is defined by the scanning of the electron beam (EB) over the surface of the specimen. The second is to use an array of small BSE detectors to give an electron backscattering pattern (EBSP) with crystallographic information from a single point. It is also possible to utilize the EBSP detector and computer-control system to give an image from an area on the specimen--for example, to show the orientations of the grains in a polycrystalline sample ("grain orientation imaging"). Some further possibilities based on some other ways for analyzing the output from an EBSP detector array, are described.

High-spatial-resolution analytical electron microscopy using energy-dispersive X-ray (EDX) and electron energy-loss spectrometry (EELS) of yttrium- and lanthanum-doped Al2O3 has been conducted to ascertain the level of segregation of these impurities to grain boundaries. Line profile analyses indicate that the segregation is confined to a layer thickness of

Grain-boundary embrittlement, caused by the segregation of impurity and alloying elements, occurs in many systems and has been the focus of a large amount of research owing to its technological importance. However, the exact mechanism by which the segregating elements cause embrittlement remains unclear. In this paper the localized changes in the electronic structure in the classical embrittling system of Bi in Cu have been studied. Experimental results were obtained by examining the fine structure in the electron energy loss spectrum which was then compared to calculations using the layer Korringa-Kohn-Rostoker (LKKR) method. A change in the d density of states has been observed for the Cu atoms at the grain boundary, associated with Bi, and an electronic model to explain embrittlement is described.

High-resolution electron microscopy and nano-beam analytical electron microscopy have been used to characterize both the intergranular silicate film thickness and its local composition in a series of high-purity Si3N4 ceramics doped with 0–450 at. ppm Ca. Calcium was detected at both two-grain junctions and triple junctions, even in the 80-ppm-Ca-doped specimen. The thickness of the intergranular film at two-grain junctions was found to depend sensitively on Ca content. In undoped material, the thickness was 1.0 ± 0.1 nm. With increasing Ca content, the thickness decreased in the dilute region (80 ppm Ca), but then increased. The variation in film thickness can be qualitatively understood in terms of the balance of three long-range forces acting normal to the film, namely the van der Waals dispersion force, a structural “steric” force, and an electrical-double-layer force. By comparing the measured thicknesses to those predicted, estimates for the structural correlation length and the inverse Debye length can be made. These estimates have values of ∼ 0.22 nm and approximately 0.3–0.5 nm, respectively, for the calcia-free and 80 ppm calcia materials.

Extended abstract of a paper presented at Microscopy and Microanalysis 2011 in Nashville, Tennessee, USA, August 7–August 11, 2011.

Atomic layer deposition (ALD) of epitaxial c-axis oriented BaTiO3 (BTO) on Si(001) using a thin (1.6 nm) buffer layer of SrTiO3 (STO) grown by molecular beam epitaxy is reported. The ALD growth of crystalline BTO films at 225 °C used barium bis(triisopropylcyclopentadienyl), titanium tetraisopropoxide, and water as co-reactants. X-ray diffraction (XRD) reveals a high degree of crystallinity and c-axis orientation of as-deposited BTO films. Crystallinity is improved after vacuum annealing at 600 °C. Two-dimensional XRD confirms the tetragonal structure and orientation of 7–20-nm thick films. The effect of the annealing process on the BTO structure is discussed. A clean STO/Si interface is found using in-situ X-ray photoelectron spectroscopy and confirmed by cross-sectional scanning transmission electron microscopy. The capacitance-voltage characteristics of 7–20 nm-thick BTO films are examined and show an effective dielectric constant of ∼660 for the heterostructure.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008

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Distribution and migration of oxygen in the highk/metal gate stack has a strong impact on the CMOS transistor electrical characteristics. Excess O can cause interlayer (IL) growth and subsequent increase of Equivalent Oxide Thickness (EOT), whereas O-vacancies induced by the metal gate contact may lead to unpredictable and feature size dependent shifts in threshold voltage (Vt). In addition to these phenomena, we have recently described a new migration pathway for O in poly-Si/TiN/TiO2-based high-k/stacks [1]. Besides re-growth of the bottom IL, excess O –released by the thermal decomposition of TiO2-based high-k stacks upon annealing– was observed to diffuse upwards, resulting in SiO2 growth at the TiN/poly-Si interface, as evidenced by regular SIMS analysis following the O main isotope. Here, we have employed SIMS depth profiling in combination with isotopic labeling –using minority Oisotope– to characterize the migration and/or redistribution of O in the high-k metal gate stack (HK/MG) at different stages of processing. Firstly, the creation of vacancy defects in high-k dielectrics –induced by the TiN-based metal gate contact upon high temperature annealing– is the most probable cause for large (~500 meV) Vt shifts, which is especially problematic for pFET devices. We have demonstrated that these shifts can be largely recovered after a lowtemperature low-pressure top-down oxygenation step on TiN metal gate exposed by poly-Si removal, while preventing excessive oxidation of TiN and parasitic IL regrowth [2]. Using SIMS, we have systematically investigated the incorporation of O by SIMS for different temperatures and TiN thicknesses on TiN-gated high-k films, subjected to top-down oxygenation with isotopic labeled O2, see Figure 1. We have thus established that incorporated O-doses –needed to remove the defects created in a metal-HfO2 contact– amount 1.4e14 to 3.9e14 at.cm. In addition, O-profiles after top-down oxidation show a small but significant shift with respect to pre-existing O towards the TiN-interface (see inset Figure 1). This implies that passivation of vacancies preferentially occurs in the top portion of the high-k layer, consistent with negligibly small oxide (IL) re-growth. Secondly, remote O-scavenging from the SiO2 interlayer (IL) using a poly-Si/doped TiN metal gate stack is a promising technique to achieve aggressive EOT scaling in a gate-first flow, compliant with 16 nm technology node requirements [3]. The remote scavenging mechanism is based on the presence of a metallic element M, inserted in the TiN metal gate at a certain separation from the high-k interface. This scavenging element is capable of scavenging O from the SiO2 IL upon poly activation anneal, as evidenced by TEM and conventional O-SIMS. Here, we have employed SIMS to determine the kinetics of O-scavenging from Hf-based high-k dielectric –enriched in O by isotopic exchange after high-k deposition upon low-temperature O2 exposure– towards M-TiN alloy for different annealing temperatures and IL’s. Use of an O-isotope enriched high-k layer allows following of O-redistribution through scavenging and isotopic exchange for different annealing temperatures, see Figure 2. This approach has revealed a subtle effect of IL composition on remote O-scavenging kinetics. In addition, rapid isotopic exchange between the different interfaces through the TiN metal gate is seen to occur upon high temperature anneal, indicating rapid Odiffusion in these stacks. These examples demonstrate the benefits of using O isotope labeling for SIMS analysis to resolve small quantities of O and to obtain fundamental knowledge on oxygen transport in high-k metal gate stacks.

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The presence of internal boundaries can significantly influence many important properties of materials, such as fracture toughness, creep, electrical conductivity and magnetic behavior. Interfacial structure, chemical composition and bonding, on a nanometer length scale, are often controlling and sought after factors influencing these properties. An electron spectroscopic technique, known as energy-loss near edge structure (ELNES) analysis, can be utilized to probe compositional and bonding variations with a spatial resolution less than 1 nm and is therefore well suited to this endeavor. When a fast electron passes through a material in an electron microscope, it collides with the electrons bound to the atoms in that sample. As a result, the fast electron often gives up a small fraction of its kinetic energy to the bound electrons. The laws of quantum mechanics dictate that these so-called inelastic scattering events will only take place if the bound electron can gain enough energy to enter an empty energy level.