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In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push–push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628–682, 556–610, and 509–548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were −10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.

Spin Hall nano-oscillators (SHNOs) exploiting current-driven magnetization auto-oscillation have recently received much attention because of their potential for oscillator-based neuromorphic computing. Widespread neuromorphic application with SHNOs requires an energy-efficient way to tune oscillation frequency in broad ranges and store trained frequencies in SHNOs without the need for additional memory circuitry. Voltage control of oscillation frequency of SHNOs was experimentally demonstrated, but the voltage-driven frequency tuning was volatile and limited to megahertz ranges. Here, we show that the frequency of SHNO is controlled up to 2.1 GHz by a moderate electric field of 1.25 MV/cm. The large frequency tuning is attributed to the voltage-controlled magnetic anisotropy (VCMA) in a perpendicularly magnetized Ta/Pt/[Co/Ni]n/Co/AlOx structure. Moreover, non-volatile VCMA effect enables control of the cumulative frequency using repetitive voltage pulses, which mimic the potentiation and depression functions of biological synapses. Our results suggest that the voltage-driven frequency tuning of SHNOs facilitates the development of energy-efficient spin-based neuromorphic devices.

A D-band low-noise amplifier (LNA) has been developed based on a 65-nm CMOS technology, which showed a measured peak gain of 16.1 dB at 134.5 GHz. The noise property of the fabricated amplifier was characterized with two different noise measurement techniques: the cryogenic Y-factor method and the N-times power method. The two methods showed a minimum value of the noise figure of 10.7 dB and 14.7 dB, respectively.

A new interstage matching technique has been proposed and successfully applied to a ${D}$ -band amplifier in a 65-nm CMOS technology. The proposed technique is based on a simultaneous conjugate matching at the interstages of multistage amplifiers at two frequencies, resulting in an increased bandwidth. The six-stage amplifier designed based on this technique shows a peak gain of 13.8 dB at 113.7 GHz with a 3-dB bandwidth of 11.2 GHz (110.6–121.8 GHz) without balun loss compensation, while consuming a dc power of 40 mW. Measured noise figure shows a minimum value of 10.8 dB at 115 GHz. The output $P_{1\,\text {dB}}$ and the saturation output power $P_{\mathrm{ sat}}$ are −14 and −3 dBm, respectively. The circuit occupies an area of $1100 \times 550~\mu \text{m}^{2}$ .

645-GHz signal generation with a harmonic oscillator based on a 250-nm InP heterojunction bipolar transistor technology is demonstrated. The oscillator is based on the common-base cross-coupled topology, generating a second harmonic signal through the push–push operation. The fabricated oscillator exhibits oscillation frequencies ranging from 561.5 to 645.1 GHz with bias variation. The measured peak output power is –17.4 dBm with a dc power dissipation of 49.3 mW (dc-to-RF efficiency of 0.04%). Additionally, terahertz imaging was successfully demonstrated with the developed oscillator employed as a signal source.

This work describes the development of a D-band (110?170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50?75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is 900 × 1,890 μm², including RF and DC pads.

This paper presents two 3-stage D-band stacked amplifiers developed in a 0.13-μm SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.

A 260-GHz amplifier in a SiGe heterojunction bipolar transistor (HBT) technology is reported. It is based on three-stage differential cascode topology and adopts a passive shunt transistor pair at the output of each amplifying stage to relax instability caused by parasitic base inductance of amplifying transistor pair. The instability of the amplifier can be mitigated by tuning the base bias voltage of the shunt transistor pair. Peak gain of the amplifier was measured as 15 dB at 260 GHz. DC power dissipation is 112 mW. The chip occupies 300 × 160 μm2 excluding Baluns and probing pads.

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 ㎓ based on SiGe HBT technology. Firstly, a 123-㎓ oscillator was developed based on Colpitts topology, which showed - 5 ㏈m output power and phase noise of -107.34 ㏈c/㎐ at 10 ㎒. DC power dissipation was 25.6 ㎽. Secondly, a 135 ㎓ mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 ㏈ at 1 ㎓ IF at fixed LO frequency of 134 ㎓. DC power dissipation was 3 ㎽, which mostly comes from the buffer.

In this paper, a receiver has been developed in a CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as . The chip size is excluding the probing pads.

Two fundamental-mode oscillators operating around 300 GHz, a fixed-frequency oscillator and a voltage-controlled oscillator (VCO), have been developed in this work based on a 250-nm InP heterojunction bipolar transistor (HBT) technology. Both oscillators adopted the common-base configuration for the cross-coupled oscillator core, providing higher oscillation frequency compared to the conventional common-emitter cross-coupled topology. The fabricated fixed-frequency oscillator and the VCO exhibited oscillation frequency of 305.8 GHz and 298.1-316.1 GHz (18-GHz tuning range) at dc power dissipation of 87.4 and 88.1 mW, respectively. The phase noise of the fixed-frequency oscillator was measured to be -116.5 dBc/Hz at 10 MHz offset. The peak output power of 5.3 dBm (3.8% dc-to-RF efficiency) and 4.7 dBm (3.2% dc-to-RF efficiency) were respectively achieved for the two oscillators, which are the highest reported power for a transistor-based single oscillator beyond 200 GHz.

A balanced RF duplexer with low interference in an extremely narrow bandgap is proposed. The Long-Term Evolution band-7 duplexer should be designed to prevent the co-existence problem with the WiFi band, whose fractional bandgap corresponds to only 0.7%. By implementing a hybrid bulk acoustic wave (BAW) structure, the temperature coefficient of frequency (TCF) value of the duplexer is successfully reduced and the suppressed interference for the narrow bandgap is performed. To achieve an RF duplexer with balanced Rx output topology, we also propose a novel balanced BAW Rx topology and RF circuit block. The novel balanced Rx filter is designed with both lattice- and ladder-type configurations to ensure excellent attenuation. The RF circuit block, which is located between the antenna and the Rx filter, is developed to simultaneously function as a balance-tounbalance transformer and a phase shift network. The size of the fabricated duplexer is as small as . The maximum insertion loss of the duplexer is as low as 2.4 dB in the Tx band, and the minimum attenuation in the WiFi band is as high as 36.8 dB. The TCF value is considerably lowered to .

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².

In this paper, the stability of RF MOSFETs is investigated in terms of the stability-factor ( $k$ -factor) for various layout schemes and device dimensions based on two different RFCMOS technologies. To systematically analyze the effect of small-signal device model parameters on RF MOSFET stability, the expression for $k$ -factor is derived as a function of the small-signal model parameters of RF MOSFETs. Based on the expression, the effect of small-signal model parameters on the stability of RF MOSFETs is explored along with its bias dependence. In addition, the effect of wiring schemes, number of gate fingers, gate finger pitch, and gate length is examined based on various device structures. It is shown that the transconductance and capacitances are the dominant device parameters to determine the stability of RF MOSFETs. The result also indicates that the stability of RF MOSFETs is strongly affected by the details of layout scheme and lateral dimension. Additionally, it was found that there is a tradeoff between device stability and speed. This study is expected to serve a guideline for the device design and optimization for stable operation of RF MOSFETs and circuits based on them.

In this work, a 70/140 GHz dual-band push-push voltage controlled oscillator(VCO) has been developed based on a 0.18-μm SiGe BiCMOS technology. The lower band and the upper band oscillation frequency varied from 67.9 GHz to 76.9 GHz and from 134.3 GHz to 154.5 GHz, respectively, with tuning voltage swept from 0.2 to 2 V. The calibrated maximum output power for each band was —0.55 dBm and —15.45 dBm. The VCO draws DC current of 18 mA from 4 V supply.

A wideband H-band detector operating near 300 GHz has been developed based on SiGe HBT technology. The detector consists of an on-chip antenna and a HBT differential pair for square-law detection. It showed responsivity of more than 1,700 V/W and noise equivalent power (NEP) smaller than 180 pW/Hz 0.5 for the measured frequency range of 250–350 GHz. The maximum responsivity and the minimum NEP were 5,155 V/W and 57 pW/Hz 0.5 , respectively; both were obtained at 330 GHz with DC power dissipation at 9.1 W.

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90- nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm × 0.69 mm including the DC and RF pads.

This paper presents a comprehensive study on the high-Q island-gate varactor (IGV), which includes a comparison with the conventional multifinger varactors (MFVs) and analyses on the effect of structural variations on the varactor performance. The study shows that the IGV exhibits smaller Rs and larger Q factor compared to the MFV, while its capacitance tuning ratio is smaller. The effect of the dimension variation and shape of the gate island, as well as the gate thickness, is substantial and the observed trends can be exploited for IGV optimization. This work indicates that the IGV is a highly promising option for millimeter-wave applications.

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-μm Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92～19.31 GHz with tuning range of 0～1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82～55.84 GHz) and, with varactor tuning of 0～1.8 V, the total operating range is 2.4 GHz(54.82～57.17 GHz). The fabricated circuit size is 0.42 mm×0.6 mm including probing pads and 0.099 mm×0.056 mm for core area.

In this work, a 18 GHz divide-by-4 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in Si RFCMOS technology. The free-running oscillation frequency is from 4.98 to 5.22 GHz and output power is about －30 dBm, consuming 33.4 mW with a 1.5 V supply voltage. At 0 dBm input power, the locking range is 3.5 GHz(17.75~21.25 GHz) and with varactor tuning, the operating range is increased up to 5.25 GHz(16.0~21.25 GHz). The fabricated chip size is including DC and RF pad.

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT times BVCEO product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.

Recently, the demand on ㎜-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the ㎜-wave frequency band have been traditionally implemented in Ⅲ-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled ㎜-wave circuits realized in a Si CMOS technology. In this work, a 58 ㎓ CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a 0.13-㎛ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the ㎜-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 ㎓ with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 ㏈c/㎐ at 5 ㎒ offset was achieved. The output power varied around -20 ㏈m over the measured tuning range. The circuit drew current (including buffer current) of 10 ㎃ from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 ㏈c/㎐.

The current characteristics of SiGe heterojunction bipolar transistors (HBTs) operating in the reverse active mode are investigated. It is experimentally shown that the I/sub C/ is identical for the reverse and the forward modes for arbitrary doping and Ge profiles across the base to first order. In contrast, the impact of V/sub BE/ and V/sub CB/ modulation on I/sub C/ is opposite for the two modes, leading to a smaller Early voltage but more ideal collector current for the reverse mode.

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

SiGe HBT transistors achieving over 200 GHz f/sub T/ and f/sub MAX/ are demonstrated in this paper. Techniques and trends in SiGe HBT design are discussed. Processing techniques available to silicon technologies are utilized to minimize parasitic resistances and capacitances and thereby establish raw speeds exceeding III-V devices despite the higher mobility in those materials. Higher current densities and greater avalanche currents, which are required for establishing such high performance, are discussed as they relate to device self-heating and reliability and the degradation of the devices. Simple circuit results are shown, demonstrating 4.2-ps ring-oscillator delays.

Temperature-dependent minority electron mobilities in p-type SiGe have been measured for the first time. Measurements were made on test n-p-n SiGe-Si heterojunction bipolar transistors (HBTs) with pseudomorphic p-type Si/sub 1-x/Ge/sub x/ (0.2/spl les/x/spl les/0.4) base layers. Magnetotransport measurements were performed on the fabricated HBT's to obtain the minority electron mobilities in the heavily B-doped base layers for temperatures ranging from 5 to 300 K. The measured minority electron mobilities exhibited sharp increase with decreasing temperature, and also showed enhancement with decreasing base Ge composition. The cutoff frequency technique was also employed to estimate the room temperature minority electron mobilities of the alloys and the results confirmed the trend in mobilities with Ge composition as determined by the magnetotransport technique.

Embedding magnetic layers in inductors is an attractive option for increasing inductance density, which is a critical issue for radio-frequency applications. In this letter, we develop a magnetostatic model for square spiral inductors incorporating a magnetic layer. In our model, we assume that the permeability of the magnetic layer is isotropic and infinite. The model provides a fast and effective numerical calculation of the inductance of inductors incorporating a magnetic layer. We show the derivation of the model and provide calculation results for various inductor structures.

A double mesa-structure Si/SiGe heterojunction bipolar transistor (HBT) and novel micromachined lumped passive components have been developed and successfully applied to the fabrication of X- and Ku-band monolithic amplifiers. The fabricated 5/spl times/5 /spl mu/m/sup 2/ emitter-size Si/SiGe HBT exhibited a DC-current gain /spl beta/ of 109, and f/sub T/ and f/sub max/ of 28 and 52 GHz, respectively. Micromachined spiral inductors demonstrated resonance frequency of 20 GHz up to 4 nH, which is higher than that of conventional spiral inductors by a factor of two. Single-, dual-, and three-stage X-band amplifiers have been designed, based on the extracted active- and passive-device model parameters. A single-stage amplifier exhibited a peak gain of 4.0 dB at 10.0 GHz, while dual- and three-stage versions showed peak gains of 5.7 dB at 10.0 GHz and 12.6 dB at 11.1 GHz, respectively. A Ku-band single-stage amplifier has also been designed and fabricated, showing a peak gain of 1.4 dB at 16.6 GHz. Matching circuits for all these amplifiers were implemented by lumped components, leading to a much smaller chip size compared to those employing distributed components as matching elements.

Device characteristics for SiGe heterojunction bipolar transistors fabricated by a simplified process without selectively implanted collector (SIC), which exhibit peak fmax of 310 GHz at the collector-current density of 7 mA/mum2 and BVCEO of 2 V, are reported. For comparison, the characteristics of devices with various SIC doses are also presented, and the observed trends are discussed

The reduction of the dislocation density in relaxed SiGe/Si heterostructures using a low-temperature Si(LT-Si) buffer has been investigated. We have shown that a 0.1 μm LT-Si buffer reduces the threading dislocation density in mismatched Si0.85Ge0.15/Si epitaxial layers as low as ∼104 cm−2. Samples were grown by both gas-source molecular beam epitaxy and ultrahigh vacuum chemical vapor deposition.

The use of supersonically injected pulses of phosphine to achieve uniform and high levels of n-type doping in Si during gas-source molecular beam epitaxy is demonstrated. Uniform n-type doping up to levels of 5×1019 cm−3 is obtained. SiGe/Si junction diodes made with this doping technique show good doping profiles and rectifying characteristics.

Harmonic emissions of nonlinear bulk acoustic wave (BAW) resonators with their different configurations are demonstrated and analysed. With the anti-polarisation configuration of the piezoelectric resonators, the second harmonic emissions are dramatically reduced. However, the anti-series configuration of dual BAW resonators exhibits a sharp increase in second harmonic emissions near the anti-resonance frequency. By investigating the phase difference of the generated harmonic waves, the reason for that sharp increase has been successfully analysed.

A common base five-stage D-band amplifier developed in a 0.18-μm SiGe HBT technology is presented. An inductive positive feedback technique is employed to enhance the gain, leading to 12.2 dB peak gain at 135 GHz with a power consumption of 67.2 mW. Measured output saturated power was - 5.8 dBm. The total chip area including pads is 1.54 × 0.56 mm 2 .

Using Si/SiGe heterojunction bipolar transistors with a maximum oscillation frequency of 52 GHz and a novel structure for passive components, a two-stage K-band lumped-element amplifier has been designed and fabricated on high-resistivity Si substrates. The chip size including biasing and RF chokes is 0.92/spl times/0.67 mm/sup 2/.

Presented is a D-band divide-by-3 injection-locked frequency divider (ILFD) based on a ring oscillator in a 0.18 µm SiGe BiCMOS technology. The ILFD exhibits a locking range of 7.9 GHz (132.5–140.4 GHz) at an input signal power of −2 dBm, dissipating a total DC power of 71.2 mW. The ILFD core occupies an area of 0.0021 mm2.

A 138 GHz down-conversion mixer with a branch-line coupler has been developed based on a 90 nm CMOS technology. The fabricated mixer shows a differential conversion gain of 3.7 dB with the mixer core drawing a current 0.66 mA from a 1.2 V supply. The 1 dB gain compression point is estimated to be larger than −6 dBm. The mixer occupies 0.61 × 0.62 mm2 of chip area excluding pads.

A V-band wideband variable gain low-noise amplifier (VGLNA) with a 3 dB bandwidth of 14 GHz (58–72 GHz) is developed in a 65 nm RFCMOS technology. The three-stage VGLNA, adopting the current steering method for the gain control, shows a measured peak power gain of 21.8 dB with a 1 dB gain flatness of 10 GHz (60–70 GHz). With tuning voltage adjusted from 0.8 to 2.8 V, the gain and noise figure are varied from 21.8 to 12.8 dB and from 4.2 to 5.7 dB, respectively, at 64 GHz. Input P−1dB was measured to be −22.1 dBm. DC power consumption is 36 mW with VDD=1.2 V and the chip size is 0.75×0.65 mm.