Search

We propose a new approach for the extraction of the equivalent parameters of quartz tuning forks used as sensors by means of noise measurements. Noise is used as the test signal for the determination, by means of spectral analysis, of the frequency response of a circuit including the quartz tuning fork whose parameters need to be determined. A new approach for the analysis of strongly peaked noise spectra was developed in order to allow the correct measurement of the strongly peaked noise spectrum at the output of the system, which is the result of the high-quality factor of any quartz tuning fork-based sensor. With the approach we propose, the best compromise in terms of accuracy and measurement time can be obtained in a single measurement run. The performances of the approach we propose are discussed in comparison with those that can be obtained from a swept spectrum approach in the same operating conditions.

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performedex situand transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

The main requirement for using the Fluctuation Enhanced Sensing technique is the ability to perform low-frequency noise measurements. The portability of the measurement system is also a quite desirable feature not limited to this specific application. In this paper, an approach for the realization of a dual channel spectrum analyzer that is capable of exploring frequencies down to DC, although based on a USB sound card, is proposed. The lower frequency range of the input signals, which is outside the frequency range of the sound board, is upconverted to higher frequencies by means of a very simple modulation board. Then, the entire spectrum is reconstructed numerically by proper elaboration. With the exception of the modulation board, the approach we propose does not rely on any specific hardware. Thanks to the efficiency of the spectra estimation and reconstruction software, which is based on a public domain library, the system can be built on a low-cost computer single board computer, such as the Raspberry PI3. Moreover, when equipped with an optical TCP/IP link, it behaves as a compact spectrum analyzer that along with the device under test can be placed into a shielded environment, thus being isolated from external electromagnetic interferences.

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Knee injuries are among the most common health problems in the world. They not only affect people who practice sports, but also those who lead a rather sedentary life. Factors such as age, weight, working and leisure activities can affect the health of the knees, causing disorders such as inflammation, edema, deterioration of cartilage and osteoarthritis. Although for the diagnosis and treatment of the various pathologies it is always advisable to contact orthopedists and specialized structures, it would often be useful to monitor the state of health of the knees in order to evaluate the healing (or worsening) process and the effects of sport/motion activities or rehabilitation. In this perspective, a portable knee health monitoring system was developed to be used at home or in gyms and sports environments in general. Besides requiring a simple custom front end, the system relies on a PC audio board capable of a sampling rate of 192 kHz to perform bioimpedance measurements at frequencies in excess of 50 kHz. A simple numerical calibration procedure allows to obtain high accuracy while maintaining low hardware complexity. The software developed for the operation of the system is freely available to any researcher willing to experiment with the bioimpedance measurement approach we propose, ensuring the conditions of portability and low complexity. Primary (intracellular and extracellular resistances and cell membrane capacitance) and secondary (real and imaginary parts of the total impedance) bioimpedance parameters can be obtained and analyzed through direct measurements with reference to an equivalent circuit model. The functionality of the system has been tested on nine subjects with different well-known health conditions, providing encouraging results in terms of the ability to correlate bioimpedance measurements to the health status of the knees. If proper clinical trials were to confirm our preliminary results, a system such as the one we propose could be used for fast and frequent monitoring of knee joints, thus possibly reducing the frequency at which complex and expensive medical exams, sometimes involving long waiting lists, must be performed.

It is shown how some photovoltaic MOSFET drivers can be used for the realisation of a low noise, programmable voltage source, with a dynamic range that can easily exceed several tens of volts starting from standard ± 12 V power supplies. Such a source can be useful in the investigation of the electrical properties, and particularly noise properties, of organic thin film transistors on plastic substrates, since relatively large gate voltage sweeps are required in order to obtain a significant change in the conduction properties of the channel.

Focusing on the interplay between interface chemistry, electrochemistry, and integrated electronics, we show a novel low-cost and flexible biosensing platform for continuous glucose monitoring. The amperometric biosensing system features a planar three-electrode structure on a plastic substrate, and a wireless near-field communication-powered electronic system performing sensor analog front-end, A/D conversion, digital control, and display tasks. The working electrode is made of electropolymerized poly (3,4-ethylenedioxythiophene) film onto a polyethylene terephthalate/gold electrode followed by immobilization of cross-linked glucose oxidase by glutaraldehyde. The advantages offered by such a device, including low-cost materials and instrumentation as well as the good sensitivity of 9.24 $\mu \text{A}/({\mathrm {mM}} \cdot {\mathrm {cm}}^{2})$ are promising tools for point-of-care monitoring. It is demonstrated that the devices are good candidates for the development of advanced sensing approaches based on the investigation of the noise produced during operation (fluctuation-enhanced sensing).

In this paper, we discuss a few techniques that allow an effective reduction of the background noise and/or the reduction of the measurement time when performing voltage noise measurements by employing a number of nominally identical voltage amplifiers with negligible equivalent input current noise. It is demonstrated in particular that, if $N\ (N > 2)$ voltage amplifiers are connected to the device under test and if the properties of cross-correlation among all $N$ acquisition channels connected to the output of each amplifier are exploited, the time required for obtaining a given accuracy is reduced by a factor $N(N - 1)/2$ with respect to the conventional setup for cross-correlation that employs only two channels. From another point of view, the effective background noise is reduced for constant measurement time. Such a factor can be further increased if amplifier paralleling is also employed for reducing the equivalent input voltage noise for each channel. Measurements on two different setups employing up to four channels and up to eight channels are presented that confirm the expected reduction factors in measurement times.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance–voltage, and noise measurements. Results suggest that transport in the CYTOP™ gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier $\phi _{B} \approx 1$ eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility $\mu \theta $ estimated in the order of $10^{-9}$ cm2/(Vs). Gate current noise follows a 1/ $f$ law and it is found to be proportional to $I_{G}^{2}$ , which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the total retention time is limited by the leakage associated with state “0” due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time.

In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.

In this paper, the authors demonstrate that a proper connection of two or more low-cost low-accuracy digital-analog converters can be used for the realization of a high-accuracy static analog memory (SAM). High-accuracy SAM is a circuit behaving as a high-accuracy sample and hold block with indefinite hold capability. The proposed topology can be applied both at the board level and at the integrated-circuit level when designing compact and low-cost devices for automated test equipment. In fact, as it will be demonstrated in this paper, high accuracy can be guaranteed by design, without the need for any calibration procedure. The proposed approach can therefore be considered as a possible and advantageous alternative to the conventional methods employed for the realization of high-accuracy multiple-output programmable voltage or current sources. A prototype of the SAM, based on the proposed approach, has been assembled and tested. As it will be shown, the obtained experimental results fully confirm the validity of the approach

Ultralow noise measurements often require the application of signal processing and correction techniques to go beyond the noise performances of front-end amplifiers. In this paper, a new method for the voltage noise measurement is proposed, which allows, at least in principle, the complete elimination of the noise introduced by the amplifiers used for the measurements. This is obtained by resorting to the conventional cross-correlation technique for the elimination of the contribution of the equivalent input voltage noise of the amplifiers and by using a new three-step-measurement procedure that exploits different amplifier-configuration measurements in order to subtract the contribution of the equivalent input current noise of the amplifiers

In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO/sub 2/. Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

In this work we propose a channel backscattering model in which increased carrier temperature at the top of the potential energy barrier in the channel is taken into account. This model represents an extension of a previous model by the same authors which highlighted the importance of considering the partially ballistic transport between the source contact and the top of the potential energy barrier in the channel. The increase of carrier temperature is precisely due to energy dissipation between the source contact and the top of the barrier caused by the high saturation current. To support our discussion, accurate 2D full band Monte Carlo device simulations with quantum correction have been performed in double gate nMOSFETs for different geometries (gate length down to 10 nm), biases and lattice temperatures. Including the effective carrier temperature is especially important to properly treat the high inversion regime, where previous backscattering models usually fail.

In this paper we critically review and compare experimental methods, based on the Lundstrom model, to extract the channel backscattering ratio in nano MOSFETs. Basically two experimental methods are currently used, the most common of them is based on the measurement of the saturation drain current at different temperatures. We show that this method is affected by very poor assumptions and that the extracted backscattering ratio strongly underestimates its actual value posing particular attention to the backscattering actually extracted in nano devices. The second method is based on the direct measurement of the inversion charge by CV characteristics and gets closer to the physics of the backscattering model. We show, through measurements in high mobility p-germanium devices, how the temperature-based method gives the same result of the CV-based method once that its approximations are removed. Moreover we show that the CV-based method uses a number of approximations which are partially inconsistent with the model. In particular we show, with the aid of 2D quantum corrected device simulations, that the value of the barrier lowering obtained through the CV-based method is totally inconsistent with the barrier lowering used to correct the inversion charge and that the extracted saturation inversion charge is underestimated.

In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate length down to 70 nm. Moreover we propose an extension of the backscattering model to the case of 2D geometries (e.g. bulk MOSFETs). We found that, in this case, the backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1D approach can be significantly different from the real 2D value.

We propose a model for partially ballistic MOSFETs and for channel backscattering that is alternative to the well known Lundstrom model and is more accurate from the point of view of the actual energy distribution of carriers. The key point is that we do not use the concept of "virtual source". Our model differs from the Lundstrom model in two assumptions: i) the reflection coefficients from the top of the energy barrier to the drain and from top of the barrier to the source are approximately equal (whereas in the Lundstrom model the latter is zero), and ii) inelastic scattering is assumed through a ratio of the average velocity of forward-going carriers to that of backward-going carriers at the top of the barrier kv > 1 (=1 in the Lundstrom model). We support our assumptions with 2D full band Monte Carlo (MC) simulations including quantum corrections in nMOSFETs. We show that our model allows to extract from the electrical characteristics a backscattering coefficient very close to that obtained from the solution of the Boltzmann transport equation, whereas the Lundstrom model overestimates backscattering by up to 40%.

In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages: (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface: (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique. (C) 2009

In this paper, a comprehensive study of hot- carrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: (1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; (2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and (3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.

In this paper we investigate warm electron injection in a double gate SONOS memory by means of 2D full-band Monte Carlo simulations of the Boltzmann Transport Equation (BTE). Electrons are accelerated in the channel by a drain-to-source voltage VDS smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based post-processing method as a function of the particle distribution obtained from Monte Carlo. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias and warm electron injection can be an interesting option for programming when short channel effects prohibit the application of larger drain bias.

In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors (pMOSFETs) with a Si passivated surface. The gate stack consists of HfO(2)/SiO(2) dielectric with TiN/TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole-Frenkel conduction. Gate current 1/f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole-Frenkel conduction and the high gate current 1/f noise in Ge pMOSFETs. (C) 2008

In this paper, we investigate warm electron injection (WEI) as a mechanism for NOR programming of double-gate SONOS memories through two dimensional (2D) full-band Monte Carlo simulations. WEI is characterized by an applied VDS smaller than 3.15 V, so that electrons cannot easily accumulate a kinetic energy larger than the height of the Si/SiO2 barrier. We perform a time-dependent simulation of the program operation where the local gate current density is computed with a continuum-based method and is adiabatically separated from the 2D full Monte Carlo simulation used to obtain the electron distribution in the phase space. Trapping and detrapping from the nitride layer is taken into account by using a simplified Shockley–Read–Hall model. In this way, we are able to compute the time evolution of the charge stored in the nitride layer and of the threshold voltages corresponding to forward and reverse biases. We show that WEI is a viable option for NOR programming in order to reduce power supply and preserve...