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In this paper, we propose an effective neural network algorithm to perform singular value decomposition (SVD) of a cross-correlation matrix between two data streams. Different from traditional algorithms, the newly proposed algorithm can extract not only the principal singular vectors but also the corresponding principal singular values. First, a dynamical system is obtained from the gradient flow, which is obtained from optimization of a novel information criterion. Then, based on the dynamical system, a stable neural network algorithm, which can extract the left and right principal singular vectors, is obtained. Moreover, by satisfying orthogonality instead of orthonormality, we are able to extract the normalization scale factor as the corresponding singular value. In this case, the principal singular triplet (principal singular vectors and the corresponding singular value) of the cross-correlation matrix can be extracted by using the proposed algorithm. What’s more, the proposed algorithm can also be used for multiple PSTs extraction on the basis of sequential method. Then, convergence analysis shows that the proposed algorithm converges to the stable equilibrium point with probability 1. Last, experiment results show that the proposed algorithm is fast and stable in convergence, and can also extract multiple PSTs efficiently.

Generalized eigenvalue decomposition has many advantages when it is applied in modern signal processing. Compared with other methods, neural network model-based algorithms provide an efficient way to solve such problems online. Generalized feature extraction algorithms based on neural network models have been described in the literature. However, the majority of the existing algorithms can only extract the principal generalized eigenvector(s) or eigensubspace. To extract principal and minor generalized eigenvectors from two vector sequences, in this paper, two different information criteria are proposed, and a unified algorithm for the extraction of multiple components in a parallel way by simply altering the sign is derived based on these information criteria, which is feasible for generalized principal and minor component analysis. Moreover, all the corresponding principal and minor generalized eigenvalues can be extracted simultaneously because the desired equilibrium point depends on these values. Thus, the proposed algorithm can perform multiple generalized eigenpair extraction. The proposed algorithm possesses four properties: unification, self-stability, parallel extraction and generalized eigenpair extraction, that few of the existing algorithms can encompass. The global convergence and self-stability property of the proposed algorithm are proved through the Lyapunov method and ordinary differential equation method, respectively. The proposed algorithm has a fast convergence speed, high precision and strong tracking ability. Finally, numerical examples and applications are explored to further demonstrate the efficiency of the proposed algorithm.

General Purpose Graphics Processing Units (GPGPUs) have been extensively used in the last decade as accelerators in high demanding applications, such as multimedia processing and high-performance computing. Nowadays, these devices are becoming popular even in safety-critical applications, such as in autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of transient faults, such as those produced by radiation effects. Among those effects, Single Event Upsets (SEUs), which are the focus of this paper, can cause application misbehaviors, which may lead to catastrophic consequences. In this work, we first describe how we extended the capabilities of an open-source VHDL GPGPU model (FlexGrip) and developed a new version named FlexGripPlus to study and analyze the effects of SEUs in a GPGPU in a much more detailed manner. We also performed extensive fault injection campaigns using FlexGripPlus, which allowed identifying the most critical effects within the GPGPU architecture. We finally focused on the scheduler controller since it represents a module that is specific to the GPGPU architecture and showed that it has different levels of SEU sensibility depending on the affected location. Moreover, the results of additional analyses varying the number of parallel execution units in the system are presented, demonstrating the correlation between the number of execution units in a GPGPU and the system reliability.

Radiation-induced single-event transients (SETs) are the leading cause of mal-operations in CMOS nanometric integrated circuits. The increasing complexity of advanced CMOS digital circuits makes SET effects investigation a rising challenge. In this work, we propose a 3-D-oriented simulation approach able to model the passage of heavy ion particles through the physical structures of modern digital circuits implemented with ultrananometric manufacturing processes. The proposed approach is able to generate the transient voltage pulse in response to a heavy-ion track and identify the effects of the sensitive volume and contact structure. We present heavy-ion radiation test experiments performed on a 65-nm Flash-based CMOS technology process and, as proof-of-concept, we successfully compared the SET cross sections showing comparable results.

Generalized minor component analysis (GMCA) is of great use in modern signal processing. The GMCA algorithms can be simplified to extract the minor generalized eigenvector of the autocorrelation input matrices pencil. In contrast to batching methods, the Hebbian-rule-based algorithm can extract the minor generalized eigenvector online. Few Hebbian-rule-based GMCA algorithms have been reported in the literature, and most of them are not self-stabilizing. Thus, a novel algorithm for GMCA, which is advantageous in terms of good convergence speed, self-stabilizing property, and multiple generalized minor component extraction in sequence, is proposed in this paper. A theoretical analysis verifies these properties via matrix theory and the deterministic discrete-time method. Numerical simulations are conducted to further demonstrate the advantages of the proposed algorithm.

The partial least squares (PLS) method has been widely used in quality-related industrial process monitoring because of its ability to extract quality-related information. Generally, online quality monitoring data cannot be obtained in real time, and in this case, updating the online monitoring model is a serious challenge. In this paper, an online monitoring dynamic PLS (OMD-PLS) model that uses the relation between time-delay process data and time-delay quality data is proposed. To accurately monitor the quality-related and process-related fault data, we also propose an online monitoring dynamic concurrent PLS (OMDC-PLS) model based on OMD-PLS, which has the ability to detect slight deviations. Furthermore, an alarm-parameter alarm method based on the OMDC-PLS model is proposed and effectively reduces the false alarm rate. Finally, numerical simulations and the Tennessee Eastman process are used to illustrate the effectiveness of the proposed methods.

The robust guaranteed cost consensus problem of high-order discrete-time linear multi-agent systems (MASs) with parameter uncertainties and time-varying delays is studied, and a linear consensus protocol of it is designed. Norm-bounded uncertainties and polytopic uncertainties are considered. First, the idea of robust guaranteed cost control is introduced into consensus problems for the MASs, where a cost function is defined based on state errors among neighbouring agents and control inputs of all the agents. Second, by constructing suitable Lyapunov functions and using the stability theory of discrete-time linear systems, two sufficient linear matrix inequality conditions are derived to insure that high-order discrete-time linear MASs with the two types of parameter uncertainties and time-varying delays reach robust guaranteed cost consensus. At the same time, two upper bounds of the guaranteed cost function are also given. Third, convergence results are given as final consensus values of the MASs with parameter uncertainties and time-varying delays. Finally, two numerical comparisons are given to illustrate the correctness and availability of the theoretical results.

In recent years, three-dimensional IC (3D IC) has gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation and achievable clock frequencies. However, the reliability of 3D ICs regarding soft errors induced by radiation is not investigated yet. In this work, we propose a method for evaluating the sensitivity of 3D ICs to Single Event Transient induced by Heavy Ions. The flow starts with identifying the characteristics of the generated transient pulses with respect to the radiation profile and 3D layout of the design. Secondly, our method provides a Dynamic Error Rate using a Simulation-based Fault Injection environment. Experimental results achieved applying the approach on a 15nm 3D configurable Look-Up-Table (LUT) designed on two tiers demonstrated the feasibility of the method, showing the vulnerability characterization of four different functional configurations using eight different types of heavy ions.

General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video processing thanks to their powerful parallel architecture. In the last years, GPGPUs have been considered also for safety-critical applications, such as autonomous and semi-autonomous car driving systems. New GPGPU devices include an increasing number of parallel cores in order to increase throughput and performance. This increment in the number of cores and the requirements in terms of power consumption force designers to use aggressive semiconductor technologies.Nevertheless, those new devices can be seriously affected by radiation effects, modeled as Single Event Upsets (SEUs). SEUs could generate unexpected operation effects in the applications which could be unacceptable for the safety-critical ones. This work analyzes the SEU effects resorting to an open-source model of a GPGPU based on the Nvidia’s G80 architecture and aims at complementing previous analysis based on radiation experiments

General Purpose Graphics Processing Units (GPGPUs) have been used in the last decades as accelerators in high demanding data processing applications, such as multimedia processing and high-performance computing. Nowadays, these devices are becoming popular even in safety-critical applications, such as autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of transient faults, such as those produced by radiation effects. These effects can be represented in the system as Single Event Upsets (SEUs) and are able to generate intolerable application misbehaviors in safety critical environments. In this work, we extended the capabilities of an open-source VHDL GPGPU model (FlexGrip) in order to study and analyze in a much more detailed manner the effects of SEUs in some critical modules within a GPGPU. Simulation results showed that scheduler controller has different levels of SEU sensibility depending on the affected location. Moreover, a reduced number of execution units, in the GPGPU can decrease the system reliability.

Commercial SRAM-based FPGAs are widely used in aerospace applications thanks to their limited costs and high performances. Dynamic Partial Reconfigurability (DPR) allows to rewrite sections of the configuration memory of these devices while they are normally working. This is a powerful feature which provides advantages in terms of area, power consumption and flexibility. Moreover, DPR plays the main role in the recovery from faults that may occur in the configuration memory of the device when it operates in a radiation environment. Indeed, ionized particles which strike electronic devices, may cause various types of events. The Single Event Transient (SET) is a well-known phenomenon, which affects sensitive nodes causing transitory voltage spikes that can be sampled by a memory element, causing a fault. In this paper, an evaluation methodology for the errors caused by SETs during the reconfiguration of the configuration memory in SRAM-based FPGAs is presented. The evaluation methodology includes the fault model evaluation and the development of a fault injection and error evaluation workflow. The illustrated methodology has been applied on a physical device implementing a benchmark design and the obtained results are reported.

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.

General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applicationssuch as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field.Functional tests adoptingSoftware-based Self-test(, orSBST)are an effective solution since they providebenefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to knownmethods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions.This paper focusesOonone of the most relevant module consists on the scheduler corewhich is in charge of managing different scalar computational cores and the different executed threads.At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we providesome guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. This paper presents a methodology for accurate characterization of radiation-induced Single Event Transients (SETs) effects in SRAM-based Field Programmable Gate Arrays (FPGAs). A technique based on internal electrical pulse injection is proposed for emulating SET within logic resources of SRAM-based FPGAs. Experimental results provide detailed characterization of basic logic gates.

Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist.

SRAM-based FPGA devices manufactured in FinFET technologies provide performances and characteristics suitable for avionics and aerospace applications. The estimation of error rate sensitivity to harsh environments is a major concern for enabling their usage on such application fields. In this paper, we propose a new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation. Experimental results provide a comparison between radiation test campaigns, which demonstrates the feasibility of the proposed solution.

Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-Programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.

Due to the decreasing feature sizes of VLSI circuits, radiation induced Single Event Transients (SETs) are increasingly dominating the event ratio on modern VLSI devices. In particular, Flash-based FPGAs are characterized by the main concern of radiation-induced voltage glitches or SETs in the combinational logic. Transient pulses can be sampled by a storage element and can propagate through the circuit up to the outputs and leading to an error. In this paper, we propose a complete implementation flow including sensitivity analysis, fault tolerant mapping and fault tolerance-oriented place and route for the effective design of SET tolerant circuits on Flash-based FPGAs. In details, the proposed method allows accurate measurement of the transient pulse source induced by radiation particles and estimation of the SET error rate on the overall circuit. Besides the developed method provides a netlist mapping and place and route tool for the selective mitigation of SET effects. The proposed method has been applied to an industrial design oriented to the Euclid European Space Agency mission including more than ten different modules. The obtained results show an improvement of the total filtering capability of around 43 times with respect to the original netlist without affecting the timing constraints of the circuit.

Due to rapid technology scaling, electronic devices are becoming more susceptible against soft errors induced by radiation particles, which is a serious challenge for aerospace applications. Meanwhile Field Programmable Gate Array (FPGA) devices have been attracting attention in safety- and mission-critical applications in recent years with the increasing performance and flexibility they provide. Among different types of FPGAs according to the device technology, the SRAM-based FPGA has a higher sensitivity against soft errors as SRAM cell, which is used for storing the configuration data of the circuit design implemented and mapped on the FPGA, is one of the most sensitive devices against radiation induced soft errors. Hence, to guarantee the usage of SRAM-based FPGAs in safety critical environments, the design mapped on it requires an effective verification and validation procedure. Radiation test is one of the verification methods regarding the effects of radiation induced soft errors. In this paper, we present an automated setup for monitoring the soft errors during the radiation test and we compared the measurement obtained from radiation test with the one provided by analytical tools. The experimental results we gained demonstrated the feasibility of the proposed measurement platform.

Hybrid error-detection techniques combine software techniques with an external hardware module that monitors the execution of a microprocessor. The external hardware module typically observes the control flow at the input or at the output of the microprocessor and compares it with the expected one. This paper proposes a new hybrid technique that monitors the control flow at both points and compares them to detect possible errors. The proposed approach does not require any software modification to detect control-flow errors. Fault-injection campaigns have been performed on an LEON3 microprocessor. The results show full control-flow error detection with no performance degradation and small area overhead. A complete solution can be obtained by complementing the proposed approach with software fault-tolerance techniques for data errors. This work was supported in part by the Spanish Government under Contract TEC2010-22095-C03-03.

In this paper, we propose a methodology for executing simulation using analytical models for the execution of SET propagation on System-on-a-Chip implemented on Flash-based FPGAs. Analysis performed on EUCLID-based circuit design demonstrated its effectiveness.

The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.

When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.

In this paper we combine a set of software-based fault tolerance techniques with a hardware module that monitors the trace port, and explore from an experimental point of view the fault coverage against soft errors in COTS processors that can be achieved. The costs in terms of performance and memory are also evaluated. Fault injection results show fault coverage is superior to the state-of-the-art techniques with lower performance and memory overheads.

The present work proposes a methodology to predict radiation-induced Single Event Transient (SET) phenomena within the silicon structure of Flash-based FPGA devices. The method is based on a MonteCarlo analysis, which allows to calculate the effective duration and amplitude of the SET once generated by the radiation strike. The method allows to effectively characterize the sensitivity of a circuit against the transient effect phenomenon. Experimental results provide a comparison between different radiation tests data, performed with different Linear Energy Transfer (LET) and the respective sensitiveness of SETs.

As microprocessors are increasingly used in safety-critical applications, there is a growing demand for effective fault-tolerance techniques that can mitigate the effects of soft errors while reducing intrusiveness and minimizing the impact on performance and power consumption. To this purpose, approaches that are based on monitoring the microprocessor operation through an external interface in a non-intrusive manner have recently been proposed. In this paper we focus on the use of the trace interface for on-line monitoring. This interface provides detailed information about the instructions executed by the processor and can be reused to support error detection and correction in several ways, including multi-processors in hardware redundancy, time redundancy and control-flow checking.

This paper proposes a mapping tool for selectively mitigate radiation-induced Single Event Transient phenomena within the silicon structure of Microsemi RTG4 Radiation hardened Flash-based FPGAs. Experimental results on three benchmark circuits demonstrated effective SET mitigation.

Over the past decade, the complexity of electronic devices in the automotive systems increased significantly. The modern high level vehicles include more than 70 Electronic Control Units (ECUs) aimed at managing the powertrain of the vehicle, and improving passengers' comfort and safety. ECU microcontrollers aimed at the control of the fuel injection system have a key role. In this paper we present a new FPGA-based platform able to supervise and validate Commercial-Off-The-Shelf timer modules used in today state-of-the-art software applications for automotive fuel injection system with an accuracy improvement of more than 20% with respect to traditional approach. The proposed approach allows an effective and accurate validation of timing signals and it has two main advantages: can be customized with the exact timing module configurations to meet the exigency of new tests and allows effective modularity design test. As case study two industrial Time Modules manufactured by Freescale and Bosch have been used. The experimental analysis demonstrates the capability of the proposed approach providing a timing and angular precision of 10 ns and 10−5 degrees respectively.

General Purpose Graphics Processing Units GPGPUs are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.

This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial tool-chain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average.

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.

Technology scaling enables the Field Programmable Gate Arrays (FPGAs) provide increasing computing power while remain low power consumption. Together with the high flexibility for application design and deployment, FPGAs have become popular even in safety- and mission-critical applications. Meanwhile, Commercial Off-The-Shelf (COTS) components are often used in system design to reduce time-to-market and development cost. In this paper, we are proposing a new method for the analysis and mitigation of Single Event Upsets (SEUs) on SRAM-based FPGAs. The method is based on an analytical analyzer algorithm able to accurately estimate the application error rate; furthermore, the same developed algorithm is able to implement mitigation rules. We present the radiation experiment results for analysis and mitigation of Single Event Upsets (SEUs) in an ARM-based SoC implemented on Xilinx Virtex-V FPGA demonstrating the feasibility of the analysis tool and the effectiveness of the mitigation method.

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

The increasing technology node scaling makes VLSI devices extremely vulnerable to Single Event Effects (SEEs) induced by highly charged particles such as heavy ions, increasing the sensitivity to Single Event Transients (SETs). In this paper, we describe a new methodology combining an analytical and oriented model for analyzing the sensitivity of SET nanometric technologies. The paper includes radiation test experiments performed on Flash-based FPGAs using heavy ions radiation beam. Experimental results are detailed and commented demonstrating the effective mitigation capabilities thanks to the adoption of the developed model.

Flash-based Field Programmable Gate Arrays (Flash-based FPGAs) are becoming more and more interesting for safety critical applications due to their re-programmability features while being non-volatile. However, Single Event Transients (SETs) in combinational logic represent their primary source of critical errors since they can propagate and change their shape traversing combinational paths and being broadened and amplified before sampled by sequential Flip-Flops. In this paper the SET sensitivity of circuits implemented in Flash-based FPGAs is mitigated with respect to the working frequency and different FPGA routing architecture. We outline a parametric routing scheme and placement and routing tools based on an iterative partitioning algorithm able to generate high performance circuits by reducing the wires delay and reducing the SET sensitivity. The efficiency of the proposed tools has been evaluated on a Microsemi Flash-based FPGA implementing different benchmark circuits including a RISC microprocessor. Experimental results demonstrated the reduction of SET sensitivity of more than 30% on the average versus state-of-the-art mitigation solutions and a performance improvement of about 10% of the nominal working frequency.

Transient faults can affect the behavior of electronic systems, and represent a major issue in many safety-critical applications. This paper focuses on Control Flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers. The new method achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost: moreover, the proposed technique does not involve any change either in the processor hardware or in the application software, and works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RFaPI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic, its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RFaPI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RFaPI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power ArchitectureTM.

In the present paper, we propose a new design flow for the analysis and the implementation of circuits on Flash-based FPGAs hardened against Single Event Effects (SEEs). The solution we developed is based on two phases: 1) an analyzer algorithm able to evaluate the propagations of SETs through logic gates; 2) a hardening algorithm able to place and route a circuit by means of optimal electrical filtering and selective guard gates insertions. The effectiveness of the proposed design flow has been evaluated by performing hardening on seven benchmark circuits and comparing the results using different implementation approaches on 130nm Flash-based technology. The obtained results have been validated against radiation-beam testing using heavy-ions and demonstrated that our solution is able to decrease the circuits sensitivity versus SEE by two orders of magnitude with a reduction of resource overhead of 83 % with respect to traditional mitigation approaches.

Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.