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Summary: Approximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 ×10−5 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR). [ABSTRACT FROM AUTHOR]

Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Because different conduction mechanisms can dominate the gate and drain/source leakage currents, mainly depending on the insulating materials used as gate dielectric, the dimensions of the gate structure, and the transistor operation regime, we proposed an improved analytical model to describe the behavior of these currents in silicon on insulator fin-shaped field-effect transistor devices by taking into account changes in the aforementioned factors. This model considers the direct tunneling, trap-assisted tunneling, and band-to-band tunneling as the predominating mechanisms for leakage currents associated with the gate structure. These specific features make the model valid for a wide operation range and include its impact on the drain leakage current. The implementation of this model in Verilog-A code is presented in this work, which allows calculating quickly and accurately the scaling constraint of a specific gate dielectric material and the power consumption that yields such leakage currents in a circuit by using commercial simulators. All presented results are validated with experimental data from fin-shaped field-effect transistors with different dimensions and gate dielectric materials and performed under different bias conditions. [ABSTRACT FROM AUTHOR]

MOS-Modelle und Parameterextraktion Arbeitskreis (MOS-AK) is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high-level behavioural modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open-source compact model standardization activities and presents advanced topics in metal-oxide-semiconductor field-effect transistor modelling, focusing in particular on analogue/radio frequency applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The opensource computer-aided design tools Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated radio frequency model performance is evaluated and compared with experimental results for 90 nm CMOS technology. [ABSTRACT FROM AUTHOR]

SUMMARY This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this work, we propose the subgap density-of-states (DOS) based device-circuit co-design platform for solution-processed organic integrated circuits. For the circuit simulation, analytical I-V and C-V model were established from experimentally extracted DOS parameters, incorporated into HSPICE via Verilog-A, and verified by comparing the simulation result with the measured characteristics of inverter integrated with solution-processed polymer-based organic thin-film-transistors. Furthermore, as the case study, it was shown by using our well-calibrated simulation platform that the pass-transistor type logic was potentially promising in low-power and high-speed solution processed organic integrated circuits. [ABSTRACT FROM AUTHOR]

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms. [ABSTRACT FROM AUTHOR]

The ‘Quite universal circuit simulator’ (Qucs) is an open source circuit simulator supporting Verilog-A compact model standardization. This paper describes a number of compact semiconductor device and circuit macromodelling techniques that have been implemented in recent Qucs releases, stressing those techniques that are not found in SPICE 2g6 or 3f5. It also introduces a novel hierarchical approach to Verilog-A compact model and circuit macromodel construction based on non-linear equation-defined devices, linear-controlled sources and noise generators embedded in subcircuits. To illustrate the new approach, the properties and models of a number of components with electrical and non-electrical characteristics are described. These models demonstrate how recent trends in open source simulation technology use embedded equations as integral elements in component and physical process models. Copyright © 2008 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Recent trends in compact device modelling and circuit simulation suggest a growing movement towards standardization of Verilog-A as a vehicle for semiconductor device specification and model interchange among commercial and open source simulators. This paper introduces a nonlinear equation-defined device (EDD) characterized by current, voltage and charge equations with a similar syntax to Verilog-A. The EDD has been implemented in Qucs and used extensively as a central feature in an interactive modelling system that allows straightforward prototyping of compact device models prior to translation into Verilog-A. To illustrate the properties and the use of the Qucs EDD a number of examples centred on well-known SPICE models are described. Copyright © 2008 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Although cache control mechanisms for use in multiprocessors that use a multistage interconnection network (MIN) as the interconnecting network have been proposed in which a directory or the cache itself is built into the switches in the MIN, the structure of the switches in these methods have been complex and there therefore remains room for improvement. Our research group has therefore proposed a MIN with directory cache switch (MINDIC) that implements cache control by only building small- capacity directory caches into the switches. This paper reports on the results of evaluating MINDIC using a clock level simulator. The results reveal that MINDIC is able to achieve a level of cache control efficiency that is equal to that of a full map directory management scheme by setting the number of entries in the MINDIC directory caches to approximately 2048 entries. The results also show that the amount of memory required for the directory can be greatly reduced by MINDIC. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(9): 11–23, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20301 [ABSTRACT FROM AUTHOR]

An accurate approximation of base-2 logarithm (log2) in hardware can be used to simplify many complex calculations such as power and division. There are several existing low error approximations of log2, but those approaches are either slow or require a lot of memory. In this letter, the authors propose a new shift and add-based approximation of log2 using Maclaurin series. Experimental results show that with the proposed method maximum error is as less as 0.0102 and average error is reduced to 0.0050. Being independent of a number of bits this approximation can be used for any range of numbers. Results of hardware implementation show that area, power, and frequency of the proposed method are comparable with the existing methods. [ABSTRACT FROM AUTHOR]

A self-adjusting sensing circuit spin-torque transfer magnetic random access memory (STT-MRAM) is proposed. STT-MRAM is considered to be the most promising candidate among the new emerging memories. However, read performance has emerged as a new bottleneck, because of its low tunnelling magneto-resistance ratio (TMR) and low read current. The proposed self-adjusting sensing circuit shows an improved sensing margin, overcoming the weaknesses of the STT-MRAM. The proposed circuit using Verilog-A model, a 65 nm complementary metal-oxide-semiconductor process also evaluated, and Monte Carlo analysis. The results of analysis show that the proposed circuit ensures a certain sensing margin, which is more than 200 mV in TMR 150% and about 50 mV in TMR 100%. [ABSTRACT FROM AUTHOR]

Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library. [ABSTRACT FROM AUTHOR]

Magnetic random access memory based on magnetic tunnel junctions (MTJs) is among the most attractive technologies of emerging nonvolatile memories. However, the integration of spin-based devices in integrated circuits is still hindered by a lack of established standard electrical simulator models. Many of such models have been proposed during the past decade which can be classified into two categories: the first ones are based on the physical Landau-Lifshitz-Gilbert (LLG) equation describing real-time MTJ magnetic switching dynamics; the second one uses analytical expressions for switching thresholds derived from the LLG equation. The aim of this reported work was to investigate for the first time the capability of each strategy to fulfil the need of industrial standard electrical simulation tools and pave the path towards a standard industrial model. Multi-simulator compatibility, efficient runtime, accuracy and reliability are the three main assets of a device model. It is shown that using the Cadence® tools suite with the Spectre® simulator, the LLG modelling strategy overcomes the analytical approach in terms of accuracy and speed with a 7x faster runtime. Both models require nearly the same hardware memory resources. [ABSTRACT FROM AUTHOR]