Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing.

Authors :: Labrado, C.
Thapliyal, H.
Source :: Electronics Letters (Wiley-Blackwell). 9/15/2016, Vol. 52 Issue 19, p1618-1619. 2p. 4 Diagrams, 2 Charts.
Publication Year :: 2016
Abstract: Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library. [ABSTRACT FROM AUTHOR]

Subjects :: *NANOMAGNETICS
*VERILOG (Computer hardware description language)
*POLARIZATION (Electricity)
*ELECTRIC inverters
*ELECTRIC circuit analysis

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