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A border trap (BT) evaluation method was established for SiO2/GeO2/Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiO2/GeO2/Ge gate stacks were fabricated by post-passivation thermal oxidation. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from GeO2/Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and the density (Nbt) was in the range of 1017-1018 cm−3. For n-type MOSCAPs, BTs at the position range of 2.8-3.4 nm from the GeO2/Ge interface were measured. The energy of these BTs were distributed in a relatively wide range near to the conduction band edge of Ge, and the Nbt was approximately one order of magnitude higher than those for p-MOSCAPs. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge.

Keeping in view the potential demands of 22 nm (and beyond) technology nodes for high-k dielectric materials, the device reliability was taken into consideration by selecting appropriate atomic scale deposition techniques and device characterization methods. This paper presents the fabrication of n-Si/ALD-ZrO2 gate stack with an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL). The problem of the gate leakage current has been resolved by post deposition annealing (PDA) of ZrO2 film ~ 11.63 nm in oxygen ambient on the silicon substrate followed by the pre-growth of SiON IL ~ 6.92 nm. The structural, morphological and film thickness studies have been performed by the characterization techniques such as XRD, AFM and FESEM respectively. Electrical characterizations such as capacitance-voltage (C-V) and current density-voltage (J-V) reveal the improved results for O2 annealed ZrO2 sample relative to the as-deposited ZrO2 sample in terms of suppressed gate leakage current (~ 2.8 × 10-8 A/cm2), increased dielectric constant (~ 33) and reduced effective oxide thickness (EOT~ 1.37 nm). Furthermore, in this paper, we will present comparative studies on types of gate stacks viz. HfO2/SiO2 , HfO2/SiON, Ar-annealed ZrO2/SiON, N2 annealed ZrO2/SiON and O2 annealed ZrO2/SiON and their comparative analysis indicates better results for O2 annealed ZrO2/SiON in terms of reduced EOT, reduced leakage current and increased dielectric constant. Figure 1

Germanium as a high mobility channel material is currently of considerable interest since Ge has both higher electron and hole mobility as compared to silicon (1). The deposition of high-k dielectrics on Ge has been a significant challenge because of high interface defects density, Dit (2). By considering the interface reaction kinetics, thermal budget various atomic layer deposition (ALD) schemes and interface treatments can be identified to get a stable dielectric with a robust interface. However, understanding of the interface kinetics and defect distribution into gate stack and/or Ge is still limited. In this work, we report the impact of different interface treatments on the p type Ge prior to any high-k layer deposition on defect generation. Ge surface was oxidized by a controlled chemical oxidation, slot-plane-antenna plasma oxidation and oxidation through vapor O3 treatment before ALD deposition of 1nm Al2O3/3.5nm ZrO2 for gate stack formation. These devices were characterized to evaluate the interface and possible bulk defects by deep level transient spectroscopy (DLTS), capacitance spectroscopy, conductance method in addition to standard I-V and C-V measurements. DLTS has the advantage to have the spectrum comparison among the interface treatments. Signature of these spectra can reveal the difference, which is more accurate than the defects estimated by Conductance method. DLTS also provides the signature of slow traps (~1ms) (Fig. 1) originating from the bulk or interface depending on the type of GeOx formation. Furthermore, we evaluate the defect distribution when the gate stack was subjected to a slot-plane antenna plasma oxidation prior to metal deposition. A TiN/Hf1-xZrxO2/Al2O3/Ge gate stack with six different Zr content was investigated (Fig. 2). Al2O3 was used to impede the Ge diffusion into the gate stack. Interface state density (Dit) and C-V hysteresis show that the mid-gap Dit tend to increase with decrease in EOT, possibly due to the undesirable native oxide formation on Ge. The author would like to thank Drs. Y.M. Ding (Western Digital Corporation, Shanghai, China), M.N. Bhuyian (Globalfoundries, Malta, NY, USA), K.L. Ganapathi (Indian Institute of Technology Madras, India), N. Bhat, (Indian Institute of Science, Bangalore, India) and K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, G. Nakamura, and G. J. Leusink of TEL Technology Center, America, Albany, NY, for their help in this work. References Arimura et al, IEDM Technical Digest, (2020) N. Bhuyian et al, ECS Journal of Solid-St. Sci. and Tech., vol. 7(2), N1-N6, (2018) G. Kolla et al, J. Vac. Sci. Technol. B, 36(2), 021201 (2018) Ding et al, IEEE Trans. on Dev. and Materials Reliability, 17(2), 349-354, (2017) Ding, et al, J. of Vac. Sci. and Technol. B, 34(2), 021203, 2016. Figure 1

Now-a-days, high-k dielectric materials are in demand as they not only inhibit direct tunneling but also ensures relatively thicker oxides. To replace SiO2 as gate dielectric, a number of high-k materials have been extensively studied such as aluminum oxide (Al2O3), zirconium dioxide (ZrO2), cerium oxide (CeO2), hafnium oxide (HfO2) and titanium dioxide (TiO2). Among them, ZrO2 is one of the most outstanding candidates due to its excellent chemical, physical and electrical properties such as good thermodynamic stability with silicon, high dielectric constant, high melting point, high refractive index, and sufficient band gap. Atomic layer deposition (ALD) method having the benefit of low temperature deposition and extremely precise thickness control has been utilized for the deposition of ZrO2 film. Additionally, the post deposition annealing (PDA) of ZrO2in argon (Ar) ambient has been performed along with Ti-Pt as bilayer metal gate. Taking into consideration the state-of-the-art research progress, we report the fabrication of ultra-thin silicon oxynitride (SiON) as a sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stackfollowed by post deposition annealing (PDA) of ZrO2 in argon (Ar) ambient. The surface roughness for the Ar annealed ZrO2 film measured using atomic force microscopy (AFM) was found to be 0.796 nm whereas the thicknesses of SiON SL ~ 5.34 nm and ZrO2 film ~ 11.63 nm were corroborated by field emission scanning electron microscope (FESEM) and spectroscopic ellipsometer (SE). Electrical characterizations such as capacitance voltage and current voltage measurements indicates the improved results for n-Si/ALD-ZrO2/Ti-Pt MOS capacitor in terms of various performance parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) and their determined values are 26, 2.1 nm, 8.75 × 10-9 A/cm2, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The noble concept of SiON SL along with the PDA of ZrO2 in Ar ambient can enable the further scaling of n-Si/SiON/ZrO2 gate stack without the adverse effects of gate leakage current. Some of the important results obtained from the reported work have been exemplified in the figures below. Figure 1

This work explored the performance evaluation of high-k gate stack on the analog and RF figure of merits (FOMs) of 9 nm Silicon-on-Insulator (SOI) FinFET. The results have been observed by replacing high-k dielectric with SiO2 material between gate and fin. The dielectrics investigated in this exploration are Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), Hafnium Dioxide (HfO2), and Aluminium Oxide (Al2O3). The characteristics such as DIBL (Drain Induced Barrier Lowering), SS (Subthreshold Slope), electron mobility, energy band, surface potential and switching ratio (Ion/Ioff) have been performed for the comparison analysis. Further, some important RF figure of merits (FOMs) has been explored and found that the high-k gate stacked SOI-FinFET configuration shows superior RF performance in terms of cut-off frequency (f T) and maximum oscillation frequency (f MAX), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). Thus the implementation of a high-k gate stack, the major limitations of our transistor device such as short channel effects (SCEs), leakage current, and parasitic capacitance have been reduced and pave the way for high switching and RF application.

1) Introduction Ge is one of the candidate materials for the future high performance MOSFET. In order to embody the high performance Ge-MOSFET, stacked gate dielectrics with thin Ge oxide interlayer, such as SiO2/GeO2 and Al2O3/GeOx, have been studied actively [1, 2]. On the other hand, in the case of Ge-MOS gate stacks, not only interface traps (ITs) but border traps (BTs) located in gate dielectric are also problematic because they degrade MOS characteristics and mobility of the MOSFET. For deep understanding and performance improvement of Ge MOS gate stacks, both density and position of BT in stacked gate dielectrics should be clarified. However, in-depth study of BT in Ge gate stacks is limited. Recently, we succeeded in separating the BT and IT signals using deep-level transient spectroscopy (DLTS) in SiO2/GeO2/Ge gate stacks grown by thermal and plasma oxidation [3,4]. In this study, the densities of IT (D it) and BT (N bt) in Al2O3/GeOx/p-Ge gate stacks grown by post plasma oxidation (PPO) were evaluated. In addition, to study the relationship between BTs and mobility of devices, Ge p-MOSFETs with Al2O3/GeOx/Ge gate stacks were also fabricated and characterized. The effect of BTs on the mobility of MOSFETs is also discussed. 2) Experimental P-type (100) Ge substrate with a doping concentration of 2.3×1016 cm-3 was used. After chemical cleaning by HF solution, the first layer of Al2O3 was deposited at 300°C by ALD with precursors of water and trimethylaluminum for 3, 9, 14 and 20 cycles, corresponding to four samples, followed by PPO using electron cyclotron resonance (ECR) at room temperature. The GeOx thicknesses in Al2O3 gate stacks with 3, 9, 14 and 20 ALD cycles were 0.87, 0.42, 0.06, and 0.16 nm, respectively. The second layer of Al2O3 was deposited at 300°C by ALD for 25 cycles to avoid current leakage during electrical measurements. A 400°C post-deposition annealing for 30 min was performed. Then, the TiN layer was deposited by sputtering, followed by 350°C post-metallization annealing for 20 min. After that, the Al layer was also deposited and gate electrode was patterned. To improve the electrical contact between TiN and Al layers, a contact annealing was performed at 300°C for 10 min. Finally, an InGa back contact was formed. Ge p-MOSFETs were fabricated on n-type (100) Ge substrate with a doping concentration of 9.3 × 1015 cm-3. We used a gate-first process. An Al2O3/GeOx/Ge gate stack was fabricated by the same method as MOS capacitors as mentioned above. The source/drain (S/D) region was fabricated using B ion implantation, followed by the activation annealing (for S/D) at 300°C for 10 min. The active hole density of 4.3×1019 cm-3 was confirmed by Hall Effect measurement. 3) Summary of the r esults ITs and BTs in Al2O3/GeOx/p-Ge gate stacks were characterized using DLTS. Through evaluating the gate stacks with different GeOx thickness, the respective BTs in Al2O3, Al2O3/GeOx interface region, and GeOx were successfully detected. The D it near to mid-gap is lower in the MOS capacitors with a thicker GeOx, while the D it near to valence band is lower in the MOS capacitor with a thinner GeOx, which is probably due to the defect termination by Al oxide. The N bt in Al2O3 was 6~9×1017 cm-3, which is lower than those in GeOx (~2×1018 cm-3), and the highest N bt of ~1×1019 cm-3 was found in Al2O3/GeOx interface region. Ge p-MOSFETs with Al2O3/GeOx/p-Ge gate stacks were analyzed. It was confirmed that the ITs and the BTs near to valence band edge of Ge affect the effective mobility of Ge p-MOSFETs in high field region. Therefore, reduction of ITs and BTs near to valence band is the key to reach high-performance p-MOSFETs. In this sense, Al2O3 is a suitable dielectric material for Ge p-MOSFETs. Acknowledgement This work was partially supported by (JSPS) KAKENHI (grant numbers 17H03237 and 18KK0134) and Advanced Graduate Program in Global Strategy for Green Asia, Kyushu University. References [1] K. Hirayama, R. Ueno, Y. Iwamura, K. Yoshino, D. Wang, H. Yang, H. Nakashima, Jpn. J. Appl. Phys., 50, 04DA10-1-5 (2011). [2] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices 59, 335 (2012). [3] W.-C. Wen, K. Yamamoto, D. Wang, and H. Nakashima, J. Appl. Phys. 124, 205303 (2018). [4] W.-C. Wen, K. Yamamoto, D. Wang, and H. Nakashima, J. Appl. Phys. 127, 169901 (2020).

To meet the existing challenges associated with gate leakage current and scaling beyond 22 nm node, we report the fabrication of 8.46 nm thin ALD-ZrO2 film on silicon substrate with ~ 5.43 nm SiON as interfacial layer. Electrical characterizations such as capacitance-voltage and current-voltage measurements reveal that the post deposition annealing (PDA) of ZrO2 in NH3 ambient results in improving various performance parameters such as leakage current density (92% decrease), effective oxide thickness (~22% decrease) and dielectric constant (~32% increase) when compared to PDA in N2 ambient. The surface roughness for N2 and NH3 annealed ZrO2 samples studied using AFM were found to be 0.4949 nm and 0.1385 nm respectively; thereby showing 72% decrease in surface roughness for NH3 annealed samples. The thicknesses of the grown films were corroborated by Ellipsometry and FESEM while the structural analysis was carried out using FTIR technique. The results demonstrate that post deposition annealing of ZrO2 film in NH3 ambient at 5000 C using rapid thermal processing (RTP) gives reduced EOT (~ 1.7 nm), increased K (~30) along with the suppressed off-state leakage current density (2.1× 10-9 A/cm2) and this performance enhancement is attributed to the effective replacement of oxygen by nitrogen atom to form a thermally stable phase of ZrON. Some of the important results obtained from the present work has been exemplified in the figure below. Keywords: Post depositionannealing (PDA); Zirconium oxide (ZrO2); leakage current density (J); effective oxide thickness (EOT); high- K dielectrics. Figure 1

Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

While the issues of Fermi level pinning by interface states at the dielectric/semiconductor interface has first attracted the concern of device engineers working on high-mobility channel devices, more and more attention is going nowadays to the so-called border traps (BTs) at some distance from the interface in the gate dielectric. According to their definition [1] they are able to communicate with the inversion layer in a MOS devices with time constants on the order of 1 ms and higher. As such, they will contribute to the frequency dispersion and hysteresis in capacitance-voltage and transconductance characteristics [2] and generally dominate the low-frequency noise spectrum [3]. Historically speaking, the 1/f noise in MOSFETs has always been interpreted in terms of trapping/detrapping towards BT (Fig. 1), whereby in many cases, pure elastic tunneling was assumed, yielding a simple relationship between the trap depth z and the noise frequency f, which is based on the tunneling parameter at. The latter mainly depends on the tunneling barier Φit at the interface and the tunneling effective mass mox [3]. Based on that, several methods to derive a BT density profile from a noise spectrum have been developed; an example is given in Fig. 2 for the spectrum obtained on a Si-passivated Ge pMOSFET. It is the intension of this work to illustrate the 1/f noise method for oxide trap profiling in high-mobility channel devices with a high-k gate stack. As shown in Fig. 3 for InGaAs/InP/Al2O3 nMOSFETs, quite uniform trap density profiles have been obtained, irrespective of the architecture, i.e., buried channel with InP cap or surface channel (InP etched) or the use of surface passivation with S [4]. On the other hand, the absolute value of the trap density strongly depends on pre- and post-high-k deposition treatments. While there is quite some literature on the LF noise of Ge pMOSFETs with silicon passivation, little results have been reported on alternative gate stacks or n-channel Ge MOSFETs. As shown in Fig. 4, the noise spectrum for a Ge nMOSFET with GeOx/Al2O3/HfO2 gate stack is close to 1/f, yielding a uniform profile, according to the constant fxSI function. It corresponds with a high NBT in the range of 6×1019 cm-3 eV-1, indicating a rather poor gate stack quality [5]. Finally, the impact of inelastic tunneling in the modeling of BT profiles from 1/f noise spectra will be discussed and a possible internal depth versus frequency calibration will be outlined [6]. References [1] D.M. Fleetwood, IEEE Trans. Nucl. Sci., 39, pp. 269-271 (1992). [2] D. Lin et al., in IEDM Tech. Dig., The IEEE (New York), pp. 645-648 (2012). [3] E. Simoen, H.-C. Lin, A. Alian, G. Brammertz, C. Merckling, J. Mitard and C. Claeys, IEEE Trans. Device and Mater. Reliability, 13, pp. 444-455 (2013). [4] M. Scarpino, S. Gupta, D. Lin, A. Alian, F. Crupi, and E. Simoen, IEEE Electron Device Lett., 35, pp. 720-722 (2014). [5] W. Fang, E. Simoen, H. Arimura, J. Mitard, S. Sioncke, H. Mertens, A. Mocuta, N. Collaert, J. Luo, C. Zhao, A. Thean, and C. Claeys, submitted for publication in IEEE Trans. Electron Devices. [6] E. Simoen, J.W. Lee and C. Claeys, IEEE Trans. Electron Devices, 61, pp. 634-637 (2014). Figure 1

Concerning future high-performance applications, materials such as germanium (Ge) and III/V, have been extensively studied as alternative for the channel region instead of silicon. The high mobility makes Ge a promising channel material for both low power and high performance applications of advanced devices [1]. On the other hand, gate stack engineering is challenging in Ge devices, in view of the higher density of interface states typically observed [2]. This work analyses the influence of gate stack layers (GSL) on intrinsic voltage gain and low frequency noise in planar Ge pMOSFET devices. The GSL is composed of germanium oxide (GeOx), aluminum oxide (Al2O3) and hafnium oxide (HfO2), where both Al2O3 and HfO2film thicknesses were varied. There are also two different plasma powers under evaluation. Furthermore, the analog parameters were analyzed at high temperature, ranging from 25 to 150 °C. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are four wafers with different dielectric composition as shown in table 1. The planar device dimensions are channel width (W) of 10 µm and channel length (L) of 130, 250, 1 and 10 µm. The low frequency noise (LFN) was measured in linear operation showing no clear impact of the gate stack processing. From the normalized noise power spectral density versus drain current it is derived that the predominant flicker noise is due to trapping by border traps in the gate stack and more specifically in the GeOx layer. Representing the square root of the input-referred voltage noise spectral density (SVG 0.5) versus Id/gmyields the flat-band value (intercept) and the mobility scattering coefficient is obtained from the slope of a linear fit in Fig. 1. Among the studied wafers (figure 2), D20 (which has the thinnest Al2O3 thickness) presents the lowest value of the intrinsic voltage gain (AV) for the channel length range studied due to the degradation of the Early voltage (VEA). Furthermore, for the other wafers no significant AV variation betweem the wafers was observed. It suggests that neither the HfO2 thickness nor the plasma power presented a relevant influence on the AVvalue. Considering that the AV for all studied wafers, except D20, present the same trend at room temperature (figure 2), wafer D18 was chosen to investigate the analog basic parameter performances from 25 to 150 °C. In figure 3 is can be seen that the transconductance (gm) is strongly degraded as the temperature increases due to mobility degradation. On the other hand, the output conductance (gD) presented almost no difference with the temperature rise. Figure 4 focuses on the AV as a function of temperature. It can be seen that AVdecreases 5 dB as the temperature increases from 25 to 150 °C, due to the influence of the gm reduction. [1] J.-H. Han et al., Microelectronic Engineering, v.109, p. 266–269, 2013. [2] V.P.-H Hu et al.,TED, v.60, I. 10, p. 3596 – 3600, October, 2013. [3] S. Takagi et al., Microelectronic Engineering, v.109, p. 389–395, 2013. Figure 1

HfO2 has been one of the most important subjects of intensive research in recent years due to its outstanding material properties making it suitable for several industrial applications in the field of semiconductor electronics, especially for the high-k gate stack application. Recently, the fluorine incorporation into the HfO2 gate stack has been suggested for the sake of defect passivation of the gate stack.1-2 In this paper, we present preliminary findings on the fluorine incorporation into the HfO2 gate stack using post-gate dry cleaning technique with NF3/NH3 plasma as an engineering technique to improve the electrical property of the gate stack. For this study, HfO2 films were deposited onto p-type (100) Si wafers by atomic layer deposition (ALD) with H2O and TEMAH sources after removal of the native oxide. Post deposition annealing (PDA) was followed using rapid thermal process (RTP) at 600oC for 30sec in N2 ambient. Subsequently, the HfO2 samples were dry-cleaned using an indirect down-flow plasmasystem with NF3/NH3 gas mixture. The plasma was generated at 1 Torr with 50sccm of NF3 and 100sccm NH3 at different powers ranging from 30W to 150W for 30sec. Then, in-situ annealing was performed at 180oC for 2min in N2 to remove by-product. The chemical and physical properties of the 8nm-thick HfO2 films were examined using XPS and TEM measurements. Electrical characterizations were carried out with the MOS capacitors of the dry-cleaned HfO2 gate stacks employing TiN metal gate. Fig.1 shows that fluorine atoms were incorporated into the HfO2 films by NF3/NH3 dry cleaning. The concentration of F was slightly increased and Si-O bonding was decreased with the increase of the plasma power. Any other significant changes in HfO2 chemical composition by the dry cleaning were not observed by the XPS measurements. TEM observations (Fig.2) show that the interfacial layer was suppressed significantly at 150W compared to the sample without dry cleaning. Electrical characterizations of I-V and C-V measurements of the MOS capacitors are summarized in Fig.3. There was no significant change in flat band voltage by the dry cleaning application and its conditions of plasma power. There is a report that the fluorine incorporation led to an oxide capacitance reduction and poor electrical characteristics in HfO2 gate stack.2 Compared to the previous study on the fluorine incorporation into the HfO2 gate stack, our experimental results may indicate that the active fluorine species produced from NF3/NH3 plasma reach to the HfO2/Si interface and break the vulnerable Si-O bonds making volatile SiFx compounds selectively and the degree of the interfacial reaction is increased by the power of the NF3/NH3 plasma. In conclusion, we have found that a post-gate dry cleaning using the NF3/NH3 plasma can reduce the interfacial low-k SiOx layer without any serious degradation of the electrical properties of the HfO2 gate stack. And we suggest that the interfacial layer of the HfO2 gate stack can be controlled with process parameters of the novel NF3/NH3 dry cleaning process technique. 1. W. C. Wu, et al., J. Electrochem. Soc., 154, H561 (2007). 2. J. C. Lee, et al., Microelectron . Eng ., 88, 1417 (2011). 3. H. Ogawa, et al., Jpn. J. Appl. Phys.,41, 5349 (2002).

We report on in-situ surface preparation methods prior to atomic layer deposition (ALD) of gate dielectrics on In0.53Ga0.47As, and investigate their influence on the ability to scale the equivalent oxide thickness (EOT) and to reduce interface trap densities (Dit ). The surface treatments employed here consist of in-situ cleaning involving alternating cycles of nitrogen plasma and trimethylaluminum (TMA) pulses prior to ALD of different dielectrics (1,2). We demonstrate metal-oxide-semiconductor capacitors with HfO2 dielectrics and low Dit (in the mid 1012 cm-2 eV-1 range) that can be scaled to sub-nm EOT. Accumulation capacitances exceed 3 µF/cm2 at 1 MHz on n-type In0.53Ga0.47As. Complementary studies of interface chemistry and surface morphology using transmission electron microscopy, x-ray photoelectron spectroscopy, and secondary ion mass spectrometry as a function of surface cleaning parameters are presented and elucidate the mechanisms by which these novel surface preparation methods allow for reducing both Dit and EOT.

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling. After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1]. In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4]. Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed. [1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013). [2] S.-C. Seo, et al., VLSI, p. 36 (2011). [3] M. M. Frank et al., as discussed at SISC 2011. [4] M. M. Frank et al., as discussed at SISC 2013. .

In0.53Ga0.47As based capacitors and self-aligned transistors fabricated with HfO2/Al2O3/Si gate stacks in a gate-first process flow show promising electrical properties. With in-situ and ex-situ characterization methods, we review systematically the physical and chemical properties of the whole multilayered stack. Especially, critical instabilities which may potentially limit the achievement of sub-nanometer capacitance equivalent thickness and a low interface state density are described in detail. Finally we propose some alternative solutions to avoid the observed instability paths.

Over the last couple of scaling generations the gate stack in leading edge technology has migrated from Poly-Si and SiON to a metal gate with a bi-layer of a Hafnium based dielectric with a SiON interlayer (IL). This switch yielded immediate gains in gate leakage (Ig) and reliability, allowing a thinning of the inversion thickness (tinv) from ~20Å to less than 14Å. Even though gate length scaling and performance would drive further thinning of the dielectric stack, reliability considerations limit this. Understanding the fundamental reliability mechanisms enables mitigation with process changes and an optimization of reliability, performance, and operating voltage (Vmax). This paper will explore the main reliability mechanisms that are limiting scaling and the processes that improve reliability. Furthermore, the relationship between device level reliability and circuit reliability will be broached with ring oscillator data that shines light on the dominant reliability mechanism limiting Vmax.

One of the most critical issues for Ge/III-V MOSFETs is gate insulator formation. In this paper, we focus on viable Ge/III-V MOS gate stack technologies realizing the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). these requirements. As for Ge gate stacks, we present a ultrathin EOT Al2O3/GeOx/Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. (100) Ge pMOSFETs using GeOx/Ge MOS interfaces is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm2/Vs. As for InGaAs gate stacks, we show the impact of Al2O3 inter-layers on interface properties of HfO2/InGaAs MOS interfaces. The 1-nm-thick capacitance equivalent thickness (CET) in the HfO2/Al2O3/InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4e-2 A/cm2.

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n- and p-MOSFETs using the gate-stack formation by bilayer (SiO2/GeO2) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm2V-1s-1, respectively, despite the very thin GeO2 thickness. We will present the detailed fabrication method and device performance.

HfLaON is one of the most promising high-k dielectrics because of its higher crystallization temperature and ability to tune the work function of the metal gates from Si midgap to around 4eV, meeting the requirement of nMOSFETs. In this paper, HfLaON was prepared using reactive sputtering that alternates between Hf and HfLa targets in N2/Ar ambient, followed by a post-deposition anneal. Before deposition of HfLaON film, SiO2 interfacial layer was grown to improve the interface properties. HfLaON/SiO2 gate stack exhibited good physical and electrical characteristics, including good thermal stability, excellent interface properties, small equivalent oxide thickness and low gate-leakage current. Further studies found that the excellent characteristics of the gate stack have close relation to the grown method of SiO2 interfacial layer. In order to investigate their relationship, the different grown methods of SiO2 interfacial layer were adopted and compared in the fabrication of HfLaON/SiO2 gate stacks, such as oxidation in O3/H2O solution, rapid thermal anneal in N2 or N2/O2 mixed gas.

Interfacial oxide (IL) /high-k (HK) gate dielectric stack is widely used in 45nm logic technology and beyond nodes. Interfacial oxide, which is buffer layer between silicon substrate and HK dielectric, is a crucial factor to control Silicon/IL, IL/high-k interface charge and high-k film quality. In this work, atom layer deposition (ALD) Hf based HK film is deposited on two classes of IL by thermal oxidation (process A or B) and chemical oxidation (process C or D), respectively. XPS is used to characterize the film bonding energy, while non contact CV and spectroscopic ellipsometry (SE) are used to characterize the interface trap. The electric properties of the film stacks are characterized by C-V and I-V curves. The results reveal that interface trap of chemical oxide film has positive surface voltage and less dense SiOx, as compared with that of thermal oxide. With the same interfacial oxide thickness and HK deposition process, the chemical oxide/HK stack got 3.4A thick EOT, which is about two orders lower leakage than that of thermal oxide/HfO2. It can be explained by the fact that chemical oxide had plenty of O-H bonds, which is good for ALD Hf based HK film nucleation and growth and resulted in good film quality. However, due to the high Si/chemical oxide interfacial charge, the chemical oxide/HfO2 dielectric stack has a disadvantage of the larger C-V hysteresis.

Band alignment of TiN/HfO2/SiO2/Si stack is systematically investigated by X-ray photoelectron spectroscopy. The differences of binding energies of Si 2p core level between SiO2 and Si substrate are experimentally found to decrease with the sequence of 5 nm SiO2/Si, 4 nm HfO2/5 nm SiO2/Si and 2 nm HfO2/5 nm SiO2/Si stacks. The p-type Schottky barrier heights at TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack are experimentally estimated to increase with thicker HfO2 thickness. A physical model based on band alignment of TiN/HfO2/SiO2/Si stack is employed to successfully explain these experimental results. The flatband voltage (VFB) of TiN/HfO2/SiO2/Si stack is demonstrated by the proposed model based on band alignment of entire gate stack. The positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are also physically demonstrated by this model and attributed to interface induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

We investigate Vfb behavior of (TaC)1-xAlx gated HfO2 MOS capacitors as a function of post metal annealing (PMA) temperature. The positive Vfb shift appears in PMA temperature at above 700 °C, while the negative Vfb shift occurs at below 600 °C. At below 600 °C, the effective work function (φm,eff) of gate electrode becomes lower by increasing Al atoms with a low work function. We found that the positive Vfb shift occurs dominantly due to the φm,eff change induced by Al diffusion from gate electrode at 700 and 800 °C. At above 900 °C, Al atoms reach to the HfO2/SiO2 interface and form the AlOx layers, and results in positive Vfb shift due to the bottom interface dipole. We can divide into two components of φm,eff change of gate electrode and the bottom interface dipole due to AlOx layer as a function of PMA temperature.

We have recently reported electrical performance improvements of atomic layer deposited (ALD) HfO2 films grown by use of a cyclical deposition and annealing scheme (termed DADA) compared to a single deposition with or without a post-deposition anneal (PDA). Likewise, a process for improving leakage and reliability characteristics of ALD HfZrO by use of an interspersed room temperature ultraviolet ozone (RTUVO) treatments, referred to as multi-deposition multi-room temperature annealing (MDMA), has recently been reported. We have developed a version of this MDMA process on our 300 mm clustered tool with in situ RTUVO treatments interspersed between ALD HfO2 depositions. In this report we compare these two processes (DADA vs. MDMA) for HfO2 dielectric formation in a low temperature MOSCAP flow with in-line measurements of the HfO2 and interface layer thicknesses.

Silicon carbide has gained considerable attention for future power electronics. However, it's well known that SiC-based MOS devices have suffered from degraded electrical properties of thermally grown SiO2/SiC interfaces, such as low inversion carrier mobility and deteriorated gate oxide reliability. This paper overviews the fundamental aspects of SiC-MOS devices and indicates intrinsic obstacles connected with an accumulation of both negative fixed charges and interface defects and with a small conduction band offset of the SiO2/SiC interface which leading to the increased gate leakage current of MOS devices. To overcome these problems, we proposed using aluminum oxynitride (AlON) insulators stacked on thin SiO2 underlayers for SiC-MOS devices. Superior flatband voltage stability of AlON/SiO2/SiC gate stacks was achieved by optimizing the thickness of the underlayer and nitrogen concentration in the high-k dielectrics. Moreover, we demonstrated reduced gate leakage current and improved current drivability of SiC-MOSFETs with AlON/SiO2 gate stacks.

Although gate stack structures with high-k materials have been extensively investigated, there are some issues to be solved for the formation of high quality gate stack structures. In the present study, we employed hard x-ray photoelectron spectroscopy in operating devices. This method allows us to investigate bias dependent electronic states while keeping device structures intact. Using this method we have investigated electronic states and potential distribution in a Pt gate metal/high-k gate stack structure under device operation. We have found that potential gradient was formed at the Pt/HfO2 interface by analyzing the shifts of the core levels as a function of the applied bias voltage. Angle resolved photoelectron spectroscopy revealed that SiO2 layer was formed at the Pt/HfO2 interface. The formation of the SiO2 layer at the interface might concern the Fermi level pinning, which is observed in metal/high-k gate stack structures.

The gate dielectric breakdown (BD) reversibility in MOSFETs with ultra-thin hafnium based high-k dielectric is studied. The phenomenology is analyzed in detail and the similarities with the resistive switching phenomenon emphasized. The results show that after BD, the switch between two different conductive states in the dielectric is possible. We have demonstrated that the conduction in both states is local, which has been verified through CAFM measurements. Additionally, the injected charge to the first recovery (QR) has been proposed as a parameter to describe the BD reversibility phenomenon. The BD recovery partially restores not only the current through the gate, but also the MOSFET channel related characteristics. The electrical performance of MOSFETs after the dielectric recovery has been modeled and introduced in a circuit simulator. The simulation of several digital circuits shows that their functionality, though somehow affected, can be restored after BD recovery.

Electrical and structural properties of GaSb metal-oxide-semiconductor capacitors with in-situ deposited HfO2 gate dielectric and in-situ deposited amorphous silicon interface passivation layer are presented. Capacitance-voltage characteristics with low C-V stretch out, reduced hysteresis, lower EOT is obtained in a temperature range of 3500C-5500C post deposition annealing in forming gas. The gate leakage current of the gate stack was ≤ 1μA/cm2. p-MOSFETs fabricated on epitaxially grown strained (In)GaSb quantum channel (ε=1.6%) channels using this all in-situ high-k gate stack showed a maximum ION=23mA/mm for a 3μm gate length device

RRAM devices received increased interest lately as advanced non-volatile memory technologies in terms of low operating power, high density, better non-volatility, fast switching speed, and compatibility with conventional CMOS process. However, up to date the fundamental physical principles controlling the switching are not well understood. We have employed first-principles simulations based on density functional theory (DFT) to elucidate the effect of oxygen vacancy defects on the electronic structure of rutile TiO2 and NiO using the local density approximation with correction of on-site Coulomb interactions (LDA+U). The vacancy filament induces several defect states within the band gap, which can lead to the defect-assisted electron transport and account for on-state low resistance conduction in bulk rutile TiO2 and NiO. For CMOS devices on the other hand the reliability of the gate stack is becoming a significant challenge with the continuous scaling of transistors, due to the ultrathin oxides and defects in the gate stack. The degradation of the gate oxides has been observed under electrical stress, due to traps generated by defects, e.g. oxygen vacancies present in these materials. First principles methods based on density functional theory are used to determine the location of the defect states in the band gap when these defects are at the various interfaces of the gate stack and how they contribute to the oxide breakdown in ultrathin gate stacks.

A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst others the GeO2 thickness, the high-k material and the Post Deposition Anneal (PDA). The GeO2 thickness seems to have the largest impact, and an inverse relation between the density of interface traps Dit and border traps Nbt exists for GeO2 layers up to ~2 nm. We found that the most optimal passivation is achieved by using an (almost) oxide-free surface as this would result in the lowest Nbt. Although such a surface is characterized by a high mid-gap Dit, this can be improved by performing the correct PDA. We conclude that the most promising oxide-free surface is obtained after an H2S treatment.

Effects of a thin metal layer (W, Ta, or Mo) inserted at the interface between La2O3 high-k gate dielectric and TiN gate metal were studied. It was found that the inserted metal layer plays crucial role in determining the electrical characteristics of the TiN/Metal/La2O3/Si gate stack. Our results show that EOT can be scaled to 0.5nm and below by inserting a W layer with optimum thickness at the interface between La2O3 high-k gate dielectric and the TiN gate metal.

We have investigated the atomic layer deposition (ALD) on III-V substrates (i.e., GaAs and In0.53Ga0.47As) of Al-doped ZrO2 (Al-ZrO2) films. The aim is to benefit from TMA-based chemistry as adopted in the ALD of Al2O3 and to boost the dielectric constant of the stack. An in situ monitoring of the process with spectroscopic ellipsometry was carried out in order to address the formation of the first few monolayers of the films. The correlation with the structural and chemical characterization provides insights about the interface composition upon ALD. The electrical performances of capacitors fabricated on In0.53Ga0.47As including Al-ZrO2 as gate dielectric exhibits encouraging properties compared to those acquired for Al2O3.

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved in the gate stack with a 3nm W inserted layer after annealed at 800oC in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates in realizing high-k gate stack with EOT 0.5nm and beyond.

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.

The scalable direct LaLuO3/Ge MIS gate stack was investigated by the IL scavenging with a subsequent low temperature O2 annealing (LOA). LOA dramatically improved the interface states degraded by the GeO volatilization from the interface, with no cost of the equivalent oxide thickness (EOT). The GeO desorption was also efficiently suppressed thanks to the upper LaLuO3 film, although a reaction between LaLuO3 and GeO2 might induce electrical defects in LaLuO3/Ge system. It is strongly suggested that the appropriate selection of high-k dielectrics (LaLuO3) and scavenging process followed by LOA enable us to achieve the scalable EOT for Ge-CMOS.

The electrical properties of Pt/HfO2/In0.53Ga0.47As metal oxide semiconductor capacitors were studied as a function of post-deposition annealing conditions and analyzed using the conductance and Terman methods. Forming gas annealed gate stack exhibit an unpinned Fermi level while nitrogen annealed stacks are effectively pinned at midgap.

Control of the high-k/III-V interface by deposition of thin (~1-2 nm) interface control layers (ICLs) of Al2O3 or MgO, as part of an overall bi-layer structure with a high-k metal oxide MO2 (M = Hf|Zr), is explored. An Al2O3 or MgO ICL is deposited on unpassivated InxGa1-xAs (x = 0|0.53) substrates prior to MO2 gate oxide deposition, forming a Pd/high-k/ICL/III-V gate stack. The aim of a bi-layer structure is to enable continued device scaling using a high-k MO2 oxide while improving the high-k/III-V interface quality and interfacial band structure, with an Al2O3 or MgO ICL. Metal-oxide-semiconductor capacitor (MOSCAP) devices with an Al2O3 ICL on p-GaAs display significantly reduced leakage current density, and reduced frequency dispersion of accumulation capacitance when compared to a no-ICL device, indicating an improved high-k/III-V band structure and interface quality, respectively. Further studies on ZrO2/Al2O3/In0.53Ga0.47As devices find a reduced defect response with a post-metal forming gas anneal.

High mobility channels are currently being explored to replace the Si channel in future technology nodes. However, until now the promising bulk properties are very difficult to translate into reality due to a bad passivation of the interface between the gate stack and the substrate. In this paper we want to emphasize that gate stack passivation is the result of a complex interplay between the surface treatment and the ALD deposition. During ALD deposition on GaAs, the removal of surface oxides is observed. However, this effect does not lead to a good passivation. For Ge, the S-passivation of the interface is studied in combination with different high-κ. It is clear that the Ge/S/Al2O3 interface is superior to the Ge/S/ZrO2 interface.