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A novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique. [ABSTRACT FROM AUTHOR]

Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being. [ABSTRACT FROM AUTHOR]

Polymer-based energy storage media are widely used in electrical and electronic applications due to their high power density and excellent charge and discharge efficiency. In this paper, thermoplastic polyurethane elastomer (TPU) organic fillers were doped with polyetherimide (PEI) by the solution blending method to prepare PEI composite films with excellent energy storage properties. The effects of different TPU contents on the dielectric properties, leakage current density, and energy storage performance of the composite films were explored. The results showed that the flexible TPU fillers, which could improve the inter-chain interactions and spatial structure of PEI, reduced the chain spacing of the polymer, effectively hindered the input of charge carriers, and mitigated the electric field distortion, thus improving the insulation and dielectric properties of PEI. When the mass fraction of the added TPU elastomer reaches 0.75%, the energy storage density of the composite film reaches 11.51 J/cm3, which is 2.88 J/cm3 higher than that of the pure polyetherimide, while maintaining a high charge/discharge efficiency (87.32%), and the energy storage performance has been significantly improved under an applied electric field strength of 600 MV/m. The results show that the composite film is more efficient than the pure polyetherimide, and the energy storage performance has been significantly improved. [ABSTRACT FROM AUTHOR]

The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications. [ABSTRACT FROM AUTHOR]

The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively. [ABSTRACT FROM AUTHOR]

Concrete structures are often subjected to harsh environmental conditions, and problems such as corrosion will greatly limit their service life and safety. Stray current is one of the factors that can be easily ignored but seriously affect concrete structure. Therefore, the study of the influence of stray current on concrete structure is conducive to understanding the performance and corrosion mechanism of concrete structure, providing technical support for protecting concrete structure, and improving its service life and safety. In this experiment, the effect of stray current and chloride ion interaction on the corrosion of reinforced concrete structure was studied, and the protective effect of the coating on reinforced concrete was studied by using Zn-Ni alloy plating solution. Electrochemical workstation, silver nitrate spraying, scanning electron microscope (SEM), energy dispersive spectrometer (EDS) and direct observation were used to simulate and compare the corrosion experiments under different current intensities. By analyzing the influence of 0.05 and 0.10 A stray currents on concrete corrosion, the chloride penetration resistance of concrete structures was evaluated, and blank control experiments were set for different current intensity and different energizing time. The corrosion resistance of the steel bar coated with Zn-Ni alloy is compared with the steel bar without changing the coating under the same corrosion conditions. The results show that the corrosion tendency of concrete structures will be further increased under the action of stray current and chloride ion coupling, and the corrosion reaction will be accelerated. In addition, at the same time, the higher the simulated current, the more serious the corrosion of concrete structure; Under the same simulated current, the longer the electrification time, the worse the resistance of concrete structure to chloride ion erosion. Moreover, the corrosion resistance of the steel bar coated with Zn-Ni alloy is better. In summary, this study concludes that the coupling of stray current and chloride ion causes damage to the corrosion of concrete structures, and the current intensity and energized time are proportional to the corrosion degree, and the modified Zn-Ni alloy coated steel bar has better corrosion resistance [ABSTRACT FROM AUTHOR]

Polymer-based energy storage materials are widely utilized in the fields of electrical and electronics due to their high-power density and excellent charge-discharge efficiency. In this study, polyetherimide (PEI) composite films with outstanding energy storage properties were prepared by growing an inorganic barrier layer of boron nitride (BN) on the surface of PEI films through the in situ chemical vapor deposition (PECVD) method. The effects of BN deposition time on the dielectric properties, leakage current density, and energy storage properties of the composite films were investigated. The results reveal that the BN inorganic barrier layer, prepared by the PECVD method, demonstrates excellent interfacial compatibility with the PEI polymer matrix and forms a densely deposited layer. The BN inorganic barrier layer effectively suppresses carrier injection at the electrode, reduces the current density inside the PEI composite film, and improves the breakdown strength of the composite film. The composite film exhibits optimal performance when BN is deposited for 20 min. At an electric field strength of 660 MV/m, the energy storage density of the composite film reaches 6.08 J/cm3, which is 1.53 J/cm3 higher than that of pure PEI, while maintaining a charge-discharge efficiency of 90.43%. The findings of this study provide valuable theoretical support for the design of polymer-based energy storage materials. [ABSTRACT FROM AUTHOR]

Stray current of DC metro system will accelerate metal corrosion. Therefore, it is necessary to evaluate it. With the application of inverter feedback devices in recent years, stray current is more complex due to the DC traction power system is reversible. To evaluate stray current more accurately, the dynamic evaluation model is proposed in this paper. Firstly, traction power substation (TPS) is equivalent to controlled source, considering the diverse operating characteristics. Based on this, the dynamic evaluation model is built with multiple trains running and TPSs operation. Then, considering the nonlinear and multivalued function characteristics of TPS, the solution method is proposed. The problem of slow convergence or even non-convergence in the stray current solving process of the metro system considering reversible DC traction power system is solved. The model is validated by the field test data. Finally, the model is used to obtain dynamic stray current. Result shows that stray current level tends to be higher as traction trains and braking trains run separately and concentratedly in different areas of the line. [ABSTRACT FROM AUTHOR]

A small molecule electrolyte (SME) based on the iodide ion (FN-NDI-I) was synthesized for organic solar cells as interlayers based on fullerene and non-fullerene systems. The utilization of ITO/ZnO/SME enhances the PCE of the fullerene-based device, with an increase observed from 8.63% (pristine ZnO) to 9.06%. In the non-fullerene case, the PCE of the device based on pristine ITO/ZnO reaches 14.9%. However, due to leakage current, the performance of the device using the ITO/ZnO/SME interlayer decreases to 11.5%. When ITO/SME is employed, the device attains a PCE of 14.5%, which closely approximates the performance of the non-fullerene device based on ITO/ZnO. [ABSTRACT FROM AUTHOR]

An isolated interleaved boost converter (IIBC) based single-phase grid-interfaced photovoltaic system (SPGIPS) and its control are proposed in this article. The proposed double-stage SPGIPS consists of an IIBC and a single-phase full bridge voltage source converter (SPFBVSC). An IIBC is designed using a high-frequency transformer (HFT), two primary inductors, and two static switches with its emitter shared with photovoltaic (PV) panel ground. Shared emitter terminal reduces the gate control circuit complexity and HFT facilitates a galvanic isolation between PV panels and the utility grid, and thus it mitigates the appearance of leakage current. An IIBC reduces the ripple in PV panel current and voltages and therefore guarantees improved maximum power point operation (MPPO) of the PV system. To ensure the MPPO at PV panel terminals, a sliding mode control is used. The output DC terminals of IIBC are interfaced with self-commutated switches based SPFBVSC. To synchronize SPFBVSC with the utility grid, a new modified fourth-order generalized integrator (mFOGI) is developed. The mFOGI provides stable synchronization signal even under presence of noise, under/over shoot, or DC offset in the AC supply voltage. The proposed SPGIPS control and its performance are validated on Simulink and prototype system. [ABSTRACT FROM AUTHOR]

This article presents a new nine-level common ground (CG) type transformerless inverter (TL) structure with an integrated boost (IB) cell. The proposed structure eliminates the leakage current due to the CG structure between the input source and the grid neutral. The proposed topology is derived by combining a DC-DC boost converter and switched capacitor (SC) cell, capable of generating the nine-level output voltage over a wide range of input voltage variations. By maintaining the duty cycle of the IB converter switch at 50%, the proposed topology generates the output voltage with a boosting factor of 4. Besides, soft charging of the involved SCs and reduced inrush current is also achieved through the inductor, which ensures the permissible current stresses of the power switches. Furthermore, the voltage across the SCs is self-balanced, eliminating the need for complex independent control techniques. A 725-W laboratory prototype is built to test the performance of the proposed topology under various operating conditions, such as input and load variations. The measured efficiency of 96.9% at 725 W is obtained and is comparable with the simulation efficiency. Finally, the merits of the proposed topology are highlighted using a detailed comparison with the other recent nine-level inverter topologies. [ABSTRACT FROM AUTHOR]

This article discusses the electrical properties of an Inverse Gaussian Junctionless Gate All Around (IG-JLT-GAA) field effect transistor for identifying neutral and charged bioanalytes. In this work, the inverse Gaussian doping profile enables the potent command of gate over charge in channel in the GAA structure, resulting in improved performance attributes such as OFF current, ON current, current ratio, subthreshold slope, drain-induced barrier lowering, threshold voltage, and transconductance for the proposed biosensor. The leakage current (OFF) is 10−17 A, and the drain current (ON) is 10−6 A, with their ratio of 10−11 fetched at K = 10. This article investigates the effect of varying dielectric constants of biomolecules immobilized in cavity reflects the enhancement in biosensor sensitivity due to the immobilization of high dielectric constant protein bioanalytes. The drain-induced barrier lowering (DIBL) and subthreshold swing (SS) are 4.4 mV/V and 60.6688 mV/dec, respectively, for K = 10. The estimated threshold voltage sensitivity (SVT) for various dielectric constant biomolecules was found to be 9.7 and 110.5 mV for K = 1 and K = 10, respectively. Further, the performance of the biosensor using well-known biotin biomolecules with K = 2.63 is studied, and the result shows that the biosensor performs outstandingly in all performance attributes required for the detection of charged and neutral biomolecules. [ABSTRACT FROM AUTHOR]

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower Ioff current of 4.34 × 10−19 A, an Ion current of 4.17 × 10−06 A with an Ion/Ioff current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices. [ABSTRACT FROM AUTHOR]

The study investigates the effects of doping on the leakage current and ferroelectric properties of bismuth ferrite (BiFeO3) thin film-based heterostructures. The spin coating method has been employed to deposit thin films of BiFeO3 and heterostructures of TiO2/BiFeO3 and TiO2/BiFe0.95Mn0.05FeO3 on fluorine-doped tin oxide substrates. The ferroelectric behavior of the TiO2/BiFe0.95Mn0.05FeO3 films exhibited better ferroelectric hysteresis loop compared to the other prepared films. The ferroelectric behavior reveals the TiO2/BiFe0.95Mn0.05FeO3 heterostructure showed a significantly lower leakage current density compared to both the BiFeO3 thin film and TiO2/BiFeO3 heterostructure, and the TiO2/BiFe0.95Mn0.05FeO3 heterostructures are likely suitable for solar cell applications. FTO/TiO2/BiFe0.95Mn0.05FeO3/Au heterostructure thin films prepared by spin coating method. Structure and optical properties of TiO2/BiFe0.95Mn0.05FeO3 heterostructure thin films were investigated. TiO2/BiFe0.95Mn0.05FeO3 heterostructure thin films showed a low optical energy band gap of 2.25 eV. Enhanced ferroelectric property in TiO2 thin film composited with BiFe0.95Mn0.05FeO3 thin films. [ABSTRACT FROM AUTHOR]

In this paper, a Dickson-based RF-DC (Radio frequency power to direct current power) rectifier for energy harvesting system is designed. Dickson double-voltage structure, voltage-dividing structure and switching transistors are integrated in the system to fulfil the synchronous rectifying function, which can upgrade PCE (Power Conversion Efficiency) value, reduce the threshold voltage and decrease the leakage current, etc.. The simulation is conducted on the designed synchronous rectifier for energy harvesting of 900 MHz signal. It shows that when the input voltage $${V_{IN}} = 1V$$ V IN = 1 V , the peak output DC voltage can be stabilised at 1.8 V with the assistance of LDO (Low dropout) regulator, while the reverse leakage current is below 20 µA and the PCE value reaches 58%. The designed rectifier is assembled and tested in the paper. Both the simulation and testing results demonstrate the feasibility of the proposed synchronous rectifier. [ABSTRACT FROM AUTHOR]

This article proposes a Ti-doped Vanadium dioxide (VO2) selector device for reducing the leakage current. Here, TiO2 is formed by the Ti atoms in the VO2 film for acting like a good insulator. Hence, it reduces the integration density when the leakage current in a Cross Bar Array (CBA) is increased. In this article, the modeled Pt/Ti-doped VO2/Pt selector device is integrated with the resistive random-access memory model to demonstrate its effectiveness on sneak path current reduction. The I ON / I OFF ratio of the suggested Ti-doped VO2 selector is higher than 2 × 1 0 4. The simulated results outputs in terms of nonlinearity (∼ 28 × 1 0 4 ), current density (∼ 10 7 A cm − 2 ), and leakage current(∼0.31nA). [ABSTRACT FROM AUTHOR]

This study explores how thickness and grain size impact leakage current in RF-sputtered BFO thin films. Morphology reveals that increasing film thickness leads to larger grains, boosting grain resistivity by altering oxygen vacancies, thus reducing leakage current. Pt/Ti/BFO/FTO capacitive heterostructures are examined at varied temperatures, demonstrating a positive temperature coefficient of resistance effect. This effect stems from the closely linked interaction between multiferroic BFO and highly conductive oxide FTO, and potentially forming an electrical double layer at the Pt/Ti/BFO interface. Additionally, a dominant modified Space Charge Limited Current conduction mechanism is observed in Pt/Ti/BFO/FTO capacitive heterostructures under varying electric fields. [ABSTRACT FROM AUTHOR]

The demand of electrical energy has been increasing worldwide since the start of the 21st century. The focus on energy demand, efficiency increase, and loss control is one of the major concerns. Following the approach to control the power loss specifically in underdeveloped countries in the power distribution network where polymer insulators are installed. This research aims to study the impact of industrial pollutants by adopting accelerated aging techniques on polymer insulators installed in coastal regions. An experimental chamber is designed to model the artificial effects of the environment on polymer insulators. The polymer insulator was kept in an experimental chamber for 45 days to apply the environmental effects on it. Different environmental effects are applied in the experimental chamber including temperature, humidity, pollutants, and ultraviolet light. These environmental effects are controlled through different designated sensors that are managed by a data acquisition setup. After the accelerated aging process of polymer insulators in the experimental chamber the leakage current has been measured between healthy and contaminated polymer insulators. The healthy insulator shows 52e−9 amp leakage current while the contaminated insulator shows 149e−9 amp of leakage current after the aging process. The experimental results also concluded that the environmental impact on polymer insulators in the coastal regions is significant. Therefore, to avoid power loss due to leakage current it is recommended to have periodic cleaning of the polymer insulators specifically in the coastal regions that are installed in the power distribution network. This will help to reduce the power loss due to contamination in environment. [ABSTRACT FROM AUTHOR]

Calculating power and delay in VLSI circuits are two main challenges in designing CMOS VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor domino logic for power and delay reduction. The lector technique uses two leakage-controlled transistors, PMOS and NMOS. The gate terminal of PMOS is connected to the source of NMOS, and the gate terminal of NMOS is connected to the source of PMOS. NMOS transistor N5 is used in the proposed circuit, driven by a dynamic node, which helps to reduce the power. This manuscript uses the proposed technique to design a buffer, two-input – AND gate, OR gate, and XOR gate circuits. The logic gates are simulated on the gpdk 45 nm cadence virtuoso software tool. The simulation result shows that the proposed domino logic circuit significantly reduces power, delay, energy, and leakage current. Monte Carlo analysis is performed to study the mean and standard deviation of the proposed circuit with 1000 samples. [ABSTRACT FROM AUTHOR]

A fully soluble and photo-crosslinkable gate dielectric (6 F-SPI-Cinnamoyl: 6 F-SPI-CM) was synthesized. First, hydroxyl group substituted polyimide (6 F-SPI-Hydroxyl: 6 F-SPI-OH) polymer was prepared using monomers, 5-(2,5-dioxytetrahydrofuryl)-3-methyl-3-cyclohexene-1,2-dicarboxylic anhydride (DOCDA) and 4,4'-(perfluoropropane-2,2-diyl)dianiline (6FHAB) through polycondensation reaction. And, then 6 F-SPI-OH was further reacted with cinnamoyl chloride to prepare a photo-crosslinkable 6 F-SPI-CM. The thin film of photo-crosslinked 6 F-SPI-CM (C-6F-SPI-CM) showed the extremely low leakage current density of <1.0 x10−11 A/cm2. In addition, 6 F-SPI-CM was easily patterned by selective UV-light exposure. A flexible pentacene thin-film transistor (TFT) on polyethersulfone (PES) substrate with photo-crosslinked 6 F-SPI-CM as a gate dielectric showed a field effect mobility of 0.11 cm2/Vs with no hysteresis behavior. [ABSTRACT FROM AUTHOR]

Mn doped CaZrO3-NaNbO3 solid solutions were prepared by a conventional solid reaction method. Mn doping can reduce leakage current significantly and the optimized content is 3% (mole). For Mn doped CaZrO3-NaNbO3 solid solutions, the antiferroelectricity is stabilized when the content of CaZrO3 is less than 6% (mole) When the content of CaZrO3 is higher than 6% (mole), the polarization decreases, the polarization-electric hysteresis loop becomes slim, and the antiferroelectric-antiferroelectric related dielectric peak disappears, indicating antiferroelectric ordering is destroyed. [ABSTRACT FROM AUTHOR]

The current generation aims for Low power electronic gadgets like cell phones, PDAs, etc. This urged demand is met through adopting low power reduction techniques. These gadgets also demand the presence of cache memories, which are fabricated via Static Random Access Memory (SRAM) Cells. Now the challenge is in designing low leakage SRAM cells by adopting power reduction techniques. The proposed work of 7T based Volatile and Non-Volatile SRAM cell is carried through adopting efficient low power reduction technique referred to as Improved Self Controllable Voltage Level (I-SVL). Proposed 7T SRAM cell is based on Improved Self Controllable Voltage Level (I-SVL) technique which controls the supply voltage in Idle and Non Idle mode of SRAM cell. Also Upper-ISVL and Lower-ISVL supplies the Vdd and Vss as per the requirement there by controlling the leakage power. The proposed I-SVL based 7T Volatile and Non-Volatile is designed and simulated using Cadence Virtuoso spectre tool by using CMOS technology with gpdk 45nm. Proposed work carried is efficient in terms of sub threshold and total leakage currents in comparison with the earlier work. The obtained sub threshold and total leakage current of the proposed volatile 7T SRAM cell based on the I-SVL shows improvements in lower values with existing work by 15% and 32%. Also proposed Non-volatile based I-SVL 7T SRAM cell resulted in lesser sub threshold and total leakage current by an amount of 97% and 93% in comparison with the earlier work. The gate leakage current of proposed Non-volatile 7T SRAM cell resulted in 57% lower value in comparison with the earlier work. [ABSTRACT FROM AUTHOR]

A proposed core–shell gate all-around junctionless field-effect transistor (CS GAA JLFET) is studied using extensive simulations. An oppositely doped core is sandwiched between the shells to achieve lesser leakage current due to an increase in tunneling width at the channel/drain interface and an increase in source/channel barrier height. The core doping is initially optimized, followed by the variation of channel length. Different gate dielectric is studied and investigated. The best performance parameters are obtained for channel length 20 nm with k = 15. The OFF current of ∼10−16 A/µm, ON current of ∼10−4 A/µm, ON/OFF current ratio ∼1012, subthreshold slope of 60.61 mV/decade, and drain-induced barrier lowering of 8.5 mV/V are obtained. The study is done using contour plots, surface potential, and central potential to better understand the proposed CS GAA JLFET device. The better control over the carriers in GAA configuration and the advantage of core–shell architecture helps achieve significant improvement in performance parameters. [ABSTRACT FROM AUTHOR]

Lead-free multiferroic composite ceramics of 0.7BaTiO3-0.3Ni0.7Zn0.3Fe2O4 (BT-NZF) were prepared by the solid-state combustion technique. The BT and NZF powders were calcined in the range of 1100 to 1200 °C for 4 h and 900 to 1100 °C for 2 h, respectively. Afterward, BT-NZF composite ceramics were sintered between 1100 and 1250 °C for 4 h. The effect of the firing temperature on the phase formation, microstructure, electrical, and magnetic properties of BT-NZF composite ceramics was investigated. X-ray diffraction of BT and NFZ powders showed the highest purity phase were prepared the calcination temperatures of 1100 and 1050 °C, respectively. The BT-NZF composite ceramics exhibited coexisting tetragonal perovskite and cubic spinel phases. The maximum density of 5.85 g/cm3 was obtained when sintering the composite ceramics at 1125 °C. The dielectric constant at room temperature increased with increased sintering temperature. The hysteresis loops showed leakage current in all samples. Ferromagnetic properties showed the highest Ms ∼ 24.56 emu/g measured under a magnetic field of 10,000 Oe from the sample sintered at 1150 °C. [ABSTRACT FROM AUTHOR]

Transformerless power converters are trending in automotive sector as the demand for onboard chargers rises. The high efficiency and leakage current mitigating property of highly efficient and reliable inverter concept (HERIC) converter make it an excellent choice among transformerless topologies. By using appropriate modulation technique, the HERIC converter can transmit bidirectional power. This article presents design of sliding mode controller (SMC) for bidirectional HERIC converter to enhance the tracking performance. The SMC parameters are selected utilizing Harris hawks optimization (HHO) algorithm. During vehicle-to-grid (V2G) operation, sliding mode controller is developed for reactive power regulation of the grid connected HERIC converter and for grid-to-vehicle (G2V) operation, the converter is operated with very low voltage ripples in the DC side. The stability analysis is done by considering model uncertainties to guarantee sinusoidal grid current, low THD, and unity power factor even in the presence of grid disturbances and parametric variations. The Typhoon Hardware in the Loop (HIL) 402 device is used to execute the real-time testing. The results confirmed the efficacy and robustness of the designed controller under different scenarios for both modes of operation. [ABSTRACT FROM AUTHOR]

Rare-earth orthoferrites RFeO3 are important functional materials and are very promising due to their unique electrical properties. Amongst various orthoferrites systems, SmFeO3 is emerging as potential system having various multifunctional behaviour with structural modifications by doping or microstructural effect. In the present attempt, we explore SmFeO3 system and modify it by partially replacing Sm by Ce. We have synthesised pure SmFeO3 based system through Sol-Gel one of the combustion method. X-ray diffraction study confirms the formation of pure and highly crystalline single phase without any impurity. To get more clarity about structural features, Rietveld Refinement has been carried out using by Full-Proof Software which confirms the formation of orthorhombic structure with Pbnm space group. Dielectric study confirms that Ce doping in SmFeO3 modify dielectric constant from one order to two order. The response of polarisation with respect to applied electric field has been studied by P-E loop tracer. The remanent polarisation (pr) enhanced from 0.040 to 0.050 µC/cm2 for x = 0.10 after applied maximum electric field. An improvement in the ferroelectric loop was obtained due to the suppression of oxygen vacancies and the reduced leakage current density (10 − 8 A/cm2 at 20 kV/cm). [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

With technology scaling and to meet the desired design for low power and high-speed circuit, innovative design is being studied. The simulation study of vertical Quad gate oxide stacked junction-less Nano-sheet being a most promising device structure within a Nano scale regime, with the use of oxide, work function, and channel engineering for single, double, and triple fins Nano-sheet have been successfully demonstrated and implemented. From the reference model of tri-gate junction-less (TGJLFET) the structure is modified with a new design approach the with same design parameters. The First approach is by adding the fourth gate to the TGJLFET structure forms a new structure of quad gate junction-less Nano-sheet. The second approach is by extending the fins and adding source and drain pads with an underlap structure. The Third approach is adding the fin stacking and the fourth approach is adding gate oxide stacking to three fins vertical quad gate oxide stacking junction-less Nano-sheet (QGOSJLNS), all the approaches are simulated using a 3D visual TCAD environment. The improvement in the performance of the Nano-sheet device is denoted after comparing it with TGJLFET. Investigated performance includes leakage current, sub-threshold swing (SS), Drain induced barrier lowering (DIBL), threshold voltage (Vth), transconductance (Gm), the potential at core and surface fins of the Nano-sheet. Further, DC analysis of 3D QGOSJLNS an inverter is simulated and studied using 3D V-TCAD environment from Cogenda Pvt Ltd. [ABSTRACT FROM AUTHOR]

In this work, the impact of high-K and gate-to-drain spacing (Lgd) in InAs-based double-gate metal oxide semiconductor high-electron-mobility transistor (DG-MOS-HEMT) is analyzed for low-loss and high-frequency applications using 2D Sentaurus TCAD simulation. In this device, HfO2 is utilized as the dielectric material and that offers a reduced leakage current. The device with small gate-to-drain spacing (Lgd) gives an exquisite device operation in enhancement mode (E-mode) operation with a positive threshold voltage (VT) of 0.1223 V, the high drain current (Ids,sat) of 1.38 mA/µm, transconductance (gm) of 1.59 ms/µm, and sub-threshold slope (SS) of 75 mV/dec is achieved. These superior properties in this device show a high cut-off frequency (fT) of 547 GHz and the maximum oscillation frequency of (fmax) of 740 GHz. The numerical device simulation results show that DG-MOS-HEMT with HfO2 as dielectric offers a remarkable control of leakage current and makes it suitable for low-power, low-noise, and high-frequency applications. [ABSTRACT FROM AUTHOR]

Perovskite phase ferroelectric thin films Bi4-xSbxTi3O12 (Sb(x)-BIT) and pyrochlore crystal phase thin films Bi2-ySbyTi2O7 (Sb(y)-BTO) with different Sb concentration have been fabricated on Pt(111)/Ti/SiO2/Si(100) substrates through sol-gel method respectively. Test results show that the doping Sb can significantly reduce the leakage current of films. Especially when x = 0.04, y = 0.3 the leakage current characteristics of Sb(0.04)-BIT and Sb(0.3)-BTO both to achieve the optimal, and the ferroelectric properties Sb(0.04)-BIT are also improved. By the same means, constructed the Sb(0.04)-BIT/Sb(0.3)-BTO system with Sb(0.3)-BTO as buffer layer and Sb(0.04)-BIT as ferroelectric layer. The properties of BIT ferroelectric thin films are improved by the doping of Sb element and the addition of buffer layer. This is mainly reflected in that compared to pristine BIT the leakage current of Sb(0.04)-BIT/Sb(0.3)-BTO system decreases rapidly from the initial 8.8 × 10−4 A/cm2 to the current 7.2 × 10−10 A/cm2, the residual polarization 2Pr of the system increases sharply from 9.5 to 70.8 µC/cm2 and fatigue endurance up to more than 1010 switching cycles. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of an isolated high step-up Y-source DC/DC converter for photovoltaic systems. At high switching frequencies, the conventional impedance source converter (ISC) experiences higher switching losses. To mitigate this, a high gain soft-switched frequency-modulated Y-source DC/DC converter is proposed. Here, soft switching is implemented on the Y-source impedance converter by creating quasi-resonance during a shoot-through instant. Thus, quasi-resonance occurs by an LC resonant tank, and it is formed using a resonant capacitor and leakage inductance of a transformer. It ensures that all the active switches are turned off with zero current switching (ZCS) and the voltage stress on each switch is much lower than the output voltage with lower turn-off voltage spikes. Thus, it eliminates the need for a snubber circuit. The output voltage is regulated by frequency modulation with the ON period of all four active switches kept constant. The converter can also deliver a continuous input current (CIC) and high voltage gain with a small shoot-through duty ratio (d S T ). The galvanic isolation of the converter helps to eliminate the leakage current issues and safety hazards faced by the non-isolated counterparts. The proposed topology has all the inherent characteristics of a typical impedance source DC/DC converter with higher conversion efficiency over a wide range of output loads. The proposed converter achieves 96.46% of full load efficiency. Finally, a 200W prototype is built and tested in the laboratory to verify the converter design and performance. [ABSTRACT FROM AUTHOR]

In electrochemical machining (ECM), the material in the workpiece is removed in a localized electrochemical dissolution process, and metal oxides are formed as by-products. In this study, the electrolyte is present only above the workpiece, and the electrolyte thickness is maintained as 2 mm to limit the variation in radial current flow from the micro-tool. In this research work, experiments were conducted using two electrolytes, namely, NaCl and NaNO3, to machine through holes on a 1-mm-thick SS 304 workpiece, using a hollow tool of outer diameter 261 µm. The pressurized electrolyte was sent through the hollow tool to remove the metal oxides formed in the machining zone. A fixture was designed and used for the identification of through holes. Two sets of L16 orthogonal array (OA) were applied; the factors selected for this experimental study were voltage, electrolyte concentration, electrolyte temperature, and pressure. The output responses considered are radial overcut, taper angle and material removal rate (MRR). Analysis of variance (ANOVA) and Taguchi techniques were utilized in the analysis of results. The results showed voltage and concentration of the electrolyte as the major influencing factors, while the influence of stray current was controlled using NaNO3. [ABSTRACT FROM AUTHOR]

BiFeO3 thin films were deposited onto single crystalline Si (100) substrate using Pulsed Laser Deposition technique. The effect of different oxygen partial pressure on the BiFeO3 film growth, structural and transport properties has been investigated. Structural characterization shows that film growth under lower partial pressure exhibits a minor impurity phase which gets suppressed under higher oxygen partial pressure (OP2). The effect of OP2 during the deposition on the leakage current and the role of oxygen vacancies have been understood in the context of various charge transport mechanism. RBS study confirms the presence of oxygen content in the film studied which are responsible for the modification in the Electrical behavior of BFO/Si thin film devices. [ABSTRACT FROM AUTHOR]

Leakage current properties of pure and Mo-doped BiFeO' (BFO) thin films have been studied in order to identify the cause of high leakage currents. Interestingly, it was observed that the leakage current density reduced by more than two orders of magnitude upon Mo doping at Fe site of BFO. According to J-V characteristics, the leakage current density decreased from 1.101 × 10-6 A/cm2 to 9.4 × 10-8 A/cm2 at an applied bias voltage of 2.75 V with Mo substitution. These findings suggest that oxygen vacancies, rather than Fe2+ ions, are the primary cause of BFO's high conductivity. [ABSTRACT FROM AUTHOR]

In energy harnessing applications there are instances where energy should be transferred from a low-power, low-leakage backup battery to a temporary power delivery output capacitor. The high power delivery feature of the storage capacitor usually comes at the price of higher leakage current and thus it cannot replace the long-term energy storage backup battery. This paper presents a CMOS capacitor charger circuit which connects a long term low power battery to a short-burst high power delivery capacitor. The proposed circuit uses a switching output stage with an external inductor to reduce the dissipation during the capacitor charge-up cycle. A sigma-delta modulation approach is used to control the power switches. Under low power transfer scenarios which perform transfer in a longer duration, the proposed approach shows better performance compared with previously presented techniques. It is shown that under different transfer durations the control section only consumes 970nWs. The efficiency of the proposed circuit is more than 90% for average input powers in the 0.7 mW to 2 mW range. [ABSTRACT FROM AUTHOR]

A novel reconfigurable RF-to-DC power converter is proposed for wireless energy harvesting. The proposed RF rectifier employs low-threshold transistors with cross-coupled configuration to enhance the flow of the forward current to the load at low input RF power and adaptive stacking diodes to reduce the leakage current by lowering the driving voltage of the rectifying PMOS transistors at high input RF power. The proposed rectifier utilises the body biasing technique to modulate the threshold voltage and minimises the leakage current of the feedback diodes. The proposed novel techniques improve efficiency and extend the dynamic range. The prototype is implemented in a 65 nm CMOS technology and occupies an active area of 0.0148 mm2. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 76% with a load of a 100-KΩ load at the industrial, scientific, and medical band 433 MHz, and the achieved sensitivity of the rectifier is −18.5 dBm for 1 V DC output voltage. The proposed rectifier offers PCE at −35 dBm of 45.6%, which is the best low-power performance. Compared to the state-of-the-art rectifiers, the proposed design achieves an excellent wide-dynamic range of 17.5 dB, which is ten times better than the conventional cross-coupled rectifier. [ABSTRACT FROM AUTHOR]

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ Vgs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ Vgs =−1 V for LS = LD = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ Vgs = 0 V) and tunneling current (2 × 10−8 A @ Vgs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ Vgs = −1 V), moderate lattice temperature (326) and better Ion/Ioff ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect. [ABSTRACT FROM AUTHOR]

Industrial sectors rely on electrical inverter drives to power their various load segments. Because the majority of their load is nonlinear, their drive system behaviour is unpredictable. Manufacturers continue to invest much in research and development to ensure that the device can resist any disturbances caused by the power system or load-side changes. The literature in this field of study depicts numerous effects caused by harmonics, a sudden inrush of currents, power interruption in all phases, leakage current effects and torque control of the system, among others. These and numerous other effects have been discovered as a result of research, and the inverter drive has been enhanced to a more advanced device than its earlier version. Despite these measures, inverter drives continue to operate poorly and frequently fail throughout the warranty term. This failure analysis is used as the basis for this research work, which presents a method for forecasting faulty sections using power system parameters. The said parameters were obtained by field-test dataset analysis in industrial premises. The prediction parameter is established by the examination of field research test data. The same data are used to train the machine learning system for future pre-emptive action. When exposed to live data feeds, the algorithm may forecast the future and suggest the same. Thus, when comparing the current status of the device to the planned study effort, the latter provides an advantage in terms of safeguarding the device and avoiding a brief period of total shutdown. As a result, the machine learning model was trained using the tested dataset and employed for prediction purposes; as a result, it provides a more accurate prediction, which benefits end consumers rather than improving the power system's grid-side difficulties. [ABSTRACT FROM AUTHOR]

In view of the shortcomings of the traditional electromagnetic current transformer in the detection of pulsating DC and smooth DC, a leakage current detection method based on fluxgate magnetic field sensor is proposed in this paper. The leakage current is detected by the size of the magnetic field induced by the DRV425 fluxgate magnetic field sensor. At the same time, the magnetic core is designed to improve the sensitivity of the magnetic field sensor. Finally, the FFT is run in STM32 to identify the waveform of the leakage current from the frequency domain, and the tripping of the action mechanism is realized under different leakage current waveforms and different leakage current thresholds. The experimental results show that the method can effectively detect and identify the leakage current waveform, and can effectively improve the current status of the leakage protector. [ABSTRACT FROM AUTHOR]

The main application of the mobile geo-electrical measurement is the detection of the presence and determining the location of leakage in sewer systems. To do so, this method relies on the increase in the measured electrical current between an electrode inside and an electrode outside the sewer system. To use this technique for the quantification of leakages further assumptions on the measured current are required. In this study, a model to simulate the geo-electrical measurement system is developed. Laboratory experiments are conducted to investigate the influence and contribution of the model components on the measured current and the validity of the assumptions. The experimental results demonstrate that multiple components significantly contribute to the measured current apart from the leakage in the pipe. As a consequence, the properties of the leakage in the pipe are likely to be significantly under- or overestimated in most measuring systems currently applied in practice. [ABSTRACT FROM AUTHOR]

In this report, the detailed studies of structural, dielectric, impedance, conductivity, electrical modulus, and leakage-current characteristics of the oxide method synthesized -double perovskite Dy2CoMnO6 ceramic have been provided. From the Rietveld analysis, the structure of the compound is found to be monoclinic. The frequency-temperature dependence of the dielectric properties is discussed by using the Maxwell-Wagner model. The analysis of the Nyquist plot suggests the occurrence of grain and grain boundary effect in the compound. The frequency response of conductivity analysis was explained by Jonscher's power law. The conduction mechanism follows the space charge limited conduction (SCLC) process which is obtained from leakage current analysis. [ABSTRACT FROM AUTHOR]

The Rietveld analysis of X-ray diffraction spectrum confirms the tetragonal (P4bm) symmetry of the manganese doped Bi0.5K0.5TiO3 (BKT) compound synthesized by the solid-state reaction route. The dielectric analysis of doping of 5% manganese (Mn) ions at the Ti-sites in the host BKT is analyzed on the basis of the Maxwell–Wagner mechanism in the material. The P-E loop indicates the ferroelectric nature of the compound. Correlated barrier hopping is found to be the dominant conduction mechanism in the compound. The leakage current confirms the negative temperature coefficient of resistance nature of the compound and the Ohmic electrode contact. The substitutions of smaller Mn ion with multiple valencies at the Ti site enhances the dielectric constant substantially, decreases the loss tangent, and lower the leakage current. These features are applicable for energy storage devices, memory devices, high-temperature sensors, and high-temperature capacitors. [ABSTRACT FROM AUTHOR]

In this report, the detailed studies of structural, dielectric, impedance, conductivity, electrical modulus, and leakage-current characteristics of the oxide method synthesized -double perovskite Dy2CoMnO6 ceramic have been provided. From the Rietveld analysis, the structure of the compound is found to be monoclinic. The frequency-temperature dependence of the dielectric properties is discussed by using the Maxwell-Wagner model. The analysis of the Nyquist plot suggests the occurrence of grain and grain boundary effect in the compound. The frequency response of conductivity analysis was explained by Jonscher's power law. The conduction mechanism follows the space charge limited conduction (SCLC) process which is obtained from leakage current analysis. [ABSTRACT FROM AUTHOR]

The effects of Cs+ substitution and direct doping in (K0.5Na0.5)(Nb0.7Ta0.3)O3 (KNNT) ceramics, on the crystal structure, microstructure and electrical properties were investigated. Both the KNNT with Cs+ substitution (K0.5-xCsxNNT) and addition (KNNT-xCs) (x = 0, 0.01, 0.02, 0.03 and 0.04 mol%) were synthesized by the solid-state combustion technique using glycine as fuel. All samples were sintered at 1130–1150 °C for 4 h. The x-ray diffraction (XRD) analysis for the ceramics revealed the presence of orthorhombic (O) and tetragonal (T) phases in all samples. Increasing both the Cs+ substitution and doping amounts, enhanced the content of orthorhombic phase, as verified by the Rietveld refinement technique. It was found that Cs+ doping, either substitutional or additional, strongly decreased their density, dielectric and ferroelectric properties. The undoped KNNT ceramic exhibited well-saturated P-E hysteresis loop. With Cs+ doping, the samples became unsaturated and a leakage current was produced. The KNNT-xCs ceramics demonstrated higher density and dielectric properties than the K0.5-xCsxNNT ceramics. [ABSTRACT FROM AUTHOR]

ATLAS TCAD-based comparative investigation (mainly breakdown voltage, cut-off frequency and leakage current) has been presented in this work for different length of gate field plate and source field plate. 127 V of breakdown voltage has been achieved at 0.25 µm gate length having 0.8 µm gate field plate length and 1 µm source field plate length. By amalgamating source field plate, maximum cut-off frequency of 38 GHz was achieved at 0.25 µm channel length. Passivation layer permittivity and barrier thickness has also been used to optimize the device performance. The improvement in breakdown voltage is less prominent than the deterioration in cut-off frequency with the enhancement in passivation layer permittivity. Leakage current of source field plate HEMT has also been studied for different passivation layer permittivity. [ABSTRACT FROM AUTHOR]

Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leakage through gate oxide reduces memory retention time and reliability of gate dielectric. Knowledge of conduction mechanisms of gate leakage current is essential for the optimization of process conditions to reduce leakage current and determination of suitable operating voltage of flash memory devices. In this work, conduction mechanisms contributing to gate leakage current in SiC MIS capacitors with different gate dielectric are extracted for the entire range of the gate electric field. Space charge limited (SCL) conduction mechanisms either Ohm's law or trap filled limit process or combination of both are observed to be dominant at the low electric field. Hopping conduction found to be dominating the leakage current when the slope of leakage current changes from the lower value to a higher value. The sequence of mechanisms contributing to gate leakage current from low electric field to high electric field is found to be same in SiO2 annealed in O2 and N2, SiON and Al2O3/SiON stack. The trap filled limit process, trap-assisted tunneling and FN tunneling are dominating the gate leakage current at low, mid and high electric field respectively in all the investigated MIS capacitors. [ABSTRACT FROM AUTHOR]

The battery-driven portable systems are the lifeline of the modern era. Very large-scale integration (VLSI) designers are continuously working to enhance the performance of the portable systems. The small size, fast response and high battery back-up are the prime factors for the portable systems. Scaling down of the metal oxide semiconductor field effect transistor (MOSFET) dimensions is mandatory to design the low size systems. The power supply and the threshold voltage must be scaled-down with each new technology node in order to maintain the performance of the devices. The scaling down of the threshold voltage of the device produces leakage current. The amount of the leakage current is large at integration level and harms the characteristics of the systems. Therefore, leakage current mitigation is needed especially at lower technology nodes to boost the battery back-up of the portable systems. Number of leakage reduction techniques are available at different abstraction levels. In this review paper, a systematic flow of the low power VLSI field is explored with the target of the different existing circuit level leakage reduction techniques. NAND3 gate is designed and simulated at 16 nm technology node by using the different existing leakage reduction techniques for the comparison purpose. [ABSTRACT FROM AUTHOR]

With technology scaling, innovative approaches in the device design are increasingly being explored. Improving device design is one of the focus areas for meeting the demand for low power high-speed circuit design. FinFET being the most promising device structure within the nanoscale regime, different structure variants of FinFET have been proposed and successfully implemented. In this paper, bulk FinFET device design is modified with a new design approach. Two different Si bulk trapezoidal FinFET devices, one with stacked gate and another with extended stacked gate are implemented using the 3D TCAD tool. The improvement in the performance metrics is denoted after comparing it with a simple trapezoidal Bulk FinFET device. Investigated performance metrics include subthreshold slope, Drain-Induced Barrier Lowering, Leakage Current, transconductance generation factor and threshold voltage and internal capacitance across Gate-Substrate, Gate-Drain and Gate -Source terminals of the device. [ABSTRACT FROM AUTHOR]

Ferroelectric Bi3.25Nd0.75Ti3O12 (BNT), BiFeO3 (BFO) and Bi3.25Nd0.75Ti3O12-BiFeO3 (BNT-BFO) composite thin films were deposited onto Pt/Ti/SiO2/Si(100) substrates using the sol–gel process. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to identify the crystal structure, the surface and cross-section morphology of the deposited ferroelectric thin films. Structure evolution and ferroelectric properties of the as prepared thin films annealed under 750 °C were studied in detail. It is found that the leakage current of the entire thin film was effectively reduced by preparing BNT and BFO composite thin films with appropriate thickness ratios to achieve their full advantages, and consequently, significantly improve the ferroelectric properties of the composite thin films. [ABSTRACT FROM AUTHOR]

K0.5Na0.5NbO3 ceramic was synthesized at low calcination temperature by sol-gel route. Structural properties of ceramic were investigated by X-ray diffractometer, FESEM and FTIR spectrometer. Electro-optical properties of ceramic were investigated by UV-Vis and PL spectrometer. Dielectric nature of ceramic was studied at different frequencies and temperatures which disclosed that ceramic has maximum dielectric permittivity at 500 KHz. AC conductivity analysis shows negative temperature coefficient of resistance behavior. Leakage current was studied up to 180 V which shows low value of leakage current at room temperature. Ferroelectric nature was analyzed at different electric fields (5–20 kVcm−1) at 50 Hz. [ABSTRACT FROM AUTHOR]