An Improved Performance of Gate All-Around Junctionless FET Using Core–Shell Architecture.

A proposed core–shell gate all-around junctionless field-effect transistor (CS GAA JLFET) is studied using extensive simulations. An oppositely doped core is sandwiched between the shells to achieve lesser leakage current due to an increase in tunneling width at the channel/drain interface and an increase in source/channel barrier height. The core doping is initially optimized, followed by the variation of channel length. Different gate dielectric is studied and investigated. The best performance parameters are obtained for channel length 20 nm with k = 15. The OFF current of ∼10−16 A/µm, ON current of ∼10−4 A/µm, ON/OFF current ratio ∼1012, subthreshold slope of 60.61 mV/decade, and drain-induced barrier lowering of 8.5 mV/V are obtained. The study is done using contour plots, surface potential, and central potential to better understand the proposed CS GAA JLFET device. The better control over the carriers in GAA configuration and the advantage of core–shell architecture helps achieve significant improvement in performance parameters. [ABSTRACT FROM AUTHOR]