A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime.

The battery-driven portable systems are the lifeline of the modern era. Very large-scale integration (VLSI) designers are continuously working to enhance the performance of the portable systems. The small size, fast response and high battery back-up are the prime factors for the portable systems. Scaling down of the metal oxide semiconductor field effect transistor (MOSFET) dimensions is mandatory to design the low size systems. The power supply and the threshold voltage must be scaled-down with each new technology node in order to maintain the performance of the devices. The scaling down of the threshold voltage of the device produces leakage current. The amount of the leakage current is large at integration level and harms the characteristics of the systems. Therefore, leakage current mitigation is needed especially at lower technology nodes to boost the battery back-up of the portable systems. Number of leakage reduction techniques are available at different abstraction levels. In this review paper, a systematic flow of the low power VLSI field is explored with the target of the different existing circuit level leakage reduction techniques. NAND3 gate is designed and simulated at 16 nm technology node by using the different existing leakage reduction techniques for the comparison purpose. [ABSTRACT FROM AUTHOR]