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A new structure for improving the performance of recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The improvement has been achieved using two current recycling stages. The first current recycled stage acts as an adaptive biasing current source for the second stage. Compared to the RFC OTA, the proposed OTA shows a significant improvement in slew rate (SR), gain-band-width (GBW), and DC gain. Simulation results in 0.18 µm standard CMOS technology exhibit that the proposed OTA achieves an about three times improvement in SR, 12.4 dB DC gain enhancement, and approximately two times increase in gain bandwidth compared to the RFC OTA. The proposed OTA consumes 433 µW @1.8 V which makes it appropriate for low-power applications.

The active magnetic bearing technology is widely utilized for large turbomachinery. This research paper starts with a systematic review on the design and optimization of active magnetic bearing, by using bibliometric analysis. The salient research findings are summarized using the network analysis feature therein. Similarly, using cluster analysis, the major outcomes of research pursuits pertaining to active magnetic bearing (AMB) systems are also mapped. In this context, three performance parameters are usually evaluated, i.e., force slew rate, overall bearing volume, and total losses (copper and iron losses). In this study, optimization is carried out for a rotational speed of 22,000 rpm using multi-objective genetic algorithm so as to minimize the overall bearing volume, maximize the force slew rate, and also minimize the total losses. The optimum values of the design parameters related to the AMB geometry and electromagnetic actuator are determined.

A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

A high-gain two-stage class A–AB operational amplifier (Op-Amp) is presented. A boosted recycling folded cascode with more than four cascode transistors compared to the conventional structure is used in the first stage of the proposed Op-Amp. The AB class output stage is constructed using a quasi-floating-gate MOSFET and a bootstrap capacitor. Indirect feedback compensation is utilized, leading to smaller compensation capacitors and, therefore, higher slew rate (SR) and bandwidth. The proposed circuit is simulated by using a 180-nm 1.8-V CMOS process standard technology. Simulation results with a 50-pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 121.6 dB, 45.3 MHz, 66.2 V/μS, 29.7 nS, and 65.6°, respectively. The PM and SR reduce to 65.6° and 51.9 V/μS, respectively, when driving a 100-pF capacitance load. The proposed Op-Amp consumes 1.59 mW @ 1.8 V, which makes it a high-current-efficiency two-stage amplifier.

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm $$\times$$ 59 μm).

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

This paper proposes a modified version of recycling folded cascode amplifier. A comparative study, modelling and analysis of the proposed design along with conventional folded cascode and recycling folded cascode have been presented in this work. The design is intended for use as a preamplifier in an epileptic neurostimulator circuit, which ensures high gain, low noise low power trade-off and smaller bandwidth (lower than 500 Hz) as the primary criteria. An adaptive biasing technique is implemented to enhance the key performance parameters like intrinsic gain, slew rate and gain-bandwidth product. Also, the proposed device works in weak inversion region to ensure ultra-low power consumption. There are various neurostimulators categorized as Deep Brain Stimulation and Vagus Nerve Stimulation reported in the literature so far. However the proposed design considers high-frequency oscillations (HFO) as the biomarker of focal epileptic seizures, owing to its occurrence in higher frequencies, thereby asserting a bandwidth less than 500 Hz. The simulations for the designed structures are carried out in Cadence Virtuoso using SCL 180 nm technology, with an operating voltage 0.6 V. The simulation results illustrate the improvement in several parameters: intrinsic DC gain by 14 dB with a consumed power of 1.782 µW, and an input-referred noise of 10.97 µV/√Hz @1 Hz, establishing that the design works with ultra-low power consumption. Analytical modelling and comparative analysis of the proposed as well as conventional designs have been performed. Additionally comparison has been drawn between the pre-layout and post layout simulation results which shows close matching between each other. Furthermore, Monte Carlo analysis has been performed on the proposed design to validate its consistency and dependability.

Since the CMOS technology moving forward swiftly, digital data exchange between chips fabricated using different generations of technologies becomes a problem when the size of printed circuit board-based systems is critical for mobile or wearable devices. To achieve better performance, smaller size, and power efficiency, a 2 $$\times $$ VDD output buffer featured with process, voltage, and temperature detection and the integration of dual-Vth and standard Vth transistors optimized by W/L sizing is proposed. Slew rate (SR) self-adjustment and power–delay product reduction are also verified by Monte Carlo simulations to achieve at least 27.8% improvement and 37.6% reduction. The prototype of this investigation fabricated by a typical 28-nm CMOS process is measured on silicon to attain at least 7.6% SR improvement.

Advancements in the field of power electronics led to global changes in the electrical energy generation, transmission, and distribution. The voltage source converter (VSC) based HVDC system is the future of the power system due to the advantages it offers in terms of renewable power generation, transmission, and integration. Currently, the two-terminal VSC–HVDC systems have been successfully commissioned. Multi-terminal VSC–HVDC system is the developing trend for higher power reliability, large scale integration, and smart operation. The performance of a VSC based multi-terminal direct current (MTDC) system greatly depends upon the tuning of the controller. Standard practice is to tune the PI controller using hit and trial method or based on the operator’s experience. However, the tuning process becomes complex when multiple grids are involved. Thus, for MTDC systems, the manual tuning of the controller does not yield the desired results. This paper presents a centralized fuzzy logic-based optimization technique for VSC control of the MTDC system to obtain the optimized parameters for the PI controllers. The optimized parameters ensure a better system performance in terms of fast settling time, better slew rate, minimum undershoot, and minimum overshoot response. The proposed technique is tested on a three-terminal MTDC network in SIMULINK / MATLAB.

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

The energy range of transition-edge sensor (TES) X-ray microcalorimeters with a multiplexed readout depends upon the width and shape of the TES superconducting transition, and also on the dynamic range of the readout. In many detector systems, the multiplexed readout slew rate capability will be the limiting factor for the energy range. In these cases, if we are willing to accept some energy resolution degradation, we can significantly extend the energy range by increasing the bath temperature of operation, essentially creating a second “extended energy range” mode of operation. For example, if we require the very highest energy resolution up to 7 keV, and wish to optimize the design up to this energy, for some measurements it could be very beneficial to have a mode where we can extend the energy range to 15–20 keV even if some energy resolution is sacrificed. In this paper, we explore the trade-off between dynamic range and energy resolution from changing the bath temperature of the TES. We present measurements of TES resolution and slew rate as a function of bath temperature and compare to numerical simulations.

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

Settling time is one of the most important parameters in opamps with feedback. In this article, the step response of the fully differential single stage folded cascade architecture amplifiers is analyzed to investigate the behavior of settling time and slew rate. An important characteristic of the proposed analytical model is that the behavior of the transistors is examined in detail after applying the step in the input, and it is shown that the settling time as well as slew rate would depend on the size of the input step. The resulting model can be beneficial for design and manual calculations in integrated circuits. Moreover, to examine the validity and precision of the resulting model, various simulations are performed, which show excellent matching between the proposed analytical model and the simulation results.

Technology scaling facilitates to meet ever increasing demands for a portable and battery operated systems, at the same time causes diminution of length of the channel, gate oxide layer and threshold voltage which increases the leakage or static power at a standby mode. Static or leakage power is the dominating factor of total power dissipation in deep nanometer technologies below 90 nm. In memory design, parameters such as power, delay and stability of the memory are considered for which affects the performance of the memory. Static random access memory (SRAM) is a type of RAM, which does not need to be refreshed periodically and data is not written permanently in it. This manuscript dedicates in designing 256 × 4 memory array structure using imminent SRAM cell and sense amplifier for usage as cache memories in most modern computer systems. The other sustaining devices in executing this array structure are row decoder, column decoder and control unit. Design metrics such as static power, dynamic power, delay, power delay product, energy, energy delay product, rise time, fall time and slew rate are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that array structure designed using proposed SRAM cell and sense amplifier provides better performance than existing array structure.

Static or leakage power is the dominating component of total power dissipation in deep nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm to 54% at 65 nm technology due to continued device and voltage scaling. Static random access memory (SRAM) is a type of RAM in which data is not written permanently and it does not need to be refreshed periodically. Different techniques have been applied to SRAM cell to reduce leakage power without affecting its performance. A novel 10T SRAM architecture is proposed in this paper which operates in three modes (active, park, standby or hold). The main objective of the proposed architecture is to provide better stability and reduced delay in active mode, reduced leakage current in standby mode and retaining the logic state in park mode. Design metrics such as static and dynamic power, delay, power delay product, energy, energy delay product, rise and fall time, slew rate and static noise margin are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that the proposed SRAM is much better than conventional and other SRAM cells designed using hybrid techniques.

This paper presents two methods to reduce power consumption of switched capacitor (SC) integrators in sigma-delta analog to digital converters. The proposed two methods are based on the passive charge re-distribution technique, injecting charge into the output of the first integrator. The injected charge can be attained by a continuous function of the input voltage and feedback, or by quantizing the injected charge into three levels. In both cases, the main purpose is to minimize the initial transient voltage at the input of the first operational transconductance amplifiers (OTA), in order to bypass the slewing region of the OTA and enter into the linear settling region. Then a minor charge is left, and needs to be moved by the OTA. Using these two charge pumping techniques separately, a 10-bit performance of a conventional second-order delayed cascaded 1-bit sigma-delta modulator which consists of two SC integrators can be obtained by only consuming 60% power dissipation of the traditional structure without proposed techniques.

An ultra-low power bulk-driven operational transconductance amplifier circuit for biomedical applications is presented. Higher DC gain and improved slew rate is achieved using double recycling technique, cross-coupled positive feedback configuration and driver transistors to enhance the transconductance of the conventional bulk-driven folded cascode amplifier. The post layout simulation of the proposed bulk-driven double recycling OTA in 180 nm CMOS technology, shows a 30 dB DC gain improvement and a 250% enhancement in GBW. The above results are validated using the Monte Carlo process variation and corner case simulations. The amplifier consumes 145 nW @ 0.6 V supply voltage.

As semiconductor technologies have been shrinking, the speed of circuits, integration density, and the number of I/O interfaces have been significantly increasing. As a consequence, electromagnetic emanation (EME) becomes a critical issue in digital system designs. Electronic devices must meet electromagnetic compatibility (EMC) requirements to ensure that they operate properly, and safely without interference. I/O buffers consume high currents when they operate. The bonding wires, and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference (EMI). Therefore, I/O switching activities significantly contribute to the EMI. In this paper, we evaluate and analyze the impact of I/O switching activities on the EME. We will change the circuit configurations such as the supply voltage for I/O banks, their switching frequency, driving current, and slew rate. Additionally, a trade-off between the switching frequencies and the number of simultaneous switching outputs (SSOs) is also considered in terms of EME. Moreover, we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns. The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations. All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

The paper proposes a class-AB flipped voltage follower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the output resistance. The proposed FVF cell has several advantages such as low output resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated in Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.

A low-temperature superconducting quantum interference device (low-Tc SQUID) can improve the depth of exploration. However, a low-Tc SQUID may lose its lock owing to oscillations in the current or the occurrence of spikes when the transmitter is switched off. If a low-Tc SQUID loses its lock, it becomes impossible for the low-Tc SQUID TEM system to function normally and stably for a long period of time. This hinders the practical use of the system. In field experiments, the transmitting current is accurately measured, the voltage overshoot and current spike data are recorded, and the gradient of the primary magnetic field at the center of the transmitting loop is calculated. After analyzing the results of field experiments, it was found that when the gradient of the primary magnetic field far exceeds the slew rate of a low-Tc SQUID, the low-Tc SQUID loses its lock. Based on the mechanisms of the transmitting oscillation, an RC serial and multi-parallel capacity snubber circuit used to suppress such oscillation is proposed. The results of simulation and field experiments show that, when using a 100 m×100 m transmitting loop, the gradient of the primary magnetic field is suppressed from 101.4 to 2.4 mT/s with a transmitting current of 40 A, and from 29.6 to 1.4 mT/s with a transmitting current of 20 A. Therefore, it can be concluded that the gradient of the primary magnetic field is below the slew rate of a low-Tc SQUID after adopting the proposed RC serial and multi-parallel capacity snubber circuit. In conclusion, the technique proposed in this paper solves the problem of a lost lock of a low-Tc SQUID, ensuring that the low-Tc SQUID TEM system functions stably for a long period of time, and providing technical assurance for ground TEM exploration at an additional depth.

This work presents a 800 MHz 2 $$\times$$ VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 $$\times$$ 0.439 mm $$^2$$ , and the power consumption is 68.9/98.5 ( $$\upmu$$ W/MHz) at 450/800 MHz, respectively.

Proposed in this paper is design and analysis of an enhanced recycling folded cascode (RFC) Op-Amp. This structure is achieved using connecting two nodes and eliminating some devices in the conventional RFC. This effect enhances the DC gain with increasing output resistance of differential pair compared to the conventional RFC circuit. In the same − 3 dB frequency, the unity gain bandwidth is also increased. Moreover, for the same slew rate and input referred noise performance, other proposed improvements are the fast-settling time and total harmonic distortion. Hspice simulation results in 90 nm CMOS standard technology demonstrate that the proposed amplifier has 1.2 times the unity gain bandwidth (190 vs. 160 MHz) and also has twice gain boosting (66.2 vs. 59.5 dB) in the same − 3 dB frequency, power supply (1.2 V) and driving capacitor load of 5 pF.

A 2 $$\times $$ VDD output buffer in conjunction with a process and voltage (PV) compensation technique is proposed to keep the slew rate (SR) within predefined ranges regardless of PV variations. Temperature variation is not considered as it is found to be relatively less correlated with SR variation for a 90 nm CMOS process or better. All bias voltages in PV variation detectors are generated from bandgap circuits such that variations have been guaranteed by simulation to be less than 4.10%. The proposed design is realized on silicon using a 90 nm CMOS process, where the core area is 0.052 $$\times $$ 0.388 mm $$^2$$ . The data rate is 650/500 MHz given a 1.0/2.0 V supply voltage with a 20 pF load, respectively, by physical measurements. The $$\Delta $$ SR improvement is 30.7 and 31.4% for 1 $$\times $$ VDD and 2 $$\times $$ VDD, respectively, when the proposed PV compensation design is activated.

The Transition-Edge Sensors (TES) is a mature, high-resolution x-ray spectrometer technology that provides a much higher efficiency than dispersive spectrometers such as gratings and crystal spectrometers. As larger arrays are developed, time-division multiplexing schemes operating at MHz frequencies are being replaced by microwave SQUID multiplexers using frequency-division multiplexing at GHz frequencies. However, the multiplexing factor achievable with microwave SQUIDs is limited by the high slew rate on the leading edge of x-ray pulses. In this paper, we propose a new multiplexing scheme for high-slew-rate TES x-ray calorimeters: the spread-spectrum SQUID multiplexer, which has the potential to enable higher multiplexing factors, especially in applications with lower photon arrival rates., 12 pages, 2 figures, Submitted to the Journal of Low Temperature Physics (Proceedings of the 17th International Workshop on Low Temperature Detectors)

A modified nested-current-mirror (NCM) Single-Stage amplifier, for high-performance, liquid crystal display panels, is presented in this paper. The proposed NCM is more than 8 times faster than the original NCM structure, without any extra static power consumption. Slew rate of the NCM is improved 10 times and DC-gain is also improved 6 dB, while the power consumption, gain-bandwidth product, output voltage swing range, and the phase margin of the NCM are not affected to great extent and the input-referred-noise is reduced 12%. Proposed NCMs achieve relatively higher figure of merit in comparison to previously reported NCM amplifiers and other state-of-the-art works. The significant performance improvement is obtained due to a novel slew-rate enhancer circuit. The simulation results for the designed NCM in a typical 90 nm CMOS technology confirm the predicted performance improvements.

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits’ delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (Vth), mobility of carriers (μ0), oxide thickness (tox) and doping concentration (nsd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 × 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (1×, 2×, 3× and 4× output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.

This paper presents a low-voltage high driving capability rail-to-rail Class-AB CMOS bulk-driven (BD) operational transconductance amplifier (OTA) for analog voltage buffer with minimal current consumption. The proposed OTA design consists of adaptively biased Class-AB differential input stage to improve the effective transconductance and adaptive load relying on nonlinear current mirrors, configured in partial positive feedback mode to enhance the overall gain. In addition, because of adaptive bias and load configuration, the load-driving capability of OTA increases for a large change in differential input. The circuit is designed using UMC 65-nm CMOS process node and is operated at supply voltage of 0.5 V with a standby current consumption of 4.25 $$\upmu $$μA. Simulation results show that the buffer based on the proposed BD-OTA achieves an average slew rate of 93.2 mV/$$\upmu $$μs for a capacitive load of 100 pF, which is nearly 29 times that of conventional OTA with 13$$\%$$% increment in quiescent power dissipation.

In this paper, a single-stage class AB bulk-driven amplifier operating in weak inversion region is proposed. The presented amplifier benefits from an improved high input swing structure using quasi-floating-gate technique. The composite transistors and recycling configuration used at the input stage enable the input differential pair to operate under low supply voltages with larger transconductance as compared to the conventional models at no expense of power budget. The circuit is designed in 0.18 µm CMOS technology and simulation results show 61.5 dB low frequency gain with the gain bandwidth of 30.15 kHz and 55.3 V/ms average slew rate. The total current of 275 nA and 0.6 V supply voltage make the proposed amplifier a suitable choice for ultra-low-power applications.

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of $$2\,\frac{{\text{V}}}{{\text{V}}}$$ , this voltage combiner can produce gain more than $$5\,\frac{{\text{V}}}{{\text{V}}}$$ . So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than $$55^{\circ }$$ for a typical load of 10 pF. The input referred noise is $$150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}$$ at 10 Hz and slew rate $$0.02\,{\text{V}}{/}\upmu{\text{s}}$$ for 10 pF load.

In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high bandwidth (HBW), and high slew rate (HSR). In addition, a one-shot current boosting (OSCB) circuit was added for current control to charge and discharge the parasitic capacitance at the power transistor gate during the load-current transition to improve the response time. The experimental results show that the proposed LDO regulator consumes a quiescent current of only 4.5 $$\upmu \hbox {A}$$μA and can deliver a maximum load current of 200 mA, while regulating the output voltage at $${\text {1\,V}}$$1\,V with a 1.2 V power supply. We experimentally verified that for a current transition from 0.1 to 200 mA, the undershoot and overshoot voltages were 260 and $${\text {190\,mV}}$$190\,mV, with recovery times of only 0.8 and 0.85 $${\upmu }\hbox {s}$$μs, respectively.

This paper presents a new and compact two stage CMOS structure with enhanced gain-bandwidth product (GBW) and high slew rate. The frequency compensation technique employed here comprises of a negative capacitance cell and a flipped voltage follower (FVF). The use of negative capacitance lowers the parasitic capacitance of preceding stage and thereby achieves significant improvement in GBW. The FVF acts as a voltage buffer and exploits pole-zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. The simulated results show a GBW of 1.2 GHz and average slew rate of 88 V/µs with a power consumption of 6.3 mW.

This paper presents an adaptive Improved Recycling Folded Cascode (IRFC) amplifier with improved gain, high slew rate, high phase margin and reduced power consumption. The proposed design is implem...

This paper presents an ultra high gain two stage CMOS Operational Amplifier which is designed using self-cascoding and positive feedback technique in order to provide gain enhancement. By comparing the circuit with other designed circuits it has been shown that applying positive feedback increases the gain of the Op-Amp without affecting other properties of the amplifier. The proposed circuit is designed in 45 nm technology using Cadence Virtuoso Analog Design Environment tool at ±1 V supply. The Op-Amp is designed to achieve a high gain of 141 dB while maintaining a UGB of 101 MHz and phase margin of 60°. The simulation results conforms the estimated theoretical improvements. The dependence of various properties such as slew rate, UGB, settling time and phase margin of the designed Op-Amp on compensating capacitor CC has also been analyzed in this paper. Finally, the simulation results have been compared with a previously reported Op-Amp utilizing positive feedback technique.

This paper describes a gain enhancement method and also a slew-rate enhancement scheme for folded-cascode amplifiers which uses positive feedback + transconductance increaser method for the sake of gain increment that gives rise to approximately 21 db of increment in the amount of the gain. An approach for increasing the slew-rate has also been employed which has increased the slew-rate of the amplifier approximately 5 times the conventional folded-cascode one as well as the triple folded-cascode one. Also the settling time and consequently the speed of the circuit is improved remarkably i.e. over 6 times the conventional folded-cascode and triple folded cascode ones. The amplifier has been designed in TSMC RF 0.18 μm and consumes 920 µw of power meanwhile provides 67 db for gain, 581 MHz for UGBW, 69° for phase margin, 793 V/µS for slew-rate and 3.2 nS for large-signal settling time as well as the gain-error of the amplifier for large-signal is approximately 0.5 %. The layout of the circuit has also been carried out in Cadence and demonstrates that the op amp occupies 41 µm ? 61 µm (0.002 $$\text{mil}^{2}$$mil2) of the die area. The post-layout-simulation of the op amp was also fulfilled and the results are displayed.

In this paper a slew rate enhancement method using some extra paths in recycling folded cascode (RFC) amplifier is presented. The added transistors are in cut-off region in the small-signal operation and will be automatically turned on during slewing phase. Therefore, negative and positive slew rates are improved without increasing power dissipation in the small-signal operation. Simulation results in 90 nm CMOS technology show a 2.4 times enhancement in the average slew rate and a 69 % reduction in the settling time without affecting the gain bandwidth and power dissipation compared to the conventional RFC structure.

The paper presents a four-stage operational amplifier (OPA) with high DC gain and large bandwidth by combining no capacitor feedforward compensation and reversed nested indirect compensation. The proposed OPA is simulated in TSMC 65 nm 1.2 V CMOS process, achieving 100 dB DC gain, 330 MHz gain-bandwidth product, 266.25 V/μs slew rate and 1.56 mW power dissipation with 1.2 V supply voltage.

The paper presents a slew-rate boosted analog amplifier embedded in a digital input driver for automotive actuator control unit (ACU). The whole ACU integrated circuit has been realized in a 0.18 μm CMOS technology with embedded Flash memory. The slew-rate boosted amplifier allows to drive high capacitive loads of power FETs, with rise and fall time of few μs. The IC has been designed to face harsh automotive requirements such as extended ambient temperature range, from ?40 to 160 °C, ESD of ±4 kV as proved by experimental measurements on the fabricated IC.

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

In this paper, a new technique for enhancing the transconductance and low frequency output impedance of recycling folded cascode amplifiers is presented. These improvements were achieved by using a positive feedback and upgrading the recycling structure. The new structure benifits from better transconductance, slew rate, and DC gain in comparison to conventional folded cascode (FC) amplifier. Moreover, the input referred noise and input offset are reduced and the phase-margin is improved. The improved amplifier is simulated in 0.18 µm CMOS technology, demonstrates a DC gain enhancement of 16.4 dB as well as 117.5 MHz increase in gain bandwidth compared with conventional FC configuration. The amplifier consumes 360 µW @ 1.2 V which makes it appropriate for low-voltage applications.

This paper presents an operational transconductance amplifier compensated in frequency with a feedforward path implemented with current mirrors. This concept eliminates the need of Miller capacitor and improves performance compared to traditional feedforward topologies in regard to DC gain. Gain enhancement is achieved because of the use of current mirrors which reduces the number of the conductances that are connected to the output and increasing output impedance. Moreover, common mode range is improved by the PMOS differential pair used in the feedforward stage. Simulations results for the designed circuit on the typical UMC 180 nm CMOS process, show a DC gain above 60 dB with a unity gain frequency of 511 MHz, a phase margin (PM) of 49 $$^{\circ }$$ � , a slew rate (SR) of 205�V/ $${\upmu }$$ μ s and a power consumption of 5.1 mW maintaining low variations in regard to process, voltage and temperature variations.

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of $$53\,\hbox {V}/\mu \hbox {s}$$ 53 V / μ s with a phase margin of $$78^{\circ }$$ 78 ? .

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.

Optimizing the settling response of an operational amplifier can be a serious design issue in today's low-power CMOS technologies. Several design challenges emerge when improving the linear and nonlinear responses of an amplifier. In this paper, we developed a settling model for use in design and optimization of two-stage Miller-compensated amplifiers. Using this model, the closed-form relations between settling time/settling error, gain-bandwidth product, noise, power and stability have been obtained. These relations are employed to form a settling-based design routine for Miller-compensated amplifiers. Simulation results in 0.18- $$\upmu $$ μ m CMOS validate the effectiveness of the proposed routine. In a design prototype, it predicts the settling time with an error less than 3 %. In another design example, the relationship between settling time and gain-bandwidth has been evaluated with an accuracy higher than 95 %. The proposed design routine is used to implement a 40 MS/s sample-and-hold amplifier. It achieves a settling time and signal-to-noise-plus-distortion ratio equal to 12.5 ns and 82 dB, respectively.

In a ring oscillator, the behaviour in which the output voltage ramp (up/down) of its individual delay cell crosses the threshold, which triggers the next stage delay cell, is crucial in determining the timing jitter, and hence phase noise. Specifically, as the slew rate of the ramp decreases and/or the amount of noise contribution from the transistors in the delay cell increases, the voltage ramp (up or down) has a higher probability of crossing the threshold multiple times, before finally passing it at a time denoted as last passage time, which is more accurate than the conventional first passage time model. This multiple crossing results in a higher jitter. In the past, investigation in last passage time jitter model results in jitter expression that can only be calculated numerically and thus no design guidelines/insights are apparent. In this paper, a novel model is presented with a simple closed form formula, which shows the extra jitter, due to multiple crossing, adds a term that increases as a function of the fourth power of the noise strength/slew rate ratio. The formula is applied to a real life practical low slow rate/high noise ring oscillator which finds application, for example, in random number generator implementation. Corresponding transistor level simulation results agree reasonably well with the model. Furthermore, it is shown that, on example designs, the last passage time approach in this paper can lead to time jitter that is 100 % larger than that due to conventional first passage time model.

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces VOUT offset at medium to heavy load to counteract the VOUT drop, which is caused by ILOAD increase. Hence, transient performances of LDO and VOUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with ILOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the VOUT drop between light load and full load reduces to 0.16 mV.

In order to obtain high-performance systems on chip (SoC) using complementary metal oxide semiconductor (CMOS) technology is necessary to increase the robustness and decrease the delay, power consumption, and surface area of the integrated circuits. We present an experimental performance analysis of a class AB CMOS amplifier designed with different layout techniques (serpentine, concentric, and interdigitated). These layout techniques are evaluated in function of product potency delay area and amplifier characteristics such as electrical gain, common mode rejection ratio, power supply rejection ratio, offset, and slew rate. Based on the experimental performance results of the class AB CMOS amplifier, serpentine technique reduces its surface area to 64 %, and decreases the power consumption close to 39 % with respect to the conventional technique. In the SoC design, serpentine layout technique could be used to improve the electrical performance of their CMOS amplifiers.

A true class `AB' fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 μm CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of ±0.9 V. The interesting results such as current drive capability of ±100 μA, high output voltage swing of ±0.8 V, low static power consumption of 21 μW, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit's linearity. The transient stepwise response analysis is also done to verify the stability of proposed class `AB' FDCOS.