A new step response modeling in CMOS operational amplifiers

Settling time is one of the most important parameters in opamps with feedback. In this article, the step response of the fully differential single stage folded cascade architecture amplifiers is analyzed to investigate the behavior of settling time and slew rate. An important characteristic of the proposed analytical model is that the behavior of the transistors is examined in detail after applying the step in the input, and it is shown that the settling time as well as slew rate would depend on the size of the input step. The resulting model can be beneficial for design and manual calculations in integrated circuits. Moreover, to examine the validity and precision of the resulting model, various simulations are performed, which show excellent matching between the proposed analytical model and the simulation results.