90 results on '"Taur Y"'
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2. The mystery of the Z2-FET 1T-DRAM memory
3. Scaling MOSFETs to 10 nm: Coulomb Effects, Source Starvation, and Virtual Source
4. Technology development & design for 22 nm InGaAs/InP-channel MOSFETs
5. Simulation of Electron Transport in High-Mobility MOSFETs: Density of States Bottleneck and Source Starvation
6. Effect of Body Doping on the Scaling of Ultrathin SOI MOSFETs.
7. New polysilicon disposable sidewall process for sub-50 nm CMOS
8. Single pulse output of partially depleted SOI FETs
9. CMOS scaling beyond 0.1 /spl mu/m: how far can it go?
10. Full-swing complementary BiCMOS logic circuits.
11. A High Performance Liquid-Nitrogen CMOS SRAM Technology.
12. 0.5 μm CMOS Device Design and Characterization.
13. High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply.
14. 0.1 mu m CMOS and beyond.
15. 0.5µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation.
16. A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2.
17. Characterization and modeling of a latchup-free 1-µm CMOS technology.
18. Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process.
19. A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS.
20. A high performance 0.25 mu m CMOS technology.
21. Design and fabrication of p-channel FET for 1-µm CMOS technology.
22. A comparative study of hot-carrier instabilities in p- and n-type poly gate MOSFETs.
23. A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP).
24. A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS.
25. Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing.
26. Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET.
27. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel.
28. 25 nm CMOS design considerations.
29. A novel high-performance lateral bipolar on SOI.
30. A 4 Mb Low-temperature DRAM
31. Mobile ion gettering in passivated p+ polysilicon gates
32. A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
33. Device scaling limits of Si MOSFETs and their application dependencies.
34. Scaling Limit of CMOS Supply Voltage from Noise Margin Considerations.
35. Josephson Junctions as Heterodyne Detectors.
36. A 4-Mb low-temperature DRAM.
37. A high-performance 0.25- mu m CMOS technology. II. Technology.
38. A high-performance 0.25- mu m CMOS technology. I. Design and characterization.
39. Very high performance 50 nm CMOS at low temperature.
40. Fully depleted 0.25 /spl mu/m MOSFETs on SOS, SIMOX and BSOI substrates.
41. A self-aligned 1-µm CMOS technology for VLSI.
42. A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider.
43. A Josephson effect parametric amplifier at 36 GHz.
44. Generalized scale length for two-dimensional effects in MOSFETs.
45. High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/.
46. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's.
47. Experimental high performance sub-0.1 /spl mu/m channel nMOSFET's.
48. Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide.
49. BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS.
50. A new 'shift and ratio' method for MOSFET channel-length extraction.
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