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3D stacking technology presents benefits over 2D by providing an increased packing density, however, signal routing complexity increases significantly. Moreover, the high-density 3D vertical interconnects can cause additional signal integrity degradation due to parasitics from different directions and coupling noise. This can severely impact system performance. This paper shows a detailed case study of signal integrity and electrical modeling for 3D Vias based on MIT 0.15 µm 3DFDSOI process technology. The three-dimensional EM field solver (HFSS) and Advanced System Design simulator (ADS) are used to conduct 3D circuit analysis and simulations in both frequency (S-Parameters) and time (Eye Diagram) domains. In addition, a proposed circuit 3D test architecture based on the Gunning Transceiver Logic (GTL) I/O is proposed, which can potentially validate the 3D Via electrical modeling.

Image enhancement and segmentation is widely used for fingerprint identification and authorization in biometrics devices, criminal scene is most challenges due to low quality of fingerprint, the most significant efforts is to develop algorithm for latent fingerprint enhancement which become challenging problem due to the complex and existing problem for instance, developing algorithms of latent fingerprint is able to extract features of image blocks and removing overlapping and isolate the poor and noisy background. however, it’s still challenging and interested problem specifically latent fingerprint enhancement and segmentation. The aim study of this paper is to propose latent fingerprint enhancement and segmentation based on hybrid model and Chan-Vese method for segmentation, in order to reduce low image quality and increase the accuracy of fingerprint. The desired characteristics of intended technique are adaptive, effective and accurate, hybrid model of edge adaptive direction achieves accurate latent fingerprint enhancement and segmentation, the target needs to improve feature detection and performance, this research has proposed system architecture of research method in fingerprint enhancement and segmentation where is the method content two stages, the first is normalization and second is reconstruction, using EDTV model is required for adaptive noise, in addition Chan-vase technique contributed for identification of fingerprint image features, the result and testing using RMSE with three categories of fingerprint images good, bad and ugly show better performance for all three categories, as well RMSE shows the average of good latent fingerprint before and after enhancement. Latent Fingerprint Enhancement and Segmentation Technique Based on Hybrid Model Edge Adaptive Directional Total Variation

This research introduces the distributed ledger technology (blockchain) in terms of sustainable development in the future. This study is based on private, public and global communications in various industries. The growing demands for secure and decentralized transactions around the world demonstrate the need for Blockchain technology as a medium of operations and communications. The blockchain system is completely decentralized and allows users to exchange messages in an efficient and secure manner. The highlight of the paper is the anticipated future use of blockchain networks as a communication tool in every business and digital economy for a safe and sustainable development, while presenting its advantages and limitations that have been confirmed based on the experiences of various experts. Moreover, the article provides recommendations for the use of blockchain to greatly complicate its identification in future communications. The paper also concludes that the use of the blockchain system could be beneficial and enhance future communications and digital technologies.

An automated essay scoring system (AES) is advantageous in evaluating student’s learning outcomes since it gives them the chance to exhibit their knowledge. Most of the AES is using machine learning (ML) to enhance student’s scores but did not consider the proper construction of the essay questions. This study aims to integrate the cognitive level of Blooms’ taxonomy (BT) in constructing essay questions and compare the scores of the student. Identifying the most appropriate ML method in classifying essay exam questions (EEQ) based on BT that will be embedded in the Essay Question Generator (EQG). Using F1-Measure, the evaluation results show that the Support Vector Machine (SVM) (85.7%) outperforms Naive Bayes (82.6%) and K-Nearest Neighbor (77.6%). Therefore, SVM together with the NLP techniques is applied to automatically extract essay questions from the given text for the teachers to select and apply. The EQG was evaluated using the scores of 375 students who answered two sets of essay exam questions using Bloom’s Taxonomy (BT) and without Bloom’s taxonomy (NBT). Using frequency distribution, the scores between two types were evaluated and the result shows that most students performed well in answering the essay exam using BT 5.6% of the students obtains a perfect score of 5.0 but nobody got 5.0 for NBT. In a conclusion, this study shows that the essay questions constructed according to BT cognitive level produce higher scores using EQG when compared to exam questions prepared by the teachers.

Biometrics such as face, fingerprint, iris, voice and palm prints are the most widely used, and as well the fingerprints are one of the most frequently used biometrics to identify individuals and authenticate their identity. commonly categorized into three different categories which are rolled, plain and latent fingerprints. The reliability of image segmentation for latent fingerprint which is used in criminal issues still challenges, The difficulty of latent fingerprint image segmentation mainly lies in the poor quality of fingerprint patterns and the presence of the noise in the background, This research has investigated the fingerprint segmentation and matching based on EDTV and presented Chan-vese active contour segmentation technique, in addition, presented NIST SD27 for grayscale dataset of latent fingerprint which is standard by National Institute of Standard and Technology, where is dataset have varieties of fingerprint image samples, a total about 258 of latent fingerprint, those samples collected from crime scenes and matching fingerprint and shown the performance of matching accuracy ROC and CMC curves, To evaluate the performance of the matching ROC and CMC curves has been deployed, The area under curve (AUC) of the ROC of the good images performance is 72% with CMC rank1-idnetification of 42% and rank-20 identification of 79%. the result shows that the latent fingerprint method performance is better for good latent fingerprint images compare to bad and ugly images, while there is no much difference for bad and ugly image.

In this paper, a low-power CMOS temperature sensor based on a diode-connected NMOS FET is proposed. A sub-1V voltage reference is adopted to generate a temperature-invariant current source to bias the sensor device. The temperature sensing NMOS transistor is sized to maximize the temperature sensitivity. The proposed design is simulated based on 90 nm CMOS process technology, which shows temperature sensitivity of 0.25 mV/0C with a temperature range of from 00C to 1000C.

3D technology promises significant benefits to offer shorter interconnect and higher integration systems enabling improved performance and lower power consumption. Nevertheless, 3D stacking is facing strong thermal challenges due to higher power density and minimal heat dissipation which might cause performance and reliability degradation. This paper discusses the thermal evaluation and modeling of 3D stacked ICs. A 3D computational fluid dynamics (CFD) thermal analysis tool called FloTHERM by Mentor Graphics is used to evaluate the effect of stacking the chips on the temperature rise of 3D ICs. In our thermal modeling, all stacked chips were treated as lumped blocks with estimated thermal conductivity of the TSV chip. The stacked chips have the same size (5x5x0.1mm). The power dissipated by each chip is 0.02 W and it was assumed that the power is uniformly distributed on each chip. The maximum junction temperature with number of stacked chips were also evaluated.

this paper present artificial neural network using SOFM and vector quantization (VQ) which has gained many research concentration and importance to improve the image quality after lossless comfpression to reduce image size. The aim of this research is to investigate image compressing using SOFM 2D K-Map with vector quantization methods and arithmetic coding of lossless compression methods, SOFM and VQ are adopted technique to improve the image compression effective. However, this paper proposed and investigated SOFM based on VQ by components, the proposed new approach which provide pre-processing for subsampling into high-pass filter and low-pass filter, low pass-filter subsampling goes immediately to lossless compressing for entropy coding and as presented here is used arithmetic coding, and high-pass filter to vectorization image block then to vector quantization using SOFM. The investigation shows there are many methods used types of filters as first stage of pre-processing in image compression before entropy.

Resources allocation has become an essential component for high-speed networking data systems. Several studies have proven that conventional spectrum allocation approaches are becoming insufficient to address the rapid demand in networking spectrum which resulted in spectrum under utilization. The main goal of this work is to develop a new model for resource allocation using Shuffled Frog Leap Algorithm (SFLA). Thus, a modified power for optimal allocation strategy is introduced and integrated to a simple OFDM functions according to the research’s aims. Then, the solution has been numerically validated and verified by simulations based powerline channel. Finally, the system performance was evaluated in term of system’s capacity, allocated bit/power, and convergence.

One of the common learning activities used in educational levels and disciplines is essay writing. The problems of the essay writing activities are time-consuming, concerns in producing immediate result and/or feedback from teachers to students, and the teachers tend to be subjective in grading the essay activities. The study aims to apply the preliminary approach forautomatically generating the domain concept ontology in essays using OntoGen and applied natural language processing algorithms using NLTK (Natural Language Tool Kit) that enhance the teachers essay grading.

The aim of the research is to propose a new approach to image coding using SOFM and spatial frequency band-pass filter to investigate the Artificial Neural Network. The approach is based on SOFM which is similar to vector quantization (VQ) and it is adopted the technique to improve the image compression effectively. In the approach has been using the band-pass filter for image compression by SOFM based on vector quantization by components as the original image and the spatial frequency image component, which is derived from the adaptive to the contours of the 2D analysis and synthesis. The calculation of the computational cost is compression based on SOFM. The new approach of image coding using a band-pass filter, where is used as a first stage of proposed method of image encoding and as well as the image decoding has been presented with De-quantization with entropy coding based on arithmetic coder and high pass filter, the evaluation with jpeg format compression shows, that using 16x16 image block of pre-processing in SOFM has given the best compression ratio with small SNR. On the given experiment shows the different pixels presented by Lena.bmp, girl256.bmp and compared with a compression ratio of the Iena.jpeg file.

the effective facial recognition method should perform well in unregulated environments based on video broadcast to satisfy the demands of applications in real-world However, this still remains a big challenge for most current face recognition algorithms that will affect the accuracy of the system. This study was conducted to develop face recognition method based on video broadcast under illumination variation, facial expressions, different pose, orientation, occlusion, nationality variation and motion. Viola-Jones algorithm was applied to improve face detection which is these method have proven to detect the faces in an uncontrolled environment in the real world simply and high accuracy. A combination of Histograms of Oriented Gradients (HOG) and Local Binary Pattern (LBP) descriptors was conducted for faces features extraction purpose. These descriptors have proven to be lower computational time. The latest and accurate technique was applied for face classification based on Random Forest classifier (RF). To evaluate the efficiency of the Random Forest classifier, compared it with Support Vector Machine classifiers (SVM) is done with different existing feature extraction methods. Four experiments were implemented on Mediu staff database and excellent results have reported the efficiency of proposed algorithm average recognition accuracy 97.6% The Computer Vision and Image Processing MAT LAB 2016b Toolboxes was used for coding the desired system, dataset based on videos.

This paper reports a multi-sensing system that consists of two separate devices equipped with a set of multiple pressure sensors. The first device is a stent that to be inserted in the abdominal aorta; close to the renal arteries. The second one is a filter which has to be placed in the inferior vena cava, adjacent to the aortic stent. The two devices, side by side, are expected to be capable of continuously monitoring the hemodynamics, i.e., of the abdominal aorta and the inferior vena cava, in heart failure patients. This arrangement is advantageous in overcoming declination in the kidneys' functions. The multi-sensing system outputs will then be interrogated via external RF electronic hardware. Collected data from both devices allegedly will provide a comprehensive view of the current status of the heart failure patient, and alerts any possible prevalence of kidney impairment.

This paper presents a signal integrity study of 3-D Vias in three-dimensional integrated circuits based on their structural parameters, which include Via height, Via pitch, and Via size. Additionally, we show the electrical characteristics and performance of 3D interconnect for a stacked Vias structure. All Simulation results are based on 0.15 μm MIT 3DFDSOI technology, and obtained using the 3D Full wave simulator (HFSS) From Ansoft Corporation and the Spice-type Advanced Design System simulator (ADS) From Keysight Technologies to model and characterize 3-D Vias in frequency and time domains respectively.

This paper reports on 3-D Via crosstalk characterization in three-dimensional integrated circuits. Several physical and environmental configurations are investigated using a 3D electromagnetic field solver. In particular, this work shows a detailed study on the influence of signal-ground 3D-Via locations, distances and their structural configurations on crosstalk. Simulation results are presented using HFSS from Ansoft Corporation and based on the MIT Lincoln Lab for the 0.15μm 3DFDSO1 process technology.

This paper presents a resistor-free self-regulating CMOS ring oscillator (RO) whose oscillation frequency is insensitive to supply noise variations. The proposed RO design achieves self-regulation by adopting a cross-coupled dual latch-based scheme; Proper custom device sizing of the cross-coupled latches can improve supply noise immunity and frequency stability compared to a simple inverter design. A Five-stage RO is designed and implemented as a test vehicle which shows > 40% improvement in reducing supply noise sensitivity with a maximum frequency of 1GHz and 0.7mW power consumption. The simulation results are obtained using the Spectre simulator based on digital CMOS 0.09μm process Technology.

This paper describes a new architecture of a high-resolution multi-edge delay generator for on-chip testing applications, which enables a timing generation with a sub-gate delay resolution to be fully implemented in any purely digital CMOS process. The proposed delay generator utilizes multi edge-triggered oscillators to achieve a high resolution based on the Vernier technique with low power, a smaller footprint and without requiring a high speed clock reference compared to the conventional delay generators. In addition, the maximum measured delay range of the proposed design can be improved without degrading the achievabl5ve resolution. Simulation results based on 0.09 µm CMOS technology shows an achievable delay resolution of 14.6 ps with a reference input frequency at 500 MHz.

Nowadays to capture an emerging opportunity, when beyond the abilities of single organizations, increasingly results the formation of a Virtual Organization (VO). Typically, the VO consists of a group of independent, autonomous, and heterogeneous entities that constitute agents agreeing to collaborate and jointly fulfill certain common goals. However, within the VO, agents expose different behaviours, and in case of frictions during agents' interaction and co-working, drastic results and even total failure of the VO may be followed. Monitoring the behaviour of both the individual agents and the sub-groups within the VO, can identify/predict problem areas and potential frictions among agents, what can then be used for enhancing the health of the collaboration, and thus the survival and success of the VOs. We propose a framework for controlling the VO partners' behaviours through monitoring their norms. The paper addresses three kinds of behavioural norms including the socio-legal norms, the functional norms, and the activity-related norms in VOs. The main norms ruling over socio-legal aspects applied to VOs are either clear and known, or defined within the VO's consortium agreement. Typically, during the VO creation phase, the high level agreed and expected agents' activities and inter-relations are represented through the VO contracts. Fulfillment of these coarse-grained activities corresponds to functional norms. Nevertheless, due to the VO's dynamic and evolutionary nature, during its operation phase many other agreements are continuously made among its involved agents. These agreements are then modelled as promises, while keeping these promises constitute the activity-related norms.

Virtual organizations (VO) consist of a group of agents (individuals, enterprises, or intelligent machines) that collaborate towards achieving some common goals. Partners of the VO are independent, autonomous, and heterogeneous, thus often exhibiting complex behaviors in working together. While behaving collaboratively facilitates both performing the joint tasks and achieving the common goals of the VO, frictional behavior even if demonstrated by a few partners, may cause drastic results and total failure of the VO. Therefore, it is necessary to define a suitable framework to be able to model and analyze the partners' behaviors. However, on one hand the VO contracts usually address partners' tasks at the high level only, and on the other hand VOs are dynamic and continuously evolving. Consequently, contract terms do not sufficiently define the detailed daily activities of partners. Rather, partners in the VO perform their daily activities according to the detailed set of tasks planned and agreed together with the VO coordinator. Nevertheless, partners' daily activities comply with the commitments they have made once in their written contracts. This paper introduces a framework in which promises are incrementally made by the agents, to indicate their detailed agreements on the daily tasks to perform, and in turn promises and their fulfillments formalize the VO partners' behavior.

This paper focuses on TSV and interconnect signal integrity characterization of 3D IC embedded test structures that measure GTL high speed I/O performance. The three Tiers of a CMOS 3D IC were fabricated by MIT Lincoln Laboratory in a 150nm SOI process bonded together and the test structures were ball-bonded on to a custom FR-4 board designed for matched 50Ω microwave and high speed transient measurements. The comparison between on-chip and FR-4 board measurement results for TSV and interconnect signal integrity characterization will be shown and analyzed using equivalent electrical models. In addition, the paper reports extensive additional on-board measurements including, 1) 3D IC GTL I/O response to varying data patterns, 2) Edge timing comparing GTL signals launched from several 3D IC Tiers simultaneously to the same I/O output, and 3) GTL I/O performance under degraded environmental conditions in the 3D IC such as reduced bias.

In this paper, a low-voltage (sub-1 Volt) resistor-free voltage reference is presented. The complete design was simulated and laid out in AMI 0.5 µm CMOS process. The design provides a temperature coefficient of 12.8 ppm/°C over a temperature range from 25 to 100 °C and occupies an area of 0.037 mm2. Circuit description and experimental results of the proposed design are also presented.

This work focuses on characterizing the performance of the 3D TSVs under high speed transient simulation, which could potentially evaluate and verify the electrical models for these vertical connections. A Gunning Transceiver Logic (GTL) I/O on-chip test IC and a CML/Thermal test IC has been designed and sent for fabrication using the 3D FDSOI CMOS technology. The GTL I/O circuits are used to inject different data patterns at different frequencies across different tiers. A control MUX with Tri-state buffers and control logic can be used to switch between different I/O GTL drivers at different tiers. The GTL I/O test IC is dedicated to measure the NEXT/FEXT crosstalk between vertical connections by firing high speed signals from different tiers. The data-dependent-Jitter (DDJ) will be characterized by observing the eye diagram for a random and different data patterns. CML I/O circuits were designed to characterize high speed differential transmission, especially, the performance of high current buffers in the three tiered-system implementation. Differential signals were used to test the performance of through—silicon vias (TSV) and interconnect as the signals transmit from IC tier-to-tier. In addition, temperature sensors were integrated in order to model the 3D thermal performance as affected by the I/O drivers.

A high-speed scalable programmable divide-by-N frequency divider is presented. The divider includes a new proposed state look-ahead parallel counter with a basic conventional D-type Flip-Flop (DFF) circuit. The counter is structured from two modules of 2-bit counter stages separated by DFF buffers, where all are triggered at the edge of the input clock. The reload circuit is a single DFF buffer, while the detecting count circuit is constructed from a two level decoder. The M-bit divider critical path delay, which is independent of technology, is approximated to [3.5 + Log4 (M)] of a unit delay close to a 2-input NAND gate. This results in a measured frequency, which slightly drops to about 6% against the increase of the divider bit size. Furthermore, the divider circuit is attractive for continued technology scaling since the architecture is based on using identical modules of small count of CMOS transistors with only threshold voltage technology limitations. The measure rate of the number of transistors is approximated to a linear increase of about 17% per a two-bit increase of the divider size. The presented 8-bit programmable divide-by-N frequency divider is capable of operating up to 2 GHz for a 1.35 V power supply voltage with a maximum power consumption of 16.78 mW and a maximum frequency divider factor of N=256 using the TSMC 0.15 mum digital CMOS process, and gives a measured area of 95*143 mum2 with a total count of 508 transistors.

A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage

Due to the high nonlinearity and the mathematical complexity of power electronics circuits, their analysis has become more infeasible to describe. Power Electronics Education is a daunting, challenging task and many undergraduate students find it very difficult to grasp the basic concepts of many power electronics circuits and understand their physical and operational modes. In this paper, an interactive power electronics teaching Web site is proposed and, three main Web pages are developed for students, instructors and interactive Java Applets. Interactive online materials are posted for both students and instructors including lecture nodes, simulation problems, examples and exercises, textbook presentations, and online exams. A feedback form is used to get the input of students and instructors on the Web site. Interactive applets are developed for 29 power electronics circuits to help students better understand the circuit behavior under certain circuit parameters variations. Exact steady state waveforms are plotted with flexibility to have students change different circuit parameters and observe the circuit response in an interactive manner. This project represents the first phase in the development of interactive sites in power electronics education. The current Web site is located at www.batarseh.org. Phase two will focus on closed loop response and dynamic modeling, and phase three will emphasize on the system design of power electronic circuits.