Structural parameters effect on signal integrity of inter-tier vias in 3D stacking technology

This paper presents a signal integrity study of 3-D Vias in three-dimensional integrated circuits based on their structural parameters, which include Via height, Via pitch, and Via size. Additionally, we show the electrical characteristics and performance of 3D interconnect for a stacked Vias structure. All Simulation results are based on 0.15 μm MIT 3DFDSOI technology, and obtained using the 3D Full wave simulator (HFSS) From Ansoft Corporation and the Spice-type Advanced Design System simulator (ADS) From Keysight Technologies to model and characterize 3-D Vias in frequency and time domains respectively.