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This paper reports on integrated FET-based terahertz detectors operating in discrete frequencies spanning from 0.7-3.6THz. They are fabricated in standard 180nm CMOS process technology, and occupies a 2.7×3.0 mm2 chip area. Based on the Dyakonov and Shur theory, multi-pixel detectors are implemented by strict performance optimization and process compatibility. The simulated results demonstrate a promising application in low-cost terahertz spectrometer and imaging fields.

Quantization inference has been ubiquitously utilized in edge computing devices, enabling numerous neural networks' efficient deployment. However, the existing methods generally concentrate on classical network structures like VGG-16 and ResNet, ignoring the emerging compact networks such as MobileNets. Specifically, these networks with lightweight architectures have fewer parameters; thereby, less redundancy can be exploited in the quantization stage, which often incurs intolerable accuracy degradations. To handle these problems, we propose a novel Rounding Shift Channel (RSC) post-training quantization method using layer search. We alleviate the accuracy degradation via channel-wise scaling by minimizing a layer-wise reconstruction quantization error. Furthermore, we design a rounding-shift operation to correct biased inference, which has not been explored in previous integer-only-inference studies. The experiments carried on ILSVRC-2012 show that we can achieve 70.1%and 69.9% top-l accuracy for MobileNet V1 and V2, respectively, manifesting the effectiveness of our method. We open-sourced our code at https://github.com/xumengmeng-97IMV-Quantization.

The exponential growth of cloud computing and artificial intelligence asks for an ever-increasing communication bandwidth within the datacenter. Silicon photonics interconnect provides a promising way to achieve high-integration and low-power, which is essential for high-density hyper-scale datacenters. Among all electrical-to-optical (E/O) conversion solutions, the Mach-Zehnder modulator (MZM) outstands with wide optical bandwidth and high linearity, but suffers from the low modulation efficiency. To achieve 4-5dB extinction ratio (ER), 2-3 mm length phase shifters with traveling-wave (TW) electrodes are typically employed [1], [2]. However, the lossy electrode introduces significant attenuation at high frequency. Therefore, the TW-MZM requires higher drive-swing to obtain the same ER than the lumped modulator, which is hard for CMOS. To solve the problems, segmented MZM (SE-MZM) is proposed, consisting of multiple lumped capacitive segments [3], [4].

This paper introduces a multi-purpose image processing system. The major components of the system are a vision chip that is dedicated to visual image processing, and a field-programmable gate array (FPGA), which handles all the inputs and outputs (IO) of the system. Using an FPGA, the system supports various IO protocols, on-line and offline work modes. Furthermore, using a vision chip for image processing, the system can obtain high performance up to 208 Giga Operations Per Second (GOPS) and high energy efficiency up to 194 Giga Operations Per Second Per Watt (GOPS/W) for image processing.

Harris corner detection is a common operation in the field of image processing, but suffering from computation complexity in embedded system. The current method of corner detection is to process one pixel in one clock cycle. With the improvement of image acquisition method in modern society, higher processing speed requirements have been proposed for the implementation of corner detection. This paper presents a new pixel-level parallelism FPGA implementation for Harris corner detection, which double the processing speed or more with almost no decreasing in accuracy. It is implemented on FPGA in the high-speed camera, and the experimental results show that the implementation is suitable for real-time applications.

This paper introduces the design, analysis and simulation results of a driver for high-speed silicon photonic modulators. To achieve the high swing and high linearity simultaneously, several broadband circuit topology and techniques are employed, including the pre-emphasis circuit, variable gain amplifier and push-pull output stage. The driver is implemented in a 130nm BiCMOS process, achieving 22GHz bandwidth, 4V PP output swing, 900mW power consumption in the post-layout simulation.

This work proposes a simple method of calculating FD capacitance in 2-dimensional (2D) TCAD simulation that combines with pixel layout, simplifying the estimation of CIS FD design. Approximate per unit FD junction capacitance can be extracted by few TCAD simulations. This method has been verified using an image sensor chip with 10um-size pixel fabricated in 180nm CIS process. The testing results show that the error percentage of FD capacitance between test and calculation is approximately 5.90%.

This paper proposes a high-speed low-cost VLSI inference accelerator for depthwise separable convolution in deep convolutional neural networks (CNNs). The accelerator consists of parallel, pipelined depthwise convolution processing element array and pointwise convolution processing element array to improve system performance, with optimized hardware resource consumptions. Moreover, the PPE array can support fully-connected layers in CNNs. An FPGA prototype of the proposed accelerator was implemented. It executed a 12-layer simplified MobileNet model at a high speed above 15,000 frames per second (FPS) on $32\times 32$ images and 240 FPS on $224\times 224$ images.

The performance requirements of phase-locked loops (PLL) for the emerging applications such 5G and IoT are continuously growing. Compared with the conventional single-path loop based PLL, including the charge pump based PLL, sub-sampling PLL and all-digital PLL, the hybrid dual-path loop based PLL architecture (HDL-PLL) can combine the advantages of all these three kinds of single-path loop based PLL to achieve better performances. This paper first gives an overview of the basics, advantages, and the recent research progress of HDL-PLL. Then, two design examples based on our recent research with their measurement results are introduced to show that the HDL-PLL architecture can effectively improve the PLL performances.

The past five years has witnessed tremendous success of deep learning (DL) algorithm in the computer vision field, attributing to its high degree of accuracy on numerous visual tasks. Unfortunately, for the development of programmable vision chips, algorithm verification remains a major challenge due to the high computational complexity of the DL neural network. In this paper, we propose a novel chip-level verification method to address the common issues including low efficiency and poor reusability in verifying vision chips. In contrast to the block-level verification technique, this method focuses on the rapid implementation of the complete DL algorithm in chip-level verification, fulfilling the advanced demands of vision chip prior to the tape-out. The experiments on MobileNet-v1 indicates the significant reduction of the simulation time and debugging overheads via the proposed verification method.

A 50Gb/s PAM-4 optical receiver with Silicon Photonic (Si-Ph) photodiode (PD) and CMOS linear transimpedance amplifier (TIA) is presented. To optimize both noise and bandwidth, a two-stage front-end architecture—a high gain-low bandwidth TIA followed by a two-stage continuous time linear equalizer (CTLE) is adopted. Gain adjustment of the entire link is achieved by adjusting the TIA feedback resistor and the voltage of variable gain amplifier (VGA) to ensure that the receiver analog front-end (AFE) remains linear over the entire photocurrent input range. The chip has been realized in 40nm CMOS process. Experimental results show the TIA achieves 66dBΩ transimpedance gain, 24.4GHz bandwidth, 20dB gain dynamic range, maximum overload current 2mA, and differential output swing of 400mV. The total power consumption of the chip is 125.4mW.

In recent years, customized chips for accelerating deep learning algorithms have been continuously developed with some emerging challenges in the field of deep-learning-based vision chips. Considering the lack of algorithm-level verification tools, poor reusability of simulation code and low development efficiency in deep learning vision chip verification, a novel verification method, which is based on the fixed-point simulation tool, is proposed and utilized in the development of an array-based deep learning vision chip. This simulation tool, implemented by combination of Matlab and CUDA C, enables efficient and accurate verification of the vision chip by taking the classical MobileNet V1 as the benchmark. This method, integrated with the RTL and FPGA co-verification seamlessly, provides the golden reference and reliable verification during the entire development period of the vision chip.

With the popularity of pruning operations in neural networks, the percentage of zero-operands in mainstream neural network computing is getting higher. To meet the low-power requirements of neural network computing, the zero-skipping operation in multiplication is used in deep learning computing. This paper proposes a zero-skipping design of low-power multiplier for vision chips, which reduces the power consumption of the arithmetic and logic unit (ALU) by up to 32%, of which the low power consumption effect is remarkable.

This paper presents a terahertz source using standard CMOS process. The terahertz source is implemented with 4 mutual coupling oscillator cores based on injection locking theory. The push-push architecture is adopted in each oscillator core to generate the fourth harmonic signal. Moreover, on-chip patch antenna is integrated with each oscillator to radiate the output power. Frequency tuning is achieved by changing the phase shift between adjacent oscillators. The simulation results show that the source operates at the fundamental frequency of 86.5 GHz. The simulated fourth harmonic output power of each core is -15 dBm and the phase noise is -115 dBc/Hz at 10 MHz offset.

This paper describes an inverter-based receiver analog front-end design using T-coil technique implemented in a 40nm CMOS process. The proposed T-coil can separate the capacitance of PAD and preamplifier itself, to achieve a total bandwidth enhancement ratio of 2.7. The proposed continuous time linear equalizer(CTLE) adopts a negative feedback loop to generate low frequency zero-pole pair to slower down the compensation slope. The simulation result shows that the transimpedance gain of the system is 76.5 dBΩ under the bandwidth of 37GHz. The input referred noise current in maximum gain mode is 2.3uArms.

This paper proposes an intelligent surveillance system(ISS) based on Lightweight Single Shot Multibox Detector(L-SSD). L-SSD simplifies the backbone of SSD, dramatically reducing the cost of network computation by 28x fewer parameters than SSD. Furthermore, L-SSD adopts a novel method which can perform cross-layer feature fusion without increasing of computational resources. Firstly we implement L-SSD network on GPU and gets the performance of 6.5mAP at 65 fps for the VOC 2007 detection task. Then when L-SSD is actually implemented on NCS, its real-time frame rate can reach 7–8 fps.

This paper presents a high-speed 2b/cycle SAR ADC. By resolving their comparison time with a 1-bit TDC, the number of comparators are reduced to two instead of three in a conventional 2b/cycle SAR ADC, which benefits power and linearity simultaneously. The proposed capacitor-halving switching method can realize the same input common-mode (CM) voltage variations on two comparators during the conversion phase. A simple novel high-speed dynamic SAR logic is developed to achieve the direct and fast control from the comparator to DAC arrays. Moreover, a simplified double-tail comparator is presented to accelerate the voltage comparisons. A 8-b prototype ADC is designed in 28-nm CMOS process, operating at a 1-V supply voltage. The simulated (including noise) results show that under a 1-GS/s sampling rate, the ADC achieves a SFDR of 63.4 dB and a SNDR of 46.5 dB at Nyquist frequency and consumes 2.2-mW power, leading to a Walden FoM of 12.8 fJ/conv.-step.

This paper proposes a low-cost hardware system for rapid classification of visual objects encoded in the address-event representation (AER) format. A lightweight statistical inference algorithm is implemented in the proposed hardware to process the asynchronous pixel address streams from an AER visual sensor. The algorithm involves only a few simple operations for patch-based binary feature extraction and Random Ferns inference, which are highly parallelized and accelerated by our dedicated hardware architecture. Simulation results suggested that our hardware system was able to process as many as 50M address events per second and achieved 75% classification accuracy for the popular MNIST-DVS dataset. Compared to other AER classification systems, our low-cost FPGA implementation is more plausible for embedded applications because of its similar accuracy and higher system throughput.

This paper proposes a pixel-parallel Eulerian Video Magnification (EVM) algorithm for vision chips. The proposed algorithm is optimized for the stereotyped programmable pixel-parallel array processor architecture favored by high-speed vision chips. We also propose an improved pixel-parallel array processor with alternative image border padding modes to satisfy various algorithm requirements. We implemented an FPGA prototype of an improved 128 × 128 pixel-parallel array processor to run the proposed optimized EVM algorithm with a 120 MHz clock. Experimental results show that our pixel-parallel system can magnify subtle motion clues at a very high speed up to 20, 000 frames per second (fps).

This paper proposes a high-speed tracking system based on a multi-parallel-core processor architecture and a convolution neural network (CNN)-based tracking algorithm. Multiple processing cores are designed in the processor architecture, and they can parallel carry out operations. Each processing core can access data from another processing core through a interconnect control module (ICM), which make it easy to run CNN. Other components, such as Microprocessor Unit (MPU) and Data Transfer Control Module (DTCM), are also designed for global controlling and data transmitting. The proposed tracking algorithm is based on CNN which mainly contains three convolution (CONV) layers and one full connection (FC) layer. Based on an analysis of equivalence, the softmax layer is discarded when inferring. Because the conciseness and the effectiveness, the algorithm can be executed efficiently on the processor architecture, and Experiment results demonstrate that the tracking system based on the proposed algorithm and processor can achieve high-speed target tracking up to 880 fps.

As the optical module bandwidth fastly developing towards 400Gb/s, the single-channel data-rate reaches 56Gb/s. This leads to both architectural and bottom-level components change in the transceiver modules. More significant bandwidth shortage, nonlinearity, as well as noises are experienced by the optical devices. This paper reviews the challenges and key techniques in the design of laser and modulator drivers in CMOS. The solutions for 400G Ethernet are firstly introduced, which is then detailed in topology and core chips organization. Then, the circuits design for PAM4 modulation are discussed and demonstrated, respectively in a CMOS 50Gb/s VCSEL driver and a CMOS 50Gb/s Si-photonic MZM driver. The clock and data recovery (CDR) technique for direct PAM4 modulation is studied, which is then utilized to build the high integrity transmitters in CMOS.

This paper presents a dual 28Gb/s modulator driver with on-chip PAM4 clock and data recovery (CDR) in 40nm CMOS. Used in the 400G Ethernet, 56Gb/s PAM4 signal is recovered by the CDR and demodulates into dual-28Gb/s NRZ data streams to drive the silicon photonic MZM DAC. Push-pull driver cells are employed to reuse the current for power saving with high-swing output. A digital-assisted distributed topology is proposed, extending the driver bandwidth and enabling low-power flexible pre-emphasis within each segment. Precise retiming is implemented by phase interpolation for the velocity match both in distributed driver segments and MZM DAC segments. Measurement results show the CDR+driver achieves 4Vpp differential voltage swing, 1.78ps RMS jitter and 1.34W power consumption (including PAM4 CDR and dual-channel driver) at 50Gb/s PAM4 input, while the standalone driver contributes to 1.5ps RMS jitter at 28Gb/s NRZ outputs.

This paper proposes a tracking algorithm of generic target based on multi templates and regression network. In order to improve the robustness and accuracy, the proposed tracking algorithm keeps a template set to remember target in different states, and uses the motion information of target in the last image frame to crop a searching region from current image frame. Then, the templates and the searching region are input to a two-branch network (regression network), and the predicted status information of target and confidence are output by the network. To keep the template set adaptable to the state change of target, a special template updating method is proposed. Some training methods are also used for training the networker to get a more effective tracker. Experimental results demonstrate that the methods employed in the proposed tracking algorithm improve the robustness and accuracy. The tracker based on the proposed target tracking algorithm is better than other trackers in term of robustness and accuracy, and it still can meet the real-time requirement.

High-speed CMOS camera can capture high frame rate phenomena for a wide range of applications. However, most of the cameras currently in use are simply outputting pixel data, and cannot be adjusted in real time when the surrounding environment changes. The main idea of this paper is to develop a compact high-speed CMOS camera that can evaluate the image quality in real time while transmitting high-speed image data stably. The camera is based on the architecture of high-speed CMOS image sensor and FPGA (Field-Programmable Gate Array). The built-in sensor control, data transmission and image quality evaluation are all designed using Verilog HDL (Hardware Description Language). Our camera ensures that the processing unit at the back end of the vision system can receive high-quality images.

In this paper, the physical process of laser transmitting is modelled and analyzed, and this model is very helpful to analyze the requirements of different pixel structures on the frequency of laser emitter. In order to design the active quench circuit better, an accurate SPAD model is built with the Verilog-A description language. Then the circuit is presented and designed in 0.13um SiGe BiCMOS technology.

This paper proposes a fast auto frequency calibration (AFC) technique for wideband PLL with wide reference frequency range. The AFC circuit block adopts a proposed clock controller and a current-mode logic (CML) divider-by-2 divider to accelerate the AFC process without the penalty of AFC resolution. It also adopts the adjustable AFC counting period technique to speed up the AFC process at low reference frequency and to reduce AFC time variation within wide frequency range of reference clock. A 0.1~5 GHz ΔΣ fractional-N PLL with this AFC technique is designed and implemented in 65-nm CMOS process. The measurement results show that in the reference frequency range from 15 to 50 MHz, the AFC time varies only from 1.25 to 1.86 μs with AFC resolution range from 3 to 5 MHz.

In this paper, we presented a low frequency equalizing continuous time linear equalizer (LFEQ-CTLE). It can compensate not only the low-frequency channel loss but also the high-frequency channel loss. The LFEQ-CTLE adopts the degeneration R-C and negative feedback loop to generate the high frequency zero/pole and low frequency zero/pole. Based on Global Foundry $130nm$ SiGe BiCMOS process to achieve the overall design, the proposed CTLE compensates for the 17dB channel loss at Nyquist frequency for 50GBaud PAM4 data rates.

A 32×24 digital CMOS terahertz image sensor for 25 fps imaging at 860 GHz is presented. Pixel with DRC free structure is proposed and column parallel readout architecture is employed. The sensor array and the readout circuits are fully integrated into one single silicon chip in 180 nm CMOS process. Measured averaged room-temperature responsivity of single pixel is 1.28 kV/W at 860 GHz. The THz image sensor can operate up to 25 fps under continuous–wave illumination, and we acquired a video of a rotating blade chopping the backward wave oscillator (BWO) source beam, and the rotating blade can be clearly distinguished in the video.

In this paper, some key techniques of clock and data recovery (CDR) are proposed for PAM4 format high-speed communication, including effective voltage level transitions selection, sampling location optimization and threshold adjustment. Based on these techniques, two 50Gbps PAM4 CDR were designed and fabricated in 65nm and 40nm, respectively. The measurement results show $3.4\times10^{-9}$ BER of 65nm PAM4 CDR and $8\times10^{-9}$ BER of 40nm PAM4 CDR.

Terahertz imaging (THz) is promising in non-invasive detection, security check, material analysis et al. Current availabe detectors using microbolometer, Golery cells although proivide satisfactory responsility, they suffer from bulky volumn and are not suitable for large array. Emerging CMOS detectors, however, can offer intensive integration capability and potentials in further integrated with digital signal processors which makes Terahertz digital camera possible. This paper overview current research progress in CMOS THz detector and image sensor. Then we present the theory, design and implementation of CMOS THz detector with commercial CMOS technology,followed by recent experimental results t.

This paper presents an 18-to-23 GHz sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). It adopts the proposed injection-locked frequency divider aided adaptive injection timing alignment technique and uses a proposed (UP-DN) block to adjust the injection timing adaptively at output frequency higher than 20 GHz with low power consumption. A new pulse generator is proposed to relax the trade-off between the phase-noise suppression and the power consumption. The SIL-ADPLL is implemented in 65 nm CMOS process. Measurement results show that the covered frequency range is from 18 GHz to 23 GHz and the rms jitter integrated from 1 kHz to 100 MHz is 57.4 fs at 20 GHz output. The power consumption is 13.7 mW and the FoM is −253.5 dB. This SIL-ADPLL also shows robustness over temperature and supply variation.

A fully integrated low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end implemented in 180nm CMOS technology is demonstrated. The proposed double push-pull LNA collaborates with a current-mode down-converter to provide wideband low-noise reception, as well as the out-of-band blocker resilience. A sliding frequency synthesizer (FS) with low-frequency running VCO is employed to provide the local oscillation (LO) for both the RX and TX, with reduced power consumption. Measurement results show that, the RX reaches −102dBm sensitivity and dissipates 11mA power. The FS achieves −91dBc/Hz in-band phase noise with only 6.5mA DC power. The TX features +7.6dBm maximum output channel power, 4% EVM at the cost of 19.5mA power.

A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.