A 18-to-23 GHz −253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique

This paper presents an 18-to-23 GHz sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). It adopts the proposed injection-locked frequency divider aided adaptive injection timing alignment technique and uses a proposed (UP-DN) block to adjust the injection timing adaptively at output frequency higher than 20 GHz with low power consumption. A new pulse generator is proposed to relax the trade-off between the phase-noise suppression and the power consumption. The SIL-ADPLL is implemented in 65 nm CMOS process. Measurement results show that the covered frequency range is from 18 GHz to 23 GHz and the rms jitter integrated from 1 kHz to 100 MHz is 57.4 fs at 20 GHz output. The power consumption is 13.7 mW and the FoM is −253.5 dB. This SIL-ADPLL also shows robustness over temperature and supply variation.