Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS

As the optical module bandwidth fastly developing towards 400Gb/s, the single-channel data-rate reaches 56Gb/s. This leads to both architectural and bottom-level components change in the transceiver modules. More significant bandwidth shortage, nonlinearity, as well as noises are experienced by the optical devices. This paper reviews the challenges and key techniques in the design of laser and modulator drivers in CMOS. The solutions for 400G Ethernet are firstly introduced, which is then detailed in topology and core chips organization. Then, the circuits design for PAM4 modulation are discussed and demonstrated, respectively in a CMOS 50Gb/s VCSEL driver and a CMOS 50Gb/s Si-photonic MZM driver. The clock and data recovery (CDR) technique for direct PAM4 modulation is studied, which is then utilized to build the high integrity transmitters in CMOS.