54 results on '"Nakura, T"'
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2. Decoupling capacitance boosting for on-chip resonant supply noise reduction.
3. On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
4. An automatic phase control circuit with DLL-like architecture for phased array antenna systems.
5. Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
6. All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
7. Time-to-digital converter based on time difference amplifier with non-linearity calibration.
8. A toggle-type peak hold circuit for local power supply noise detection.
9. A robust pulse delay circuit utilizing a differential buffer ring.
10. A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS.
11. All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
12. Measurement of power supply noise tolerance of self-timed processor.
13. Ring oscillator based random number generator utilizing wake-up time uncertainty.
14. 647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA.
15. Throughput optimization by pipeline alignment of a Self Synchronous FPGA.
16. Cascaded Time Difference Amplifier using Differential Logic Delay Cell.
17. All digital wireless transceiver using modified BPSK and 2/3 sub-sampling technique.
18. SAT-based ATPG testing of inter- and intra-gate bridging faults.
19. Multi functional range finder employing a dual imager core on a single chip.
20. Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.
21. LAGS System Using Data/Instruction Grain Power Control.
22. Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector.
23. Feedforward active substrate noise cancelling technique using power supply di/dt detector.
24. Autonomous di/dt noise control scheme for margin aware operation.
25. Preliminary experiments for power supply noise reduction using stubs.
26. On-chip di/dt detector circuit for power supply line.
27. Power supply di/dt measurement using on-chip di/dt detector circuit.
28. Theoretical study of stubs for power line noise reduction [LSI applications].
29. A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM.
30. Low thermal-budget fabrication of sputtered-PZT capacitor on multilevel interconnects for embedded FeRAM.
31. A new application concept of transmission line arresters to 500-kV lines
32. A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology.
33. Tunneling spectroscopy of electronic structures of Bi/sub 2-x/Sn/sub x/Te/sub 3/.
34. A hydrogen barrier interlayer dielectric with a SiO/sub 2//SiON/SiO/sub 2/ stacked film for logic-embedded FeRAMs.
35. A 2.0Gbps multiplexer and a 2.7Gbps demultiplexer using 0.35µm SOI–CMOS technology.
36. Comparision of InGaAs absorptive grating structures in 1.55 /spl mu/m InGaAsP/InP strained MQW gain-coupled DFB lasers.
37. A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.
38. Feedforward active substrate noise cancelling technique using power supply di/dt detector
39. Theoretical study of stubs for power line noise reduction [LSI applications]
40. First observation of changing coupling coefficients in a gain-coupled DFB laser with absorptive grating by automatic parameter extraction from subthreshold spectra
41. A high-endurance 96-Kbit FeRAM embedded in a smart card LSI using Ir/IrO2/PZT(MOCVD)/Ir ferroelectric capacitors
42. Tunneling spectroscopy of electronic structures of Bi/sub 2-x/Sn/sub x/Te/sub 3/
43. Low thermal-budget fabrication of sputtered-PZT capacitor on multilevel interconnects for embedded FeRAM
44. Comparision of InGaAs absorptive grating structures in 1.55 μm InGaAsP/InP strained MQW gain-coupled DFB lasers
45. Autonomous di/dt noise control scheme for margin aware operation
46. All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
47. Cascaded time difference amplifier using differential logic delay cell.
48. Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks.
49. Design of Active Substrate Noise Canceller using Power Supply di/dt Detector.
50. Design and measurement of on-chip di/dt detector circuit for power supply line.
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