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The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

An on-chip measurement circuit that was specifically designed to capture the high-speed transient characteristics of photocurrent is employed to measure total-ionizing-dose (TID)-induced leakage from 10 keV X-rays. This circuit uses a photocurrent-controlled oscillator (PCO) to produce an analog frequency, which provides linearity comparable to traditional, off-chip methods of TID measurement. The circuit was fabricated in a sub-50 nm, fully depleted silicon-on-insulator (FD-SOI) technology. TID-induced leakage currents were measured using the circuit and results were compared to off-chip direct measurements from identical transistor arrays. Additionally, potential in situ applications of this circuit in conjunction with a TID-compensating back-gate biasing technique are explored. [ABSTRACT FROM AUTHOR]

A methodology for automating the identification of single-event transients (SETs) through ionizing radiation effects spectroscopy (IRES) and machine learning (ML) is provided. IRES enhances the identification of SETs through statistical analysis of waveform behavior, allowing for the capture of subtle circuit dynamics changes. Automated identification of SETs is facilitated by a k-nearest neighbors (k NNs) ML algorithm with IRES data. One-hundred thousand waveforms were measured from CMOS phase-locked loop (PLL) circuits irradiated at the Naval Research Laboratory’s two-photon absorption (TPA) laser facility. Known SET signatures were used to train various k NN models based on statistical features derived from several standard circuit metrics and eight moment-generating functions. Results show that SETs can be automatically identified by the k NN models, with several features resulting in greater than 98% correct identification of SETs. The tradeoffs in ML-based anomaly detection, based on the size of available training sets, choice in signal metric, and the number of included statistical moment-generating functions are discussed, along with opportunities for the future development of specific event-type classification, in situ measurement, and real-time classification of data. [ABSTRACT FROM AUTHOR]

Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ($V_{\mathrm {HOLD}}$) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat. [ABSTRACT FROM AUTHOR]

This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm partially depleted silicon-on-insulator technology node. Radiation-hardening techniques are integrated into a subsampling architecture for robust noise and radiation performance. Experimentally validated bias-dependent single-event models are used to characterize the radiation response, and the applicability of existing RHBD techniques to subsampling PLLs is examined. A significant vulnerability introduced in dual-loop architectures such as subsampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the subsampling architecture are leveraged to develop a high-performance RHBD PLL, maintaining performance specifications comparable to unhardened designs. [ABSTRACT FROM AUTHOR]

Ionizing radiation effects spectroscopy (IRES) for characterization of single-event transients (SETs) in space-deployed electronics is demonstrated. IRES enhances time-frequency spectroscopy techniques with statistical analysis, allowing for the capture of subtle changes in circuit dynamics. This is illustrated through the use of experimental data captured from two-photon absorption laser experiments on a phase-locked loop (PLL) designed and fabricated in a 130 nm CMOS technology, and further explained through the use of behavioral modeling of the PLL. The technique leverages the computational benefits of discrete windowed analysis, requiring as little as 0.2% of the data samples required in high-resolution discrete Fourier transform analysis while providing a statistical method for accurately estimating the SET characteristics. [ABSTRACT FROM AUTHOR]

At the 14-/16-nm FinFET technology node, experimental heavy-ion single-event upset (SEU) cross sections have been obtained for a D flip-flop (DFF) with variation in supply voltage over a wide range of particle linear energy transfer (LET). An empirical model for predicting the SEU cross section as a function of supply voltage based on experimental data has been developed and verified. The results are consistent with low-LET particle irradiation findings from previous works that have indicated a strong exponential increase in SEU cross section with supply voltage scaling for FinFET technologies. Furthermore, this paper reveals the impact of supply voltage variations on a sensitive area for high-LET particle irradiation. The increase in cross section from nominal (0.8 V) to a specific reduced supply voltage for high-LET particle irradiation is constant and has been observed through experimental results across the high-LET particle spectrum. The 3-D TCAD simulations are used to characterize sensitive area affecting high-LET supply voltage-dependent SEU cross sections in the FinFET technology. The developed model will allow circuit designers to predict changes in the SEU cross section due to supply voltage variation for the 14-/16-nm technology node without extensive testing. [ABSTRACT FROM AUTHOR]

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section. [ABSTRACT FROM AUTHOR]

A single-event-enabled compact model for bulk FinFET technologies has been developed and integrated with a process design kit (PDK) and an industry standard electronic design automation tool flow. The compact model incorporates transistor bias dependence and 3-D ion-incidence geometry awareness into the calculation of the single-event-generated current waveform. The model has been developed for performance from nominal supply circuit operation down to near-threshold voltage applications. The 3-D technology computer-aided design simulations have been used to calibrate the compact model transient current and voltage waveforms for single, hard-biased, devices and full 3-D logic gate response, e.g., inverter, NAND, and NOR. Single-event transient pulsewidth measurements, from heavy-ion testing over an angle of incidence and bias, on a technology characterization vehicle test chip fabricated at the 14-/16-nm bulk FinFET technology generation, have been used to validate the model response. The bulk FinFET single-event-enabled compact model, integrated with the PDK, enables a single-event analysis of circuit topologies for application in radiation environments while maintaining the standard integrated circuit design flow. [ABSTRACT FROM AUTHOR]

Ionizing radiation effects spectroscopy (IRES) for the analysis of total-ionizing dose (TID) degradation in radio frequency (RF) circuits is presented. IRES is used to image the change in the operating parameters with respect to TID and for classification of the circuit’s state based on image features. Measured data from two voltage-controlled oscillators (VCOs) and two phase-locked loops (PLLs) exposed to TID are used to demonstrate the utility of IRES for radiation effects analysis. The VCO and PLL circuits were designed in a 130-nm bulk CMOS technology. The circuits were irradiated up to 300 krad(SiO2) using an Aracor X-ray source, and IRES images were developed at various TID levels based on the instantaneous frequency of the output waveforms. The IRES technique is based upon RF-distinct native attribute fingerprinting for specific emitter identification using RF waveforms in communication systems. The technique employs statistical time–frequency analyses of various signal features. The resulting statistical measures are utilized to identify the operational state of the circuit (i.e., the TID level and bias voltage) using machine learning (ML) classification. While minor increases in operating frequency were measured with dose, the technique resulted in up to 100% prediction accuracy in the identification of the operational state following an ML training set of at least 50 measured samples. Moreover, the IRES technique enhances standard measurements by capturing global parametric shifts as well as transient variation. The technique, which exploits the subtle characteristics inherent in the waveforms, shows promise in radiation dosimetry applications as well as in-situ monitoring of device and circuit operational health. [ABSTRACT FROM AUTHOR]

Single-event transient (SET) data for the 14-/16-nm bulk finFET technology generation are presented and analyzed for variations in threshold voltage and number of fins in the transistor. The heavy-ion experimental data over a range of supply voltage allows for a comparison of the impact of drive current on the SET response of each transistor variant. The results show that the transistor drive current is a key factor for determining SET pulsewidths and cross sections for high linear energy transfer particle irradiation. Transistor variant data that result in matching transistor drive current show an excellent match for SET pulsewidths and cross sections. [ABSTRACT FROM AUTHOR]

As the minimum feature size on an integrated circuit continues to shrink aggressively toward deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a prominent concern. Various radiation-hardening-by-design (RHBD) techniques have been developed to achieve a satisfactory SE tolerance for flip-flop (FF) designs. To enable low supply voltage for ICs and overcome the “power wall,” the lowest power consumption of different RHBD techniques to meet the target SEU cross section is studied in this paper. A comparative analysis of three representative RHBD FFs and an unhardened FF fabricated at the 14-/16-nm bulk FinFET CMOS technology generation shows that at least $2\times $ power dissipation reduction may be achieved by using RHBD FFs at appropriate supply voltage without degrading SE tolerance. [ABSTRACT FROM AUTHOR]

A combinational logic family, termed dual-interlocked logic (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk FinFET technology generation and irradiated with heavy ions. Through both simulation and heavy-ion irradiation, DIL is shown to be robust to both single- and dual-node strikes. Results are compared to cascode voltage switch and standard logic to show the effectiveness of the logic family in mitigating SETs at the gate level. Three exemplar radiation-hardened-by-design synchronous systems using DIL, spatial triple modular redundancy (TMR), and temporal TMR are compared across area, power, delay, and hardness relative to an unhardened baseline system. The system utilizing DIL exhibits desirable tradeoffs compared to spatial and temporal TMRs. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) irradiation affects the single-event (SE) vulnerability of electronics by changing transistor leakage currents and/or effective threshold voltages ($\text{V}_{T}$). Characterization of SE response of flip-flop (FF) designs in a 14-/16-nm bulk FinFET technology after TID exposure has been carried out with alpha particle irradiations. Results show that SE cross section (SECS) first increase with total dose and then start to decrease after certain dose levels. These transition dose levels for SECS trend depend on supply voltage and FF design due to competing mechanisms associated with n-hit and p-hit SE transient (SET) pulse-widths and feedback loop delay. Similar trends were observed for SET-induced logic errors at high-frequency operations after TID exposure. [ABSTRACT FROM AUTHOR]

Muon-induced single-event upset cross sections are estimated for a 28-nm static random access memory (SRAM) using Monte Carlo simulations informed by ion test results. As an exercise in modeling with limited information, details of the 28-nm SRAM’s cell structure were not used (and not available) to inform choices of device model parameters such as sensitive volume dimensions and efficiencies. Instead, inferences were made based on heavy-ion and proton single event upset data. Volume dimensions were sufficiently small to resolve the charge collection profile resulting from highly localized low linear energy transfer particle strikes. Results are compared to muon experimental data taken at TRIUMF for validation. Rate predictions are made for the 28-nm SRAM using the calibrated model and compared to expected neutron rates. Muon-induced upset rates at sea level for both marginally reduced and significantly reduced electrical biases, as well as rates at 39 000 feet, are predicted to be significantly less than neutron rates in all these environments. This result is consistent with other authors’ efforts in similarly scaled bulk CMOS SRAMs, indicating that the modeling method used is reliable. [ABSTRACT FROM PUBLISHER]

A uniform technology-agnostic time-domain model for both linear and nonlinear all-digital phase-locked loops (ADPLLs) is presented. This time-domain model can be used for single-event upset (SEU)-induced perturbation time prediction and SEU sensitivity characterization of common ADPLL topologies. The model is validated against field-programmable gate array-based fault injection experiments and two photon absorption laser experimental results on three different types of designs. The model is applicable to rad-harden by design activities, failure mode predictions, and general ADPLL design optimizations. [ABSTRACT FROM PUBLISHER]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region. [ABSTRACT FROM PUBLISHER]

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node. [ABSTRACT FROM PUBLISHER]

Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced errors result in significant increases in single-event (SE) cross section for flip-flop (FF) designs. For FinFET transistors, the physical structure has changed significantly from planar structure. These changes have resulted in significantly less collected charge than that for planar technologies for the same ion strike, leading to shorter SET pulse generation. These results have necessitated the evaluation of SE cross section for FF designs as a function of frequency for accurate SE predictive capability. Circuit-level simulations and heavy-ion experiments were carried out to investigate frequency dependence of SE cross section for a hardened dual-interlocked cell-based FF design with different spacing options in a 16-nm bulk FinFET technology. [ABSTRACT FROM PUBLISHER]

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay. [ABSTRACT FROM PUBLISHER]

The single-event upset (SEU) vulnerability of common first- and second-order all-digital-phase-locked loops (ADPLLs) is investigated through field-programmable gate array-based fault injection experiments. SEUs in the highest order pole of the loop filter and fraction-based phase detectors (PDs) may result in the worst case error response, i.e., limit cycle errors, often requiring system restart. SEUs in integer-based linear PDs may result in loss-of-lock errors, while SEUs in bang-bang PDs only result in temporary-frequency errors. ADPLLs with the same frequency tuning range but fewer bits in the control word exhibit better overall SEU performance. [ABSTRACT FROM PUBLISHER]

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper. [ABSTRACT FROM PUBLISHER]

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification. [ABSTRACT FROM PUBLISHER]

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- V\textit {th} transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V\textit {th} , while the low- V\textit {th} transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( V\textit {gs}=V\textit {dd} ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- V\textit {th} transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics. [ABSTRACT FROM PUBLISHER]

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints. [ABSTRACT FROM PUBLISHER]

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs. [ABSTRACT FROM PUBLISHER]

A persistent loss-of-lock error was experimentally observed in a 20 nm charge-pump phase-locked loop (PLL). Through circuit modeling and simulation, the observed error was attributed to a non-recoverable off-state leakage increase resulted from two-photon absorption (TPA) laser-induced damage. The laser-induced damage is consistent with results from 28 nm bulk transistors. [ABSTRACT FROM PUBLISHER]

The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition. Single-event tolerant design guidelines for the digital loop filter are proposed and validated through FPGA-based fault injection experiments. [ABSTRACT FROM PUBLISHER]

Flip-flop soft errors caused due to direct strikes on flip-flops as well as soft errors caused due to latched transients from combinational logic show frequency dependence. This frequency dependence in the case of high-speed sequential circuits can derate the soft error rate by as much as 5X. Circuit variables, such as voltage, frequency, logic delay, as well as environmental factors, such as particle type and linear energy transfer that affect the frequency dependence are studied. Heavy-ion irradiation of 28-nm sequential circuits shows that the cross-section decreases with frequency for low-LET particles and increases with frequency for higher-LET particles. Competing trends involving combinational logic and flip-flops are shown to be the reason. The voltage dependence of this trend is evaluated. The key insight that emerges from this work is that at sufficiently high frequencies, the cross-section of certain sequential circuits can be lower than that at lower frequencies. Similarly, lowering voltage may not always result in increased soft error rate at certain frequencies. [ABSTRACT FROM PUBLISHER]