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In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.

We will present our work on epitaxially grown III-V on silicon DFB laser arrays, including results of pure InP-based lasers emitting around 900nm and InGaAs-on-InP lasers emitting around 1300nm.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g m by 25% compared to InAs S/D. A g m of 1310 µS/µm with an SS sat of 82mV/dec is achieved for an L g =46nm device. At this L g , a record I on above 200µA/µm is obtained at I off of 100nA/µm and V ds =0.5V on a 300mm Si platform.

In the paper, we review our work on heterogeneous integration of InP photonic devices on silicon. We elaborate on two integration technologies that have been widely explored in the Photonics Research group, i.e. the relatively mature adhesive bonding based integration scheme and a newly demonstrated buffer-less epitaxial growth approach. Based on these techniques, we describe a broad range of photonic devices including mode-locked lasers, high speed directly modulated distributed feedback lasers, electro-absorption modulators, photodetectors, super-luminescent light emitting diodes, etc.

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

In this paper we show how new materials such as InP epitaxially grown on silicon, graphene and ferroelectric materials with strong electro-optic coefficient can be integrated with silicon waveguides and enhance the functionality of the silicon photonics platform.

Optical interconnects require efficient and flexible optical sources. This paper presents results on two technology platforms being developed for realizing these. Integration using wafer bonding technologies is well established now and the focus is on new device types including tunable lasers, multi-wavelength lasers and switching. As an alternative, we also started work on monolithic integration using heteroepitaxy directly on silicon. We here report recent results on low threshold nanowire lasers.

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, L g of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Band-to-band tunneling (BTBT) in bulk group IV and III-V semiconductors is well known [1-2], but BTBT to confined layers is more difficult to calibrate experimentally. The latter occurs in most tunnel-FETs (TFET) and in particular in the promising line-TFETs [3,4]. It is predicted that field-induced quantum confinement (FIQC) and changing density of states near the semiconductor/oxide interface negatively impact the BTBT generation rate [5]. In order to gain insight while avoiding complicated TFET fabrication and analysis, we propose and demonstrate the BTBT MOS-capacitor (MOS-CAP) to characterize the onset and rate of BTBT perpendicular to the gate.

First-principles investigations are used to study the formation of defects in III-V fins grown using the aspect ratio trapping technique. We show that, during the growth of the III-V, the formation of intermediate chemical states with the precursors leads to the creation of in-diffused Mg/Zn and Al 2 O 3 sub-oxide. Our prediction is consistent with the experimental observations. These defect formations could be at the origin of the degradation of the electrical reliability of III-V fin-shaped field-effect transistors and the cause of the increasing difficulties met in the fabrication of III-V fin.

This paper gives an overview of measurement techniques to assess border traps in high-k gate dielectrics deposited on high-mobility channel materials, like Ge and InGaAs. A short description of the measurement principle and bulk oxide trap analysis will be provided for three methods, namely, low-frequency (1/f) noise, Deep-Level Transient Spectroscopy and AC transconductance dispersion. Practical application is illustrated either on metal-oxide-semiconductor capacitors or transistors, depending on the technique.

Silicon photonics holds the promise of converging electronics and photonics. The key component, a low-cost high-performance laser, is still missing however within this platform. Although novel solutions have been proposed to increase the light emission directly from silicon (or Ge), compared with their III-V counterparts, these solutions are still in their infancy. Recently, the epitaxial growth of III-Vs on silicon regained a wide interest. III-V nanowire growth has been widely investigated. However, most of the III-V nanowire lasers on silicon require a complex cleaving and transfer process, which make these devices not suitable for dense integration. In addition, the large cavity dimensions along the nanowire axis (several microns) hinder dense integration. Here, we present the first room-temperature operation of an ultra-short InP nanowire laser that is epitaxially grown on an exactly [001] oriented silicon substrate. The sub-micron sized laser cavity largely enhances the interaction of the lasing mode with the gain medium, and a large spontaneous emission factor has been obtained.

We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Moore's Law describes the scaling of Si-based CMOS technology in terms of performance, power consumption, area and cost. As we have reached the physical limits of scaling Si channels, alternative materials with higher carrier mobility such as Ge and IIIV compound semiconductors are in order. This paper reviews some of imec's work on introducing In 0.53 Ga 0.47 As in a manufacturable and integratable way into mainstream Si-based CMOS technology. Several major issues are known: dielectric/IIIV interface passivation, mismatch of lattice and crystal structure between IIIV and Si, small bandgap leading to enhanced leakage,… We will discuss mainly the epitaxial growth aspects and the integration of IIIV materials in Si MOSFET devices, and point out some more unexpected materials and device issues.

Interest in Sn-based semiconductors largely increased during the last decade. If doubts remained in the early 2000's on the hypothetical use of (Si)GeSn epitaxial layers in advanced technologies (mainly due to the low Sn solubility in Si and Ge and the associated reduced thermal stability of those alloys), recent publications from various groups provide today a much better feeling on the potential of those materials. First of all, the growth of GeSn layers with high Sn content was demonstrated by different techniques overruling their apparent thermodynamics limitations. Next, and especially very recently, Sn-based devices are showing up: GeSn MOSCAP, GeSn pMOSFET or GeSn photodetectors [9] for instance. This paper reviews the deposition techniques and different integration schemes to implement GeSn in various technologies and highlights the potential benefits in logic and photonics devices.

As CMOS continues to approach the physical limits of silicon, interest has greatly increased in the use of high mobility alternatives for devices beyond the 14 nm technology node. By virtue of their high electron and hole mobilities, InGaAs and Ge respectively have emerged as the most promising candidates for n- and p-MOS but the co-integration of these materials on the same Si wafer remains a significant challenge for the introduction of a III-V/Ge CMOS solution. A promising option for integrating Ge and III-V materials on the same Si wafer is the use of the aspect-ratio-trapping (ART) technique. In this paper we present the results of using the ART technique to fabricate InGaAs based devices on 200mm Si wafers and to create virtual III-V/Ge substrates. While further development will be needed to integrate InGaAs and Ge devices on the same wafer these results create a path for the realization of a high-mobility CMOS solution

High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. In these new material systems and devices various electrically active defects are present at or close to the interface between the high-k dielectric and the alternative channel material which are a major concern for both the performance and the reliability of these new devices.

Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.

Germanium has emerged as an exciting alternative material for high-performance scaled CMOS, however not without difficulties. After a review of the state-of-the-art, mainly focusing on two techniques to passivate the channel/dielectric interface, we analyze the strengths (carrier mobility, band gap), and weaknesses (n-type doping, lattice mismatch and BTBT leakage) of Ge for MOSFETs. We also identify some opportunities and the most important threats for the future of germanium.

The use of Ge and III/V materials for future CMOS applications is investigated. Good passivation of the Ge surface can be obtained by either GeO 2 or Si passivation. Short channel Ge pMOS devices with low EOT are fabricated using Si passivation at 350 and 500°C. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are discussed.

The introduction of high mobility channel materials together with new device structures with improved subthreshold slope provides a pathway into continuing the performance scaling of CMOS technology beyond the classical Si roadmap. The combination of Ge pMOS devices with nMOS devices made on very high electron mobility III/V compounds such as InGaAs can be achieved by selective growth on a Si-wafer, The key challenge towards achieving excellent device performance is the electrical passivation of the interface between the high-x dielectric and the alternative channel materials.