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The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.

We present a new mixed-mode stress technique for assessing the complete mixed-mode damage spectrum of SiGe HBTs, and apply it to three SiGe technology generations. We are able to distinguish four distinct regions of cross-generational SiGe HBT stress-response, identify a new low-current density damage mechanism in 3rd generation devices, and observe for the first time a novel stress-induced annealing phenomenon. The implications of these observations are addressed.

We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated.

We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications

This paper explores SiGe profile optimization for improved cryogenic operation at high injection. Through analyzing distributive transit time profiles, the bottle neck limiting high injection fT is identified and then eliminated in an optimized profile design. The fabricated profile indeed shows considerably improved fT and beta at high injection

A comprehensive investigation of reliability issues in both fully-depleted and partially-depleted SiGe HBTs-on-SOI is presented. The devices were subjected to "mixed-mode" stress at 300 K and at 77 K, and we have analyzed the changes in base current IB, collector resistance RC, M-1, and AC performance. A comparison of mixed-mode stress to conventional reverse EB bias stress is also made, and significant differences are observed. The thermal resistance Rth of the devices is extracted over the 50 K ? 300 K range.

0C (43K) in the polar shadows), makes operation of the electronics sub-systems on the surface of the Moon exceptionally difficult, but is nonetheless required for the envisioned complex suite of electronics systems used in sensing, actuation, and control of robotic systems. Such applications are typically fairly low frequency in nature (e.g., < 100 MHz), hence not requiring the most aggressively scaled CMOS technology; however, a full suite of mixed-signal circuit building blocks, and reliable operation of those circuits across extremely large variations in temperature (e.g., +120 to -230C) is needed. Adequate device reliability must clearly be achieved to accomplish this task. CMOS device degradation due to hot carriers effect (HCE) is known to be considerably worse at low temperatures [2]. Device lifetime data at cryogenic temperatures, and a solid understanding of the corresponding degradation mechanisms, are thus critical in this context of space electronics, and are addressed in this work. The Si CMOS devices investigated here are from an advanced 0.5µm SiGe BiCMOS technology, with a fixed channel width of 10.0 µm, and effective gate lengths ranging from 0.35 µm (minimum geometry), to 5.0 µm. The devices were characterized on a custom cryogenic probe system from 300K down to 43 K (-230 0 C). For brevity we will focus on the nFET data, since it represents the worst case in this technology. Fig. 1 and 2 shows typical I-V characteristics for the CMOS devices at different temperatures. The current drive capability increases significantly for the same bias conditions, as the temperature decreases. The nFET lifetime was inferred using stress-induced changes to the ID-VG characteristics. The lifetime τ is defined here as the inferred stress time for which a certain parameter of the ID-VG characteristics has shifted by a predefined amount (e.g., 10% degradation of gm). A typical lifetime assessment analysis using the ID-VG characteristics for a 1.0 µm nFET are shown in Fig. 3 and Fig. 4. The slope of 0.6 for the linear fitting in Fig. 4 suggests that interface state generation is responsible for the observed device degradation at the maximum substrate current (VG ≈ ½ VD); while that of 0.3 for the maximum gate current bias condition (VG = VD) suggests that oxide trapped charge dominates [3]. For the nFETs operating at 300K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias. There has been speculation that the worst case bias conditions for hot carrier degradation can, however, be a function of temperature [4]. It can be verified from Fig. 4 that for this technology, maximum substrate current is indeed the worst bias condition, at least down to 82K, and hence was the condition used here for device lifetime evaluation. The substrate current is comprised of the generated hot carriers, and is thus a good monitoring parameter for HCE in practical measurements. Fig. 5 and Fig. 6 show the effects of temperature and gate length on substrate current, respectively. It can be seen from Fig. 5 that the maximum substrate current under the same bias condition increases by 3x as temperature decreases from 300K to 43K; while Fig. 6 suggests that the maximum substrate current increases by more than 10x as L shrinks from 1.0 µm to 0.35 µm, and becomes negligible as L increases to 5.0 µm. This suggests that HCE is impacted more by device geometry than by the temperature. Fig. 7 shows the inferred lifetime at different drain bias’ at different temperatures. As seen in Fig. 7, τ decreases by ~10x as the temperature is reduced from 300K to 82K. Furthermore, τ differs by more than 100x between the 1.0 µm and 0.35/5 µm transistors, and hence the longer-channel devices are preferred for cryogenic applications of this technology Assuming fast interface trap generation dominates the HCE degradation, plotting τID versus ISUB/ID on a log-log scale should yield a straight line behavior [5]. The critical electron energy for generating an interface trap is calculated to be 3.9 eV from the slop of the line. Both the slope and the critical energy from Fig. 8 correlate well with literature data (2.9 and 3.7 eV in [5]), suggesting that interface state generation is the dominant limiting reliability factor at low temperatures.

A new negative differential resistance (NDR) effect is reported for the first time in cryogenically-operated SiGe HBTs. A physical explanation based on heterojunction barrier effect (HBE) is presented, and confirmed using calibrated 2-D TCAD simulations. The ac consequences of this NDR effect and the impact of technology scaling on the phenomenon are also addressed.

We assess SiGe HBTs for emerging mixed-signal cryogenic circuits designed to operate on the Moon without ambient heating or cooling (from +120C to as low as -230C), focusing of potential reliability issues. Comprehensive mixed-mode reliability stress data for these SiGe HBTs were measured from 300 K to 85 K. We extract the thermal resistance over temperature to evaluate the impact of the self-heating at low temperatures, explore the low-frequency noise performance at room temperature and cryogenic temperatures as a function of stress condition, and examine the impact of cooling on breakdown voltage and operating point instabilities for mixed-signal circuits.

The first results of the effects of mechanical planar biaxial tensile strain applied, post fabrication, to Si/SiGe HBT BiCMOS technology are reported in this work. Planar biaxial tensile strain was applied to the samples, which included both standard Si CMOS, SiGe HBT, and an epitaxial-base Si BJT control, for both first and second generation SiGe technologies. Device characterization was performed before and after strain, under identical conditions. At a strain level of 0.123%, increases in the saturation current as well as effective mobility are observed for the nFET. The Si BJT /SiGe HBT showed a consistent decrease in collector current and hence current gain after strain.

A robust, time-dependent stress methodology for investigating "mixed-mode" (simultaneous high J/sub C/ and high V/sub CB/) reliability degradation in advanced SiGe HBTs is introduced. We present comprehensive stress data on scaled 120 GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also employ calibrated MEDICI simulations using the hot carrier injection current technique to better understand the damage mechanisms, and conclude by assessing the impact of mixed-mode stress in aggressively scaled 200 GHz SiGe HBTs.