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In this study, the silicon-based nanostructures were prepared by using an electrospinning method and subsequent heat treatment process. The silane was coated on the surface of nanostructures make it superhydrophobic. Firstly, a precursor solution was prepared by dissolving an appropriate amount of Polyvinylpyrrolidone (PVP) and Tetraethylorthosilicate (TEOS) in ethanol and spun the nanostructures on the silicon wafer by using a single-syringe electrospinning. Secondly, the influence of heat treatment profile on morphology of electrospun nanostructures were explored in detail. Thirdly, silane dissolved in solution and coated on the nanostructures. This work studies the improvement of the superhydrophobic properties of the nanostructured surface through different high-temperature treatments. 600°C~800°C have different topography.

Because the e-book has rich application of education, and cloud technology can share educational resources, e-Books combined with cloud technology will be the trend in education. But teachers' personal characteristics, computer assisted learning experience, understand system little, without sufficiency training, access teaching materials and intellectual property rights, etc., will cause usage barriers which reduced usage intention. Therefore, this study developed a Cloud-based eBook, features are converting usage barriers solution into services. Teachers login account, will be able to share these cloud services by the internet. Through solving usage barriers, expected to enhance teachers' usage intention and teaching effective.

This paper presents the design of electrical interconnect for high-speed data transmission involving differential signal vias on printed circuit board (PCB). Between two channels of differential vias, with given intra pair via pitch and spacing from adjacent channel vias, there exists an offset angle where differential crosstalk is minimized. By studying single-ended terms of NEXT and FEXT relation in both time and frequency domain, it becomes clear that such phenomenon occurs once in every quadrant. The crosstalk reduction can be achieved without placing ground vias in between signal vias of two channels, giving more routing space in high-speed PCB designs.

Stress measurements in microelectronic packaging through the MOSFET devices have attracted great attentions because the measurement is in-situ and nondestructive. In this study, a new assembled methodology was designed and applied so that the calibration procedures on MOSFET stress sensors can be simpler and more accurate. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on linear relationships between drain current variation and the mechanical and/or thermal effects, and the results suggested that the MOSFET devices is a useful in-situ stress sensorsin electronic packaging. It is concluded that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

In this work, we studied the availability of p-type MOSFET with 1 mum channel width and 0.15 mum channel length as a stress sensor. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on a new measurement methodology, and linear relationships between drain current variation and stress and/or thermal effects were obtained. According to the measurement data, the extremely important thermal effect was also noted. It is concluded in this work that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

This work introduces the fringe RLGC (i.e., resistance, inductance, conductance, and capacitance) models to accurately compute the broadband S parameters for not only large power planes but also thin signal traces in multi-layered package and PCB environments. With comparable accuracy and 100/spl times/ faster than a 3D full-wave field solver, this technique enables ultra-fast design iterations to optimize the layouts for insertion and return losses, resonance frequencies, and placement of decoupling capacitors, etc.

In the paper we present a tour guide system, which brings the portable devices into museums to be your own expert guide. The purpose of the system is to construct a mobile learning environment with positioning technology and portable devices. People who are in this environment would obtain the detailed information, and even the history of the exhibit displayed in text, voice or video clips. Moreover, unequal explanations, mobile group learning, and learning activities management are provided in the proposed system.

This paper describes an RDRAM channel design with novel 32-bit RIMM/spl reg/ modules which deliver a data bandwidth of 4.8 GB/s at 600-MHz clock frequency. Only two RIMM modules are needed for the entire 32-bit, 2-channel design, reducing both the board space and manufacturing cost. Detailed physical architecture, design optimization, and modeling and simulation methodology are presented. Numerous simulations with multi-stage calibration are automated to ensure ample voltage and timing margins for a robust design.

This paper presents several methods that model a multi-bit data bus structure by a two-line equivalent. A rigorous approach using formal matrix reduction results in an accurate but asymmetric model which is inconvenient to use in simulating complex systems because the rest of the system needs be adjusted accordingly. Forcing the equivalent two-line model to be symmetric gives the advantage of applying the even- and odd-mode concept, but can lose accuracy in highly coupled lines. A novel approach is shown in this paper to include secondary coupling and achieve an equivalent, symmetric, and accurate two-line model.

As the clock speed increases and rise time decreases, an accurate I/O driver model is crucial for robust system designs. Due to the runtime limitations, a full-blown driver circuit model is impractical for those designs that require numerous simulation runs. Take the high-speed Rambus memory channel design as an example. Thousands of data read and data write simulations were performed with various patterns, configurations, and comer models. Many complex interconnect models are included in the simulation decks, in the form of frequency-dependent, lossy, and coupled transmission lines [1]. The only nonlinear model that is present is either the memory controller circuitry for data write or RDRAM driver circuitry for data read simulations. This paper describes a reduced, but equivalent, RDRAM driver model that significantly speeds up the simulation time for Rambus memory channel designs. The concept of using a reduced model in place of a full-circuit model is not new [2]. This paper, however, chooses a model that consists of a simple level-1 transistor in parallel with a voltage-controlled current source. A systematic approach is shown that curvefits the I-V curve by a level-1 transistor and matches the load line by a current source. The reduced model thus obtained results in time-domain waveforms that are nearly identical to the full-circuit's. Finally, it is noted that the same procedures can be applied to derive reduced models for many nonlinear circuits.

The wire-bond ball-grid-array (BGA) package is of interest because of its low cost and high pin counts. For better electrical performance, the coupling in the wire-bond regions needs to be contained. This paper shows a double-swizzle design that reduces coupling by ∼40% from a reference single-swizzle design. The smaller coupling was achieved through the proper assignment of ground wires. Test packages with shorted load were built, and the measurements were done by connecting either a vector network analyzer (VNA) or a time-domain reflectometer (TDR) to the balls of the package. The coupled models of bond wires, fanouts, traces, and plating stubs were then extracted from the measured data by a customized extractor. The extracted models gave some insights into the package. The attenuation was larger than expected. Some spikes in the measured S11 plots were attributed to the coupling. A package model without coupling would not be able to capture these spikes. Yet there were other spikes that were unexplained. They were finally tracked down to be caused by the Vdd plane and routing. Connecting decoupling capacitors between Vdd and ground balls moved the resonance spikes to higher frequencies. Shorting the Vdd and ground balls eliminated these mysterious spikes altogether.

This paper describes an innovative design and modeling methodology for development of a high performance memory bus with data signaling bandwidth of up to 1.6 gigabytes per second. Data signals operate at 800 megabits per second transfer rate. The clock frequency is 400 MHz and the signal edge transition time is 200 ps. Due to the extremely high frequencies involved, overall system electrical performance must be optimized. By following the methodology outlined in this paper, good correlation was obtained between simulated and measured results.

In this paper, we proposed a new algorithm based on Montgomery's algorithm to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced, the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6 /spl mu/m SPDM cell library. By our modified modular exponentiation algorithm, it takes about 1.5 n/sup 2/ clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125 Mhz, therefore the baud rate of our 512-bit RSA processor is about 164 k bits/sec.

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.

Besides reviewing the numerical techniques in computing resistance, inductance, and capacitance, this paper addresses the challenges to accurately model the deep-submicron on-chip interconnects. Deriving regression equations from numerous runs of Poisson field solvers, one can easily transfer the accuracy of physical simulation to the rule-based full-chip layout parasitic extractors. Such methodology, which was implemented in the program Raphael, can be extended to the PCB and other package applications, and help create rules for place-and-route.

Differential signaling is a popular choice for multi-gigabit digital applications such as FiberChannel, Infiniband, OIF, RapidIO, and XAUI. This is due to the fact that differential signaling has the ability to reject common mode noise such as cross talk, simultaneous switching noise, power supply and ground bounce noise. To support differential signaling, differential transmission lines are required. There are several ways of designing differential transmission lines on a conventional printed circuit board (PCB). These include microstrip line, edge coupled stripline, and broadside-coupled stripline. This paper describes a methodology for designing and verifying differential transmission lines on PCBs. The electrical performance of these three differential transmission lines is evaluated in both the frequency and time domain. The practical consideration of manufacturing variation is also examined. Finally, accurate HSPICE w-element models are generated for time domain transient simulations.

This paper shows a generalized optimizer that interacts with an external circuit simulator to extract frequency-dependent lossy coupled transmission line models from TDR or VNA measurements. The optimizer's architectural flow, and such concepts as global and local iterations, weighting function, time-windowing and piecewise-linear source models are mentioned. Several examples, including a complex BGA package model, are used to demonstrate its effectiveness in extracting model parameters and correlating waveforms.

This paper models arbitrary interconnect structures by frequency-dependent coupled transmission lines in cascade. By optimizing the input impedance of shorted structures, we show that the RLGC parameters can be extracted reliably from the vector network analyzer (VNA) measurements. The probes and lead-in traces are easily de-embedded. It is interesting to see that a complex 3D structure can sometimes be modeled by a simple transmission line.

To successfully design high-speed computers and networking equipment, it is necessary to model the interconnects (e.g. package, connector, etc.) and control signal integrity over a wide frequency range. The literature showed that lumped models were often extracted from measurements of both "open" and "short" test structures (Young and Sparkman, 1996), but there are several drawbacks. Not all test structures could be easily built. Capacitance, for example, was often measured without properly grounding the other signal conductors. A lumped model is also "narrow-band", in that it cannot easily account for the frequency dependent skin effect and dielectric loss. It is futile to derive lumped models at many frequencies because no time-domain circuit simulator can understand them. This paper presents a novel approach to extract accurate interconnect models from vector network analyzer (VNA) S-parameter measurements, using only one short test structure. The model is based on frequency-dependent coupled transmission lines in cascade. A transmission line can be considered to the most general circuit element in that it morphs into a single R, L, G, or C in the limiting case. A customized optimizer was developed to solve the circuit equations and derive RLGC matrices for HSPICE's W-element transmission line model. S11 and S21 values measured by VNA, and optimized BGA package models are presented. It is interesting to see that we can accurately model a complex BGA package's via, trace, and bond wire from DC to >2 GHz by a single section of transmission line.

Performance of a reliable storage subsystem for a centralized database system was studied by simulation. The reliable storage subsystem studied consists of three redundant disk units that are updated one at a time from a consistent database state to another consistent database state. Thus, even if a central processor and/or one disk unit fail simultaneously, at least one disk unit will contain a consistent database state. Redundant multiple disk units allow simultaneous processing of multiple read operations. Our simulation result shows that when all transactions are read-only transactions, the throughput of a three-unit system is 2.5 times higher than that of a single-unit system. On the other hand, redundant disk units slows down write operation because each disk unit must be updated for each virtual page updated. The major result in this paper shows that this adverse effect can be mitigated if updates of multiple transactions are merged and if an efficient disk scheduling policy (e.g., CSCAN) is employed. When the ratio of write operations to read operations is between 10 to 30%, the throughput of the three-unit system is still 89 to 144% higher than that of the single-unit system, which is not reliable. This result is significant when we consider that the performance of a reliable storage subsystem based on logging cannot exceed that of a single-unit storage subsystem.