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This paper presents a methodology for analysing two-photon absorption laser testing results in the frequency domain rather than with the classical mapping approach. We experimentally demonstrate, on a 28 nm device, the extraction of subwavelength dimensions from a noisy environment without requiring any synchronization between the test operations and the laser or the scan motion. A model of the experiment is then used to evaluate the impact of different parameters on the capabilities of the technique. [ABSTRACT FROM AUTHOR]

Highlights: [•] We investigate Single-Event Burn-out in SiC power diodes using two photon laser testing. [•] Two-photon absorption at blue wavelength can induce burn-out in SiC diodes. [•] A simple model of laser induced current leading to the failure mechanism is proposed. [Copyright &y& Elsevier]

Highlights: [•] We demonstrate the impact of NBTI on the Single-Event Upset threshold of a 65nm SRAM cell. [•] The SEU threshold measured by laser testing decreases over time after NBTI accelerated stress. [•] On the tested device, this effect seems to be a concern only for long-term space missions. [Copyright &y& Elsevier]

Abstract: This paper presents a detailed simulation-based analysis of the influence of the laser spot shape and size on the parametric and logical transient errors that can be injected into a digital device. The effect of the impact of a Gaussian laser beam is simulated at the electrical level for different pulse durations. Results illustrate the complex interaction between the electrical function and the laser perturbation, with potential implications for secure circuit design. [Copyright &y& Elsevier]

Abstract: This paper presents an improvement of the time resolution of the Photoelectric Laser Stimulation technique using the phase of a mode-locked laser as a reference to generate an electrical stimulus for the device under test. This synchronization system was applied to observe signal propagation in an 860 MHz ring oscillator. [Copyright &y& Elsevier]

This paper presents the numerical evaluation of different multiphotonic absorption mechanisms to be used for backside laser testing of single-event effects in GaN-on-Si HEMTs. The optical transmission through the complete stack of layers of three commercial references is calculated. Experimental results illustrating the possibility to use three-photon absorption for charge injection in the GaN layer are presented. The possible contribution of higher-order optical absorption in the buffer layers is discussed. • Wide Band Gap technologies such as GaN HEMTs have encountered significant interest for several applications • Mechanisms involved in Single event effects (SEE) on these devices need to be further understood • Laser testing for SEE characterization of commercial GaN devices presents a major interest [ABSTRACT FROM AUTHOR]

We calculate single event effect cross-section with a new general method based on the evaluation of the current collected by an electrode and the ability of the cell to dissipate the charge involved in the event. Basically, a part of the charge deposited by an ionizing particle is collected, and a part of this latest is dissipated during the transient. The approach allows explaining experimental cross section obtained for heavy ions irradiations. Moreover, the use of heavy ions experimental results allow predicting the single event crosses section for protons. [ABSTRACT FROM AUTHOR]

Abstract: Various optical defect localization techniques are applied on the same integrated circuits (IC). These circuits were previously stressed by Electro Static Discharges (ESD) to create defects. The results obtained by each technique were analyzed to determine the nature of the defects. The different data are compared to assess their sensitivity and to evaluate the contribution of each technique in a failure analysis flow. [Copyright &y& Elsevier]

Abstract: This paper presents the electrical model of a PMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures. It permits to simulate the effect of a continuous wave laser on a PMOS transistor by taking into account the laser’s parameters (i.e. spot size and location, or power) and the PMOS’ geometry and bias. It offers a significant gain of time by comparison with experiments and makes possible to build 3D photocurrent cartographies generated by the laser on the PMOS. [Copyright &y& Elsevier]

Abstract: This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064nm) on a 90nm technology metal–oxide–semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps. [Copyright &y& Elsevier]

Abstract: This paper describes a new technique that uses a 1064nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains. [Copyright &y& Elsevier]

Abstract: To determine the failing net out of a list of potential candidates provided by the ATPG diagnostic tool, probing techniques such as TRE or LVP are commonly used. To use these techniques, complex electrical setups using tester have to be implemented to control the failing net to its failing value. This paper present an alternative technique to check net integrity and to orient failure location based on optical techniques. Experimental results and simulation presented in this study demonstrate the relevance and the efficiency of this technique. [Copyright &y& Elsevier]

Abstract: Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented. [Copyright &y& Elsevier]

Abstract: The reconfigurability of SRAM-based FPGAs has also some drawbacks, especially when used in systems requiring a high level of safety and/or dependability. Dealing with single-event effects is an important issue in these systems. This paper presents a software tool to analyze a bit-stream and the functional effects of errors in it. Results of analyzes are presented, based on experiments using a laser platform to inject faults in the circuit. [Copyright &y& Elsevier]

Abstract: The failure signatures of a grounded-base NPN bipolar ESD protection under multiple TLP and HBM stresses are analyzed. For this particular device having a graded collector region, multiple TLP or HBM stresses result in different types of defects. OBIC techniques and TCAD simulations are used to thoroughly analyze the involved physical mechanisms. [Copyright &y& Elsevier]

This paper presents an experimental comparison of laser beam based techniques applied to a case study concerning ESD defect location. Thermal laser stimulation and non-biased optical beam induced current techniques are evaluated and discussed. Experimental results demonstrate the advantages and weak points of the two approaches. [Copyright &y& Elsevier]

A backside failure analysis method is presented. Single contact optical beam-induced current (SCOBIC) is detailed with a failure analysis approach. Numeric simulations have been performed in order to improve understanding of the observed responses. Optimization of the detection as well as a case study are presented. [Copyright &y& Elsevier]

Single-Event Latchup (SEL) is considered as a major reliability issue for the CMOS technology due to its capability of permanently damaging electronic components. In this work, the impact of temperature variation on the SEL mechanism is investigated. As the SEL sensitivity is influenced by design and environment parameters, the temperature variation is also evaluated along the variation of three parameters related to the geometry and to the design of the component: the doping profile, the anode to cathode spacing (A-C spacing) and the substrate and well taps placement. Moreover, the charge collection process has been analyzed. The goal was to verify whether the concept of critical charge, through studying the collected charge by the source implants, can be used for SEL, as it is used for upsets. 2D TCAD simulations have been performed, using an NPNP structure based on 65 nm CMOS inverter. From these simulations, we have analyzed the threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL. Moreover, charge collected has shown promising results about its usage for SEL. • SEL characterization shows a great thermal dependence with high temperature decreasing the robustness of the CMOS designs. • The adoption of design radiation hardening techniques is effective in reducing the sensitive to SEL but it exacerbates the thermal dependence. • SEL rate shows the same trend as the threshold LET. • The charge collected by the source terminal can be used in the SEL characterization at circuit level • When adopting the collected charge divided by the time interval in which it is collected, a better characterization can be achieved. [ABSTRACT FROM AUTHOR]

Hardware redundancy is a well-known fault tolerance technique used in safety- and mission-critical systems. However, the hardening efficiency of such techniques relies on the robustness of the majority voter circuitry. This summary provides the design exploration of majority voter architectures to be used in radiation environments such as in space missions. An application-specific Single-Event Transient (SET) characterization based on the signal probability is proposed to optimize the Triple-Modular Redundancy (TMR) block insertion methodologies. Results show that the SET cross-section of complex-gate architectures presents low input dependence while for the NOR/NAND based architectures a higher dependence is observed due to the logical masking effects. Additionally, different from the other architectures, the NAND voter has shown a reduction in the SET rate as the signal probability is increased. Considering the signal probability p = 0.1, p = 0.5 and p = 0.9, the best design for the two analyzed orbits is the NOR, CMOS1 and NAND voter, respectively. [ABSTRACT FROM AUTHOR]

Electronics are increasingly susceptible to energetic particle interactions within the silicon. In order to improve the circuit reliability under radiation effects, several hardening techniques have been adopted in the design flow of VLSI systems. This paper proposes a pin assignment optimization in logic gates to reduce the Single-Event Transient (SET) cross-section and improve the in-orbit soft-error rate. Signal probability propagation is used to assign the lowest probability to the most sensitive input combination of the circuit by rewiring or pin swapping. The cell optimization can reach up to 48% reduction on the soft-error rate. For the analyzed arithmetic benchmark circuits, an optimized cell netlist can achieve from 8% to 28% reduction on the SET cross-section and in-orbit soft-error rate at no cost in the circuit design area. Additionally, as the pin swapping is a layout-friendly technique, the optimization does not impact on the cell placement and it can be adopted along with other hardening techniques in the logic and physical synthesis. [ABSTRACT FROM AUTHOR]

Soft error mitigation schemes inherently lead to penalties in terms of area usage, power consumption and/or performance metrics. This work provides a radiation hardening efficiency analysis of two possible selective node hardening based on standard cells: Gate Sizing and Transistor Stacking. The impact on the Single-Event Transient (SET) cross-section, layout area and leakage current is discussed. The results indicate that both techniques provide the same area overhead and high efficiency for low particle linear energy transfer. Further, although transistor stacking exhibits lower static power consumption, gate sizing still presents the best trade-off between area, performance and reliability. However, the hardening efficiency of transistor stacking is strongly dependent on the input signal of the gate. Thus, according to the application, this technique can possibly outperform gate sizing. [ABSTRACT FROM AUTHOR]

This work presents an approximate triple modular redundancy (ATMR) method based on successive approximation and loop perforation. Successive approximation consists of loop-based algorithms that improve their output quality on every iteration execution. By manipulating the number of executed iterations, a designer can balance output quality and execution time performance. The proposed technique exploits this approximate computing paradigm combined with data size and precision reduction to minimize traditional triple modular redundancy (TMR) costs while maintaining a good fault masking capability. A number of ATMR configurations are presented and tested under laser fault injection to evaluate their fault masking capability. The benchmarks are implemented as embedded software in the ARM Cortex A9 processor of a Xilinx Zynq-7000 series board. The proposed technique was able to improve the execution time overhead with the usage of approximations, with an acceptable fault masking rate. [ABSTRACT FROM AUTHOR]