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• The impact higher temperatures are noticed by the increase of Ioff and the decrease of Ion, on stacked vertically nanowire devices. • The reduction of μ r reverberates on the I DS /(W/L) degradation with the increasing of temperature. • V GS , ZTC on vertically stacked nanowire devices are clearly visible until 550 K, for all devices, maintaining V GS around 0.9 V. • DIBL is more impacted for high temperatures and wider devices. This paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, I on, and I off. currents. [ABSTRACT FROM AUTHOR]

Abstract: Low-temperature electrical characteristics of n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15nm in width and 19nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope. [Copyright &y& Elsevier]

• The position of interface traps along the channel has been evaluated in Junciotnless transistors. • The effect of traps on the low frequency noise depends on the surface potential. • In JNTs, the surface potential varies along the channel with drain/gate biases. • JNTs low frequency noise is more sensitive to trap centers close to the source side. • The lower surface potential close to the source enables traps to be occupied for a longer time. Differently from inversion mode MOS transistors, Junctionless Nanowires surface potential presents a strong dependence on the gate and drain biases, when the devices are biased in partial depletion. For that reason, the position of interface trap centers along the channel could have a significant influence on the electrical characteristics of the devices. Therefore, this work has evaluated how the position of a single interface trap along the channel can affect the low-frequency noise response of Junctionless Nanowire Transistors. It has been shown that the trap centers closer to the source side of the devices are more likely to degrade the noise characteristics than those located closer to the drain, which has been attributed to the lower surface potential in this region, enabling traps to be at the same state (occupied or empty) for a longer time interval. [ABSTRACT FROM AUTHOR]

This work evaluates the operation of p-type Si 0.7 Ge 0.3 -On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor. [ABSTRACT FROM AUTHOR]

Highlights • A methodology is proposed to separate mobility of each level of stacked NW structure. • Lower low filed mobility is obtained for top GAA level comparing to Ω bottom NW. • Mobility varies with VB due to holes concentration reduction and displacement. • A linear behavior between mobility and back bias has been evidenced. • Mobility dependence on temperature remarkably varies with VB for Ω-NWs. Abstract This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I DS) varying the back gate bias (V B), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for V B influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V B through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V B for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V B and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels. [ABSTRACT FROM AUTHOR]

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (W FIN ) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on I ON /I OFF by reducing W FIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively. [ABSTRACT FROM AUTHOR]

• Charge Pumping in JNTs is analyzed through experimental data and numerical simulations. • The Charge Pumping current increases linearly with the trap density. • The dependence allows for the proposition of an interface traps extraction method. • The comparison between experimental and simulated results shows the applicability of the method. This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (N it). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for N it > 1 × 1011 cm−2. [ABSTRACT FROM AUTHOR]

• The low-frequency noise in nanowire type GAA MOSFETs was physically modeled. • The inversion carrier density was calculated according to the gate and drain bias. • The developed model can accurately LFN according to gate and drain voltages. • The model could help circuit designers to optimize noise performance. In this study, the bias dependence of low-frequency noise (LFN) in nanowire type gate-all-around (GAA) MOSFETs was physically modeled. In the model, the inversion carrier density distribution was considered based on the potential in the channel that changes according to the bias. The developed model was verified with measurement data of the fabricated device. The model could help circuit designers to optimize noise performance in analog/RF applications when designing integrated circuits using nanowire-type GAA MOSFETs. [ABSTRACT FROM AUTHOR]

Abstract: The influence of doping process in selective epitaxial growth of source/drain, for vertically aligned three-dimensional multi-channel field-effect transistors (MCFETs), is examined. We show that the electrical performance of short devices strongly depends on the optimization of source drain regions. In situ doped epitaxial process results in a significant reduction in the series resistance. A further improvement, for both n- and p-MCFETs, is obtained by combination in situ doping with ion implantation. The effective mobility, however, is degraded by additional Coulomb scattering due to dopant diffusion into the channel. The detailed mobility analysis reveals the possibility for future process optimization based on the tight control of the activation annealing step during the source/drain formation. [Copyright &y& Elsevier]

• This work studied the effects of the fin width variation on SOI Junctionless Nanowire Transistors (JNTs) from 300 K to 500 K. • The results show near ideal SS for all devices with temperature variation of 0.2 mV/dec.K. • The V TH results show temperature variation of 0.30–0.36 mV/K. • Wider JNTs show better carrier mobility at a higher temperature than narrow ones due to the impurity scattering. • Narrower JNTs show higher mobility degradation with higher temperature due to the phonon scattering. This work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300 K to 500 K. The effects of the temperature on the measured drain current and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope, and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones. [ABSTRACT FROM AUTHOR]

• The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for devices with different channel lengths and fin widths. • The temperature rise increases the current due to GIDL and its dependence on the device width. • For a fixed negative gate voltage the channel length reduction increases the GIDL current for nanowires independent of the temperature, except for devices suffering from threshold voltage roll-off due to short-channel effect. • Three-dimensional TCAD simulations showed that drain leakage is mainly composed of band-to-band tunneling rather than junction leakage, even at high temperatures. • The band-to-band generation rate intensity is larger in the bottom nanowire, with Ω-gate architecture than in the top GAA nanowire. • Band-to-band generation becomes higher as length is reduced and fin width is increased and is larger in the drain extension and gate overlap regions. • The temperature rise changes valence and conduction energy levels causing the reduction of the lateral distance between the two levels, favoring the transversal band-to-band tunneling. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling. [ABSTRACT FROM AUTHOR]

• Subthreshold operation of tri-gate junctionless transistors (JLTs) with various effective width (W eff) was investigated. • Physical operation mechanism on the subthreshold regime of JLTs was also discussed in detail. • The on current to off current ratio (I on /I off) and subthreshold swing (SS) of JLTs were varied dramatically as changing W eff. • Remained carriers at the bottom caused a higher off-current, a deviated shape of log 10 (n) derivatives. • In addition, a better immunity against short channel effects (SCEs) in JLTs was proven. Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (W eff) and compared to that of IM transistors. The on current to off current ratio (I on /I off) and subthreshold swing (SS) of JLTs were varied dramatically as changing W eff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction. [ABSTRACT FROM AUTHOR]

• Parameters extraction method based on drain current measurements is proposed. • Mobility degradation factors influence on series resistance extraction is analyzed. • Flatband voltage and low field mobility are also extracted. • Method accuracy is analyzed considering devices of different characteristics. • Method application is demonstrated in experimental devices. The aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices. [ABSTRACT FROM AUTHOR]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]

• The gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors at high temperatures of operation is experimentally assessed for the first time. • The temperature rise increases the current due to GIDL and its dependence on the device width. • Temperature rise increases band-to-band generation in the overlap region between the drain and the gate, causing a larger GIDL current. • Device width increase weakens coupling, allowing the region where band-to-band tunneling occurs to extend to the interior of the undoped body, contributing to the rise of GIDL. This paper presents an experimental assessment of gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors for different temperatures of operation, in the temperature range between 300 K and 580 K. The temperature rise increases the GIDL current and its dependence on the device width due to the increase of band-to-band generation with temperature and weakening of electrostatic coupling. [ABSTRACT FROM AUTHOR]

Operation mode dependent series resistance (R sd ) behavior of junctionless transistors (JLTs) has been discussed in detail. R sd was increased for decreasing gate bias in bulk conduction regime, while a constant value of R sd was found in accumulation operation mode. Those results were compared to conventional inversion-mode (IM) transistors, verified by 2D numerical simulation and temperature dependence of extracted R sd . This work provides key information for a better understanding of JLT operation affected by R sd effects with different state of conduction channel. [ABSTRACT FROM AUTHOR]

Transconductance (g m ) and its derivative (dg m /dV g ) of junctionless transistors (JLTs), considered as a possible candidate for future CMOS technology, show their unique operation properties such as bulk neutral and surface accumulation conduction. However, source/drain series resistance (R sd ) causes significant degradation of intrinsic g m and dg m /dV g behavior in JLTs. In this letter, the R sd effects on the operation of JLTs were investigated in detail and also verified with analytical modeling equations. This work provides helpful information for a better understanding of the operation mechanism of JLTs with de-embedded R sd effects. [ABSTRACT FROM AUTHOR]

This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated. [ABSTRACT FROM AUTHOR]

This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation. [ABSTRACT FROM AUTHOR]

In this work, the effect of high channel doping concentration and unique structure of junctionless transistors (JLTs) is investigated in the subthreshold conduction regime. Both experimental results and simulation work show that JLTs have reduced portion of the diffusion conduction and lower effective barrier height between source/drain and the silicon channel in subthreshold regime, compared to conventional inversion-mode (IM) transistors. Finally, it leads to a relatively large DIBL value in JLTs, owing to degraded gate controllability on channel region and strong drain bias effect. However, JLTs showed a better immunity against short channel effect in terms of degradation of the effective barrier height value. [ABSTRACT FROM AUTHOR]

Abstract: The performance of semiconductor devices can be linked to geometry and variations of the structure. For transistors in particular, the geometry of the gate stack is essential. In this work we investigate the gate stack of a tri-gate transistor using dual-axis electron tomography. This allows the reconstruction of all surfaces of the gate of the transistor with high resolution and measurement of the local thickness of the gate oxide. While previously, dual-axis electron tomography was employed for reducing missing wedge artifacts, our work demonstrates the potential of dual-axis tomography for improving the resolution of a tomographic reconstruction, even for structures not affected by missing wedge artifacts. By simulations and experiments we show the value of dual-axis tomography for characterization of nanoscale devices as an approach that requires no prior information and that can be easily extended even to more than two tilt axes. [Copyright &y& Elsevier]

[Display omitted] This work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low V DS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures. [ABSTRACT FROM AUTHOR]

Highlights: [•] The back bias effect on junctionless transistors (JLTs) has been investigated. [•] JLTs are more sensitive to back biasing compared to inversion-mode device. [•] The effective mobility of JLT is enhanced below flat band voltage by back bias. [•] The back bias effect in narrow JLTs is suppressed. [•] 2-D numerical simulation successfully reconstruct of the trend of back bias effects. [Copyright &y& Elsevier]

Abstract: Low-frequency (LF) noise characteristics of wide planar junctionless transistors (JLTs) are investigated. Interestingly, carrier number fluctuation is the main contributor to the LF noise behavior of JLT devices, even though their bulk conduction features are clearly proved by the extracted flat-band voltage (Vfb ). This is explained by the fact that mobile electrons in depletion, originating from the bulk neutral channel or source/drain regions, can interact with slow traps in the gate oxide, giving rise in return to fluctuations of the charge density in the bulk neutral channel. Similar values of trap density (Nt ) are extracted in JLT devices and inversion-mode (IM) t0072ansistors, which also supports that the LF noise of JLT is well explained by the carrier number fluctuation model. [Copyright &y& Elsevier]

Abstract: The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (W top_eff) was investigated, experimentally. As decreasing W top_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (C gc–Vg ), resulting in a noticeable change in the effective mobility (μ eff) behavior from that in wide JLT devices, an increase of the threshold voltage (V th), while the flat-band voltage (V fb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure. [Copyright &y& Elsevier]

Abstract: The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ 0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (V th) and subthreshold swing (S) of JLT devices was also discussed. [Copyright &y& Elsevier]

• NBTI in JNTs is analyzed through experimental data and numerical simulations. • The impacts of the temperature and the trap density on NBTI are evaluated. • The increase in the oxygen precursors density leads to the saturation in the NBTI. • Temperature rise increases the degradation of threshold voltage due to NBTI. This paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps. [ABSTRACT FROM AUTHOR]

• The device is composed of two stacked nanowire levels: omega-gate and a GAA. • The measurements were performed at room temperature and with grounded substrate. • The weak inversion region presents almost the same behavior with gm/IDS of 38 V-1. • The maximum A V was obtained for lower channel width and higher channel length devices. • Narrow and longer devices stacked nanowires present better distortion properties. This paper presents the fundamental analog figures of merit, such as the transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and harmonic distortion (or non-linearity), of n-type vertically stacked nanowires with variable fin width and channel length. To have a physical insight on the results, the basic electrical parameters such as threshold voltage, subthreshold slope and low field electron mobility of the analyzed transistors were also studied. The studied analog parameters are presented in function of the transconductance over drain current, to allow for the comparison at the same inversion level. [ABSTRACT FROM AUTHOR]

Highlights: [•] A new parameter extraction method for junctionless transistors (JLTs) is reported. [•] Bulk channel mobility (μbulk ) in JLTs was extracted by the new method. [•] The new method also extracted the flat-band voltage (Vfb ) of JLTs, simultaneously. [•] 2D numerical simulation results confirm the validity of the new method. [•] Newly defined Maserjian’s-like function for gm of JLTs also proves its validity. [ABSTRACT FROM AUTHOR]