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[Display omitted] • Strain modulation mechanism on two-dimensional Te transistor was investigated. • Tensile/compressive strains to Te were relaxed by interfacial/stacked layer. • Synergistic effects of strain and crystallinity engineering were proposed. • Te transistor showed enhanced property with a high mobility of 12.05 cm2/V·s. • Te transistor exhibited excellent stability under long-term and PBS/NBS tests. Two-dimensional p-type material, tellurium (Te), has been of particular interest owing to its extraordinary electronic, optoelectronic, and thermoelectric properties. Here, we report a promising strategy to demonstrate enhanced performance Te transistor via strain modulation effect. The compressive and tensile strains were induced to the room-temperature-sputtered Te channel layer by stacking with various metal interfacial layers, followed by the strain relaxation and deoxidization effects caused by the deposition of the aluminum oxide via atomic layer deposition process. The strain engineering mechanism was comprehensively investigated by various characterizations, and both strain modulation and deoxidization-assisted crystallinity improvement were shown to synergistically enhance the charge transport of Te transistor. As a result, the improvement in the device performance with uniformity was clearly achieved, demonstrating the carrier mobility of 12.05 cm2/V·s, the threshold voltage of 0.09 V, and the subthreshold swing of 4.34 V/decade. This further results in the stable long-term operation over 28 days and excellent electrical stability under harsh negative and positive biasing conditions. Thus, this study presents a novel strategy of strain modulation for improving the performance of Te transistor, which has great potentials for complementary-metal–oxide–semiconductor logic circuits. [ABSTRACT FROM AUTHOR]

Abstract Carbon nanotube field effect transistors (CNTFETs) have gained remarkable attention in modern fields, as one of the promising candidates for replacing conventional MOSFETs technology at the end of the roadmap. In this regard, this article presents high-performance complementary logic gates based on ballistic gate-all-around CNTFETs utilizing a novel improved analytical model. This is done by considering the effects of carrier density, quantum capacitance, and the number of channels, which are highly suitable for logic applications. For this purpose, the polarities of CNTFETs are switched between n- and p-type by harnessing its geometrical properties (i.e. the dielectric materials). In the present paper the semi-analytical method is utilized to design complementary logic gates including inverter, AND, and XOR. To benchmark the structure, the main parameters including propagation delay, power delay product, noise margin, and static and dynamic power consumptions are calculated. Then appropriate values are achieved and then used in a simple half adder. It is shown that by applying a small external voltage in the order of 0.8′ V, the enhanced design metrics including static and dynamic powers can be achieved as P s = 25.12 pW, and P d = 40.62 nW, respectively. To verify the obtained results, they are compared with those of numerical and experimental models. Our results highlight the use of complementary gate-all-around CNTFET transistors as a promising platform for computing applications. Graphical abstract Image 1 Highlights • High-performance logic gates based on ballistic CNTFETs are presented. • The effects of the geometrical and physical parameters are considered. • By applying a small voltage of 0.8 V the enhanced design are achievable. • Low power consumptions are obtained as Ps = 25.12 pW, and Pd = 40.62 nW, respectively. • This provides a path for development of CNTFETs for computing applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology. [ABSTRACT FROM AUTHOR]

The design of CMOS circuits using nanoscale MOSFET has become very difficult nowadays as device modeling faces new challenges such as short channel effects and mobility degradation. Gate engineering and channel engineering reduces these challenges and improves the mobility of the carriers, resulting in improved characteristics such as drain current and transconductance. In this review paper, the effect of gate and channel engineering on the characteristics (both D.C and high frequency (a.c)) of multigate MOSFETs have been investigated and presented. [ABSTRACT FROM AUTHOR]

This paper presents a detailed investigation of the static and Mixed − Mode analysis of the accumulation-mode cylindrical gate all around (AM-CGAA) MOSFET. Consequently, the work extends to the design and analysis of the inverter characteristics like noise margin (NM), effect of voltage scaling and transient response, etc. using the proposed device. Accumulation-mode devices are an alternative to conventional MOSFETs that do not require high cost ultrafast annealing technique for fabrication of smaller length devices. Hence, we prefer to demonstrate the short channel effects (SCEs) and DC characteristics of both n- and p-type AM-CGAA devices at different channel lengths. Further the action of inverter has been systematically explored using the complementary device architecture. The switching and transient characteristics of the inverter is analyzed and compared with experimental data reported in literature. Noise margin and delay performances have also been demonstrated which are found to be in good agreement with the information available in the literature for nano-scale devices. Moreover, the proposed device shows better on/off ratio, near to ideal sub-threshold slope (SS), low drain induced barrier lowering (DIBL) value and acceptable CMOS functionalities. [ABSTRACT FROM AUTHOR]

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches. [ABSTRACT FROM AUTHOR]

It is demonstrated that nanoprobing technique is superior in localizing silicide defect rapidly in metal-oxide-semiconductor field-effect transistor (MOSFET). Cobalt silicide (CoSi 2) as an interfacial material below tungsten contact plug, various types of defects about CoSi 2 often cause leakage current in MOSFET, so close studies of problematic silicide is significant regarding MOSFET reliability enhancement. When one MOSFET in a combinational logic circuit is suspected of anomaly, because this kind of circuit is composed of several devices which are sometimes arranged in an active area (AA) of unique geometric shape, it is impossible to collect MOSFET characteristic correctly based on regular nanoprobing flow since conventional method hits limit for combined circuits measurement. Such circumstance almost impedes failure analysis (FA) in device level. Nevertheless, relying on our alternative strategy of multi-probe configuration, a novel nanoprobing analysis flow is adopted for device examination. It is shown that exact I-V characteristic of failed device can be captured by proposed workflow. Following I-V curve analysis further reveals an evident electrical signature of abnormal abrupt junction. It corresponds to an active area shorting with its surrounding nwell region. In addition, sophisticated leakage current behaviors are exhaustively interpreted by simplified models. Eventually, we confirmed CoSi 2 encroachment from the active area into nwell by the means of transmission electron microscopy (TEM) analysis. This paper presents an effective analysis to identify leaky junction of MOSFET in logic circuit that is rarely reported before. Furthermore, our exploration exhibits impressive flexibility of nanoprobing analysis in terms of localizing unusual silicide defect, so nanoprobe analysis is clearly an attractive option to optimize MOSFET manufacturing. • Propose a novel nanoprobing workflow to identify minute silicide encroachment into well of MOSFET. • Sophisticated leakage current behaviors are exhaustively interpreted by simplified models. • Demonstrate the merit of multi-probe configuration regarding analysis of faulty combinational logic circuit. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the high series resistance associated to the source and drain extensions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. In the present paper, a numerical investigation for the drain current and small signal characteristics is conducted for the DGJ MOSFET by including highly doped extension regions. The proposed approach, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current, small signal parameters, analog/RF behavior and linearity of DGJ MOSFET for high performance analog applications. In this context, I – V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics. [ABSTRACT FROM AUTHOR]

In this study, the properties of dielectric traps by the impact of Fluorine (F) implantation on 1/ f noise and the random telegraph noise (RTN) of high-k/metal gate (HK/MG) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) were investigated. The incorporation of F has been identified as an effective method to passivate oxygen vacancies, defect sites, and reduce the gate leakage current in pMOSFETs. Compared with a control device, the F-implanted HK/MG devices show that the trap positions were closer to the SiO 2 interfacial layer (IL)/Si channel. Furthermore, we found that F implantation could result in a smaller tunneling attenuation length ( λ ) and smaller slow oxide interface trap density ( N t ). [ABSTRACT FROM AUTHOR]

The scaling of MOSFET transistors makes the use of new device geometries, such as multigate FETs, a need to solve the limitations of the conventional bulk technology. In this context we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. The modeling of rounded corners in GAA and FinFET devices is imperative because there are no perfectly square corners in the cross-section of real devices. In this model the 2D inversion charge distribution function (ICDF) is described analytically for devices of different sizes and for different operation regimes. The model reproduces accurately simulated data obtained with a state-of-the-art simulator that solves self-consistently the Poisson and Schrödinger equations in the devices under consideration. The analytical ICDF is used to better understand the device physics and to calculate the inversion charge centroid and the gate-to-channel capacitance for different device geometries and biases for modeling purposes. [ABSTRACT FROM AUTHOR]

In this work, an analytical model for the subthreshold swing of double gate and cylindrical nanowire MOSFETs is proposed. Using the Voltage Doping Transform, it is shown that a one-dimensional potential model is sufficient to obtain a high accuracy, provided that an effective oxide thickness is used. The validity of this model is then confirmed with TCAD simulations. Finally, the impact of quantum effects is discussed. Based on Density-Gradient simulations of Si and GaAs MOSFETs, it is shown that the model is still valid when quantum effects are accounted for. [ABSTRACT FROM AUTHOR]

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental I d – V g measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the scaling and carrier transport behavior of sub-100 nm In 0.7 Ga 0.3 As buried-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al 2 O 3 as gate dielectric. The device combines a 3-nm Al 2 O 3 layer grown by atomic-layer-deposition (ALD) and a 13-nm In 0.52 Al 0.48 As insulator grown by molecular-beam-epitaxy (MBE). Our long channel device with L g = 200 nm exhibits excellent subthreshold characteristics, such as subthreshold-swing ( S ) of 68 mV/decade at V DS = 0.5 V, indicating a very good interface quality between Al 2 O 3 and In 0.52 Al 0.48 As. In addition, a short-channel device with L g = 60 nm maintains electrostatic integrity of the device, such as subthreshold-swing ( S ) = 90 mV/decade and drain-induced-barrier-lowering (DIBL) = 100 mV/V at V DS = 0.5 V. We show well-behaved electrostatic scaling behavior that follows a modified FD-SOI MOSFET model. Our experimental and theoretical research suggest that further device optimization in the form of a self-aligned contact structure and aggressive EOT scaling would lead to high-performance III–V MOSFETs for multiple types of applications. [ABSTRACT FROM AUTHOR]

In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance ( C f ) separated from gate-to-contact capacitance ( C co ), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as C f and C co of MOSFET. To separate C f and C co , novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of C f with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent C f in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node. [ABSTRACT FROM AUTHOR]

Highlights: [•] Electrical characteristics of UTB (46nm) and NSD (1.6nm) SOI-MOSFETs are compared. [•] Initial SOI channel is thinned down to 1.6nm using a recessed-gate process. [•] Drain current values were found surprisingly different by 3 orders of magnitude. [•] Two Y-function-based extraction methods of series resistance are used and compared. [•] Article’s novelty is that our methods are based on I DS − V GS measured for several V DS. [ABSTRACT FROM AUTHOR]

Highlights: [•] We simulated GIDL current when an oxide trap is neutral or charged with an electron. [•] RTN in GIDL current depends on trap’s position at overlapped region. [•] We built a contour of amplitudes ΔI/I to extract the trap’s position. [•] Dependence of RTN in GIDL current on drain to gate voltage was explained. [ABSTRACT FROM AUTHOR]

Highlights: [•] A design methodology of silicon nanowire MOSFETs is presented. [•] An analytical gate capacitance model for for sub-22 nm is proposed. [•] The wire diameter does not follow the common stringent scaling rule. [•] Optimal diameter design is shown to achieve good performance. [ABSTRACT FROM AUTHOR]

Highlights: [•] A 2-D semi-analytical model of MOST parasitic capacitance. [•] Using semi-analytical method and eigenfunction expansion method. [•] The model provides a good calculation method for parasitic capacitances. [•] The model can be used in circuit simulation and device design directly. [ABSTRACT FROM AUTHOR]

Abstract: This paper reports on the effects of the Halo structure variations on threshold voltage (V th) in a 22nm gate length high-k/metal gate planar NMOS transistor. Since the V th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO2 dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L9 array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V th. The results show that the V th values have least variance and the mean value can be adjusted to 0.289V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors. [Copyright &y& Elsevier]

Highlights: [•] Relation between γ and SS in thin BOX tri-gate nanowire MOSFET was studied. [•] Lg scaling increased both SS and γ. [•] Reduction of W decreased both γ and SS resulting in trade-off relation. [•] Reduction of H is effective to achieve large γ and small SS. [ABSTRACT FROM AUTHOR]

Highlights: [•] UTBOX nMOSFEts with different spacer lengths and HDD tilt-implantation are studied. [•] Better performance is achieved for longer spacer length device (L UL =20nm). [•] GIDL and the short channel effects are reduced in extensionless structures. [•] Device with L UL =10nm or tilt-implantation shows strong lat. diffusion and worse behavior. [•] Longer spacer length devices are more immunity to the temperature influence. [ABSTRACT FROM AUTHOR]

Highlights: [•] Electrical characteristics of UTB (46nm) and NSB (1.6nm) SOI-MOSFETs are compared. [•] Initial SOI channel is thinned down to 1.6nm using a recessed-gate process. [•] Drain current values were found surprisingly different by 3 orders of magnitude. [•] Such a huge contrast was not found coherent with the literature. [•] We built a useful model approach to interpret NSB anomalous electrical behavior. [ABSTRACT FROM AUTHOR]

Highlights: [•] We model the effects of an oxide breakdown on the transistor behaviour. [•] We consider the potentiometer model. [•] We show how the relevant feature that characterize the dielectric breakdown affect the transistor’s transconductances. [Copyright &y& Elsevier]

Highlights: [•] The intrinsic parameter fluctuation is studied for the 16-nm-gate TiN/HfO2 bulk FinFETs. [•] The fluctuation includes the random discrete dopant, the random interface trap, and the random work function, simultaneously. [•] The full 3D simulated threshold voltage fluctuation is 26.2mV for the N-type bulk FinFET. [•] The statistical sum of these fluctuations is 9.5% overestimation because independence assumption on these random variables is invalid. [•] Compared with the planar MOSFET, more than 50% reduction on the threshold voltage fluctuation is estimated. [Copyright &y& Elsevier]

Highlights: [•] We evaluate the hot carrier degradation mechanisms for n-channel LDMOS transistor with STI based structures. [•] The slope of I D,lin degradation indicates the different degradation mechanism under various bias stress. [•] The location of peak impact ionization differs at various V GS stress but consistent at various V DS stress. [•] The degradation mechanism is highly dependent on the stress voltage at the gate (V GS). [•] The V DS is found as an accelerating factor for the hot carrier stress test. [Copyright &y& Elsevier]

Highlights: [•] We integrated a gate-last on high-k first on planar fully depleted SOI MOSFETs. [•] pMOSFETs reach a low threshold voltage of V Tp =−0.2V. [•] Gate-last pMOSFETS present one decade gate current gain compared to gate first ones. [•] The use of a TiN MOCVD capping decreases the EWF by 0.2eV and degrades the reliability compared to TiN ALD. [•] EOT down to 0.8nm with midgap TaN are obtained on HfO2 in a high-k last integration. [Copyright &y& Elsevier]

Abstract: The Ge impact on the threshold voltage (VT) and the flat band voltage (VFB) of SiGe pMOSFETs is evaluated through a comparison of experiments and simulations with various SiGe thicknesses and Ge contents. Increasing Ge content shifts linearly (VT–VFB) in full agreement with Poisson–Schrodinger simulation results accounting for adequate band discontinuity and strain. An additional VFB shift is needed to match the measured CV in accumulation, revealing a work function modification or the presence of dipole in the gate stack due to Ge diffusion. [Copyright &y& Elsevier]

Highlights: [•] Ge gate stacks by exposing oxygen plasma to ALD Al2O3/Ge were proposed. [•] GeO x formed between Al2O3 and Ge significantly reduces interface state density. [•] High electron mobility of 690cm2/Vs in Ge nMOSFETs with EOT of 0.7–0.8nm. [•] High hole mobility of 546cm2/Vs in Ge p-MOSFETs with EOT of 0.7–0.8nm. [Copyright &y& Elsevier]

Highlights: [•] Self-aligned and gate-first TiLaO/La2O3 n-MOSFET shows an equivalent oxide thickness (EOT) of 0.57nm. [•] Small EOT can be reached using La silicate to suppress the formation of low-κ defective interface. [•] This low-EOT MOSFET exhibits the potential to integrate with current CMOS process. [Copyright &y& Elsevier]

Abstract: In this work the device characteristic of bilayer graphene MOSFET is investigated by calculation of transmission coefficient using tight-binding method. The real shape of applied potential on the bilayer graphene was included in the tight binding calculation. As obtained transmission coefficient is used to explore the current–voltage characteristics of the device in both on and off regimes. Electrical behavior of the device was obtained for different gate and drains voltages and channel length. [Copyright &y& Elsevier]

Abstract: A nanoscale double-gate MOSFET is simulated with an energy-transport subband model for semiconductors including the effects of non-parabolicity by means of the Kane dispersion relation. The closure relations are derived on the basis of the maximum entropy principle and all the relevant scattering mechanisms of electrons with acoustic and non polar optical phonons are taken into account. The model is shown to form a system of nonlinear parabolic partial differential equations. The results of the simulations validate the robustness of the numerical scheme and the accuracy of the model. In particular, the importance of taking into account the non-parabolicity is assessed, since a relevant difference in the currents is obtained in comparison with the parabolic band case. [Copyright &y& Elsevier]

Abstract: Effect of surface preparation on the radiation hardness of MOS devices with high dielectric constant gate dielectric of HfO2 and metal gate of TiN is studied using extreme ultra-violet (EUV) light as the radiation source. Three kinds of surface treatment including HF-last, chemical-oxidation, and rapid-thermal-oxidation were evaluated. Among them, chemical-oxidation exhibits the best radiation hardiness in terms of interface traps and border traps. The state-of-the-art MOSFET with a thin high-k dielectric and a high quality chemical oxide interfacial layer shows that the degradation of subthreshold swing is more severe than degradation of threshold voltage. However, the overall degradation is less than 6% even after EUV irradiation to a total dose of 580mJ/cm2. Off-state current degradation is observed due to the generation of oxide traps and interface traps at the isolation region. This phenomenon does not occur in the conventional optical lithography process but should be considered if EUV lithography is used. [Copyright &y& Elsevier]

Abstract: The leakage current in standard MOSFET models (BSIM3/BSIM4) is typically modeled by drain–bulk and source–bulk diodes. This modeling method does not consider the impact of several parasitic bipolar devices. For the accurate modeling the impact of the following bipolar transistors has to be considered: a lateral bipolar transistor drain–bulk–source, a vertical bipolar transistor drain–bulk-substrate (only in isolated structures), and a vertical bipolar transistor source–bulk-substrate (only in isolated structures). For example, the drain or source leakage as a function of gate length cannot be modeled without the scalable parasitic bipolar devices. This contribution demonstrates the structure of a proposed macro model, implemented scalability (in most cases nonlinear), developed scaling equations, and physical explanation of this scaling. Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity. This model improvement solves not only leakage current scaling, but it also accounts for additional parasitic bipolar effects, such as current injection to the substrate. [Copyright &y& Elsevier]

Abstract: The temperature dependence of the gate leakage current has been developed for Double Gate (DG) MOSFETs. This model is compared with experimental data measured in Trigate MOSFETs at various temperatures with SiON as a dielectric material and SiO2 as an interfacial layer. The gate leakage current measurements at different temperatures show two different transport mechanisms, direct tunneling (DT) gate leakage and Trap-Assisted-Tunneling (TAT) current. Our analysis based on leakage current measurements in the above threshold regime for different temperatures shows that the DT current is clearly dominant over the TAT, while the opposite happens below threshold. Our model is able to explain the gate tunneling current in terms of gate voltage for different temperatures. The results of the DT current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements. [Copyright &y& Elsevier]

Abstract: We propose here a simple approximate, yet accurate, formula to easily calculate the maximum magnitude of the electric potential at the channel width’s midpoint of symmetric Double Gate (DG) MOSFETs with any arbitrary body doping concentration. According to it this maximum magnitude depends only on the body’s thickness and doping concentration, apart from its usual dependence on quasi-Fermi level splitting. The new formula allows to easily determine the critical body thickness value above which any arbitrarily doped symmetric DG MOSFET can be satisfactorily modeled using a conventional bulk MOSFET model. This critical value depends only on body doping concentration, The proposed approximate formula also constitutes a useful means to quickly calculate initial values in iterative numerical calculations of doped symmetric DG MOSFET models. [Copyright &y& Elsevier]

Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools. [Copyright &y& Elsevier]

Abstract: In this paper, we present an explicit compact quantum model for the direct tunneling current through dual layer SiO2/high-K dielectrics in Double Gate (DG) structures. Specifically, an explicit closed-form expression is proposed, useful to study the impact of dielectric constants and band offsets in determining the gate leakage, allowing to identify materials to construct these devices, and useful for the fast evaluation of the gate leakage in the context of electrical circuit simulators. A comparison with self-consistent numerical solution of Schrödinger–Poisson (SP) equations has been performed to demonstrate the accuracy of the model. Finally, a benchmarking test of different gate stacks have been proposed searching to fulfill the gate tunneling limits as projected by the International Technology Roadmap for Semiconductors. [Copyright &y& Elsevier]

Abstract: A first study of the BTI reliability of a 6Å EOT CMOS process for potential application in sub-threshold logic is presented. Considerable threshold voltage shifts are observed also for sub-threshold operation. The observed shifts convert to a remarkable current reduction due to the exponential dependence of current on V th in this operating regime. Moreover, the pMOS is observed to degrade significantly more w.r.t. the nMOS device, inducing a detrimental V th-imbalance. A proper device failure criterion is proposed, based on simulation of the DC robustness of an inverter logic circuit. [Copyright &y& Elsevier]

Abstract: In this work we used a three-dimensional quantum mechanical simulation approach to simulate a silicon nanowire MOSFET with square cross section. Different gate structures such as double-gate and gate-all-around with a square gate around the wire (square gate-all-around) and with an octagonal gate around the wire (octagonal gate-all-around) are investigated. The Poisson and the Schrödinger equations are solved self-consistently in this analysis. For solving the Poisson equation the Newton–Raphson method and for solving the Schrödinger equation the non-equilibrium Green''s function approach are used. By this simulator the drain current and the electron density and their variations versus the gate voltage are obtained. The transconductance (g m), the gate capacitance (C G) and then the cut-off frequency (f T) are calculated. The short channel effects (i.e. the subthreshold slope and the drain off-current) versus variation of the silicon thickness are obtained. We compared g m, C G and f T for different structures of silicon nanowire MOSFET, i.e. the double-gate, the square gate-all-around and the octagonal gate-all-around due to variation of the gate voltage, the oxide thickness and the silicon thickness. Some advantages for the proposed gate-all-around structure over the other structures are observed. [Copyright &y& Elsevier]

Abstract: As a result of recent trends in processor speed and core temperature, III–V semiconductors have become a tempting replacement for Si in semiconductor logic. However, as device geometries shrink, the advantages of such a switch are put into question. In this paper we present a computational survey of III–V materials in a tri-gate nanowire MOSFET geometry as compared with Si to determine an optimal material choice for this geometry using a 3D semi-classical Monte Carlo simulation tool. We show that InSb and InAs show promise as future materials for next generation switching devices. [Copyright &y& Elsevier]

Abstract: This paper demonstrates a concise and novel voltage-controlled multiple-valued logic (MVL) design using the standard BiCMOS technique. This MVL circuit is constructed by a voltage-controlled negative differential resistance (NDR) circuit, which is integrated by the standard Si-based metal–oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). There exists a two-peak current–voltage curve by connecting two integrated MOS–HBT–NDR elements in parallel as we suitably determine the width/length (W/L) of the MOS devices. In particular, each peak current can be effectively modulated by the corresponding controlled voltage. Using this special characteristic, we can obtain the three logic states with arbitrary sequence at the output. [ABSTRACT FROM AUTHOR]

Abstract: The asymmetric characteristics of the conventional vertical MOSFET are examined. To reduce the IR drop influences of the diffusion resistance for the vertical MOSFET, a new vertical MOSFET for the Vertical Logic Circuit (VLC) configuration, which separates the current paths of small currents from large currents, has been proposed. [ABSTRACT FROM AUTHOR]

Abstract: Several simplifications on MOSFET compact model for oxide breakdown degradation are presented. The current partitioning coefficient is systematically investigated, including influence of drain voltage and increasing breakdown strength. It reveals that several conduction paths are formed during breakdown and that the reduction of channel conductance is the dominant phenomenon at operating voltages. Based on these observations, a new physically based compact model including soft breakdown (SBD) is proposed. KW: soft breakdown, characterization, modeling, reliability. [Copyright &y& Elsevier]

Abstract: In x Ga1− x As III–V compound semiconductor metal–oxide–semiconductor field-effect transistors have become a popular topic recently due to the higher drift velocity, and lower effective mass of the In x Ga1− x As materials. The impact of In content on the accumulation and inversion behaviors of the Al2O3/In x Ga1− x As capacitors is investigated in this study. For the various In x Ga1− x As materials studied, the Al2O3/InAs MOS system showed the strongest inversion phenomena due to the shorter response time of minority carrier of InAs compared to other In x Ga1− x As materials. Also, very low gate leakage current in the 10−8 A/cm2 range was observed for these capacitors. These results demonstrate that Al2O3/InAs MOS system with strong inversion phenomena and low leakage gate current is potential candidate for future high-performance low power logic MOSFET applications. [Copyright &y& Elsevier]

Abstract: Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32nm FinFET technology. [Copyright &y& Elsevier]

Abstract: The minimum operating voltage (Vmin ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin , which is governed by SRAM cells, rapidly increases as devices are miniaturized due to the ever-larger variations in the threshold voltage (VT ) of MOSFETs. The Vmin , however, is reduced to the sub-1-V region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce VT variations. [Copyright &y& Elsevier]

Abstract: This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence onstress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed. [Copyright &y& Elsevier]