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To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low-triggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 um BCD processes and implements a segment layout resulting in a very low dynamic resistance of 2.2 Ω and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

Abstract A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage (V h). Compared with the measured V h of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the V h of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current (I t2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.

Dual-directional silicon-controlled rectifiers (DDSCRs), which provide both positive and negative electrostatic discharge (ESD) surge paths, are ESD protection devices with an excellent area efficiency. However, DDSCRs have a low holding voltage for use in 5 V-class applications, with a relatively high on-state resistance because of the elongated ESD surge path compared to unidirectional SCRs. In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18-μm CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications.

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

For robust high-voltage (HV) electrostatic discharge (ESD) protection engineering, such as 8-KV or 15-KV ESD target, the silicon-controlled rectifiers (SCRs) with high holding voltage are needed to mitigate latch-up risk. However, when implemented in the multifinger layout configuration for satisfying high robust ESD requirement, these devices may encounter holding voltage deterioration problems. In this article, such holding voltage deterioration has been explored by theoretical analysis and experimental verification. The transmission line pulsing (TLP) results indicate that the sharing of adjacent WELL pickup and removing of inner guard ring in the typical multifinger layout (TMF) are the root causes for holding voltage deterioration. Through the appropriate test-key design, both of these culprits have been identified independently. Finally, by keeping the average WELL pickup length and average number of parasitic paths of each SCR finger in the multifinger layout constant, such holding voltage deterioration can be restrained effectively, achieving a stable holding voltage regardless of the number of fingers. Therefore, this article offers very useful work for HV ESD engineering. [ABSTRACT FROM AUTHOR]

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications. [ABSTRACT FROM AUTHOR]

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology. [ABSTRACT FROM AUTHOR]