69 results on '"Horiguchi, N."'
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2. Dual Operation of Gate-All-Around Silicon Nanowires at Cryogenic Temperatures: FET and Quantum Dot
3. Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology
4. Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K
5. CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
6. Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch
7. Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies
8. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis
9. Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application
10. 3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling
11. Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
12. Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)
13. Integration of a Stacked Contact MOL for Monolithic CFET
14. Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions
15. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
16. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
17. Reliability challenges in Forksheet Devices: (Invited Paper)
18. Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
19. Insights into Scaled Logic Devices Connected from Both Wafer Sides
20. Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
21. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
22. Low temperature source/drain epitaxy and functional silicides: essentials for ultimate contact scaling
23. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
24. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
25. Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling
26. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
27. High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories
28. Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
29. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
30. Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery
31. Inspection and metrology challenges for 3 nm node devices and beyond
32. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
33. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
34. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
35. Buried Power Rail Metal exploration towards the 1 nm Node
36. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
37. Monte Carlo Analysis of -Type SiGe-Channel Nanosheet Performance<italic/><sub/><sub/>
38. Middle-of-line plasma dry etch challenges for buried power rail integration
39. Buried power rail integration for CMOS scaling beyond the 3 nm node
40. Middle-of-line plasma dry etch challenges for CFET integration.
41. Middle-of-line plasma dry etch challenges for CFET integration
42. Middle-of-line plasma dry etch challenges for buried power rail integration.
43. Dual 5-HT 2A and 5-HT 2C Receptor Inverse Agonist That Affords In Vivo Antipsychotic Efficacy with Minimal hERG Inhibition for the Treatment of Dementia-Related Psychosis.
44. Clinical, Pathological and Endoscopic Features of Neoplastic or Non-neoplastic Reddish Depressed Lesions after Helicobacter pylori Eradication.
45. The Alzheimer's disease-linked protease BACE2 cleaves VEGFR3 and modulates its signaling.
46. Allosteric inhibition of phosphodiesterase 4D induces biphasic memory-enhancing effects associated with learning-activated signaling pathways.
47. Helicobacter pylori infection associated DNA methylation in primary gastric cancer significantly correlates with specific molecular and clinicopathological features.
48. A stag beetle knife can achieve stabler and safer endoscopic submucosal dissection in the esophagus.
49. Segmental absence of the intestinal musculature in the stomach of an adult found during endoscopic submucosal dissection.
50. Large Inflammatory Myofibroblastic Tumor of the Esophagus: A Case Report and Literature Review.
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