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The eight stacked Ge $_{0.75}$ Si $_{0.25}$ nanosheets, the seven stacked Ge $_{0.95}$ Si $_{0.05}$ nanowires, and the six stacked Ge $_{0.95}$ Si $_{0.05}$ nanowires without parasitic channels are demonstrated. These highly stacked channels are made from 18 epilayers consisting of a Ge buffer, nine heavily P-doped Ge sacrificial layers, and eight GeSi channel layers with the low growth temperature (350 °C and 375 °C) to ensure the entire epilayers metastable without dislocations in the channels. The isotropic wet etching by H₂O₂ and NH $_{4}$ OH + H₂O₂ is used for the channel release and the removal of the parasitic channels, respectively. The delicate interplay between epilayer design and wet etching is implemented to fabricate the highly stacked GeSi channels. High inter-channel uniformity of the eight stacked Ge $_{0.75}$ Si $_{0.25}$ nanosheets is obtained due to the superior etching selectivity. High $I_{{on}}$ per stack and per footprint of the seven stacked Ge $_{0.95}$ Si $_{0.05}$ nanowires and the six stacked Ge $_{0.95}$ Si $_{0.05}$ nanowires without parasitic channels are achieved due to the high mobility $L_{4}$ valleys and nanowire conduction. The reduced subthreshold slope (SS) and improved $I_{{on}}$ / $I_{{off}}$ are obtained by parasitic channel removal. The record $I_{{on}}$ of 120 μA per stack (4600 μA/μm per channel footprint) at $V_{{OV}} = V_{{DS}} = 0.5$ V is reached among reported Ge/GeSi 3-D nFETs.

The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

The distinct photoresponse of the floating channels and the parasitic channels can be a signature to check the existence of the parasitic channel. The photoresponse of the sole parasitic channel mainly shows the photocurrent ( ${I}_{\text {ph}}$ ), while the photoresponse of the sole floating channels without parasitic channel shows the negative threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) for nFET. The device with both the floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure.

The undoped 4-stacked Ge 0.9 Sn 0.1 nanosheets sandwiched by double Ge 0.95 Sn 0.05 caps without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. High inter-channel uniformity of the stacked GeSn nanosheets is achieved to enhance ION by thin Ge 0.9 Sn 0.1 (5nm) channels. The carriers are separated from dielectrics by the caps to reduce the impurity and surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( ON =73μA per stack (910μA/μm per channel footprint) at V OV =V DS =-0.5V is achieved among GeSn 3D FETs for the sheet width/Lg of 80nm/80nm. The I ON per channel footprint can be improved to 1070μA/μm with the sheet width scaled to 57nm due to the large carrier population at the two ends of nanosheets. The double caps as barriers for the holes in the Ge 0.9 Sn 0.1 nanosheets decrease the low frequency noise by reducing trapping/detrapping between the GeSn nanosheets and the gate dielectrics.

Tungsten-based material is a promising candidate for work function metal. Tungsten with high electrical conductivity and midgap work function [1] has been used to fill the gate and contact plugs in the industry. In this work, the effective work function (EWF) of sputtered WN x is tuned by varying the annealing temperature and the nitrogen content in the WN x films. The EWF of sputtered WN x has 600 meV range around Si midgap. Furthermore, the tungsten-based gate metal WN x C y by plasma-enhanced atomic layer deposition (PEALD) is successfully integrated in stacked gate-all-around (GAA) transistors to modulate the Vt with no performance degradation.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $\mathrm{I}_{\mathrm{O}\mathrm{N}}=42\mu 1$ per stack ( $10.5\mu A$ . per sheet) at $\mathrm{V}_{\mathrm{OV}}\mathrm{V}_{\mathrm{DS}}=-0.5\mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus- doped Ge sacrificial layers over unintentionally doped Ge 0.98 Si 0.02 to form two stacked Ge 0.98 Si 0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. The parasitic Ge/Si channel underneath the Ge 0.98 Si 0.02 channels is completely removed by optimized etching. The infrared response of the parasitic channel is a non-destructive method to further confirm the removal of the parasitic channel. VT can be tuned by PMA, and ION can be enhanced by short L G . Record ION of 48 μA at V OV =V DS =0.5V and record Q (G m,max/ SS SAT ) of 8.3 at V DS =0.5V with L G = 40 nm are achieved among Ge nFETs. The results are comparable to Si nFETs.

Record [Sn]=12% and record compressive strain of 3.3% among GeSn 3D transistors to enhance the ION are demonstrated by CVD epitaxy. For the first time, in-situ Ge 0.95 Sn 0.05 caps are grown on stacked Ge0.ssSn0.12 channels to improve interface quality and separate carriers from the interface to achieve high mobility. L G is scaled down to 40nm to further boost the ION. Low channel doping and high S/D doping ([B] peak ~1E21cm-3) can suppress the impurity scattering in the channels and reduce the contact resistivity for the S/D, respectively, to reveal the intrinsic merit of the high mobility of GeSn. The stacked 3 Ge 0.88 Sn 0.12 nanosheets achieve record ION of 58µA at V OV =V DS = -0.5V and record G m,max of 172µS at V DS = -0.5V among GeSn pFETs, and the performance is comparable to mature Si FinFETs, stacked Si channels, and stacked Ge channels. The caps as barriers on the Ge0.ssSn0.12 channels decrease the low frequency noise by reducing trapping/detrapping between the GeSn channels and the gate dielectrics.

The tensily strained high Ge content (85%) GeSi multi-channels stacked on the Si channel with channel size optimization have good subthreshold behaviors (SS, DIBL, and $\mathrm{I}_{\mathrm{off}}$ ), and meanwhile maintain high $\mathrm{I}_{\mathrm{on}}$ . By narrowing GeSi channel, the bandgap of the GeSi can be increased by quantum confinement and the short channel effect can be suppressed. This also causes the more positive $\mathrm{v}_{\mathrm{t}}$ for GeSi than Si. As a result, $\mathrm{SS}=76\mathrm{mV}/\mathrm{dec}, \mathrm{DIBL}=36\ \mathrm{mV}/\mathrm{V}$ can be achieved due to the benefit of superior subthreshold behaviors of the Si channel underneath. The $\mathrm{I}_{\mathrm{on}}/\mathrm{I}_{\mathrm{off}}$ is improves to be 1.2E7. The high $\mathrm{I}_{\mathrm{on}}=44\mu \mathrm{A}$ perstack at $\mathrm{Vov}= \mathrm{V}_{\mathrm{DS}}=1\mathrm{V}$ , is contributed from both the GeSi and Si channels, and it is further enhanced to $46\ \mu \mathrm{A}$ by the external strain. The relatively low flicker noise indicates that the novel structure can mitigate the reliability issue of GeSi channels by the highly reliable Si channel underneath.

Si FinFET architecture has been used in mass production in the industry for advanced technology nodes. Thin and tall fin for high drive current is needed for further scaling by FinFETs. However, fin aspect ratio and lithography limitation may be problematic issues. Recently, vertically stacked channel GAAFETs become good candidates to achieve better power-performance properties than FinFETs for the given footprint. The evolution to the stacked GAAFETs mitigates the patterning challenges by well-controlled epitaxy and high etching selectivity to achieve high performance and good electrostatics. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate vertically stacked tensily strained GeSi nGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to achieve high performance and to improve the electrostatics for Ge-based channel GAAFETs. The Ge/Ge0.85Si0.15 and Ge/Ge0.98Si0.02 multilayers are epitaxially grown on SOI substrates by CVD epitaxy. Ge buffer layers and sacrificial layers are not only used to achieve etching selectivity over GeSi layers to form the vertically stacked GeSi channels, but also used to provide tensile strain for GeSi n channels. Undoped channels and heavily doped sacrificial layers are used to reduce the impurity scattering and S/D resistance, respectively. The following PMA, laser annealing, and NiGe contacts formation for nFETs can further reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi channels. For GeSi nFETs, [Ge] larger than 85% in GeSi can ensure L valley conduction for small conductive effective mass to achieve high mobility. The △Ec between GeSi and Si is nearly zero and can be negligible. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels GAAFETs. We demonstrate the vertically stacked Ge0.85Si0.15 channels above a Si channel, which has good subthreshold behaviors. The VT difference between Ge0.85Si0.15 and Si can be tuned by the channel size optimizing. By narrowing the Ge0.85Si0.15 channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive VT for Ge0.85Si0.15 than Si is observed. Therefore, the underneath Si channel with good electrostatic turn on first and dominate the subthreshold region. Good SS=76mV/dec and low DIBL=36mV/V are obtained due to low Dit and good short channel control. IOFF is also dramatically reduced and the ION/IOFF is improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow Ge0.85Si0.15 channels. The improved flicker noise of optimized channel size also indicates the enhanced reliability. To increase [Ge] in channel layers for mobility enhancement, Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus-doped Ge sacrificial layers over undoped Ge0.98Si0.02 to form two stacked Ge0.98Si0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. An additional 800oC anneal after the Ge buffer growth further improves the epi quality by confining misfit dislocations near the Ge buffer/Si interface. However, the Dit at Si underneath channel/dielectrics interface may be poor due to misfit dislocations confinement. As a result, the parasitic Ge/Si channel underneath the Ge0.98Si0.02 channels is completely removed by optimized etching. The distinct photoresponse of the floating channels and the parasitic channels can be a signature and provide a non-destructive method to check the existence of the parasitic channels. The photoresponse of the sole parasitic channel mainly shows the photocurrent (Iph), while the photoresponse of the sole floating channels without parasitic channel yields the negative threshold voltage shift (ΔVT) for nFETs. The device with both floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure. ION can be enhanced by scaled LG and large channel cross section. Record ION of 48μA per stack at VOV=VDS=0.5V and record Q (Gm,max/SSSAT) of 8.3 at VDS=0.5V with LG=40 nm are achieved among Ge nFETs. CVD grown Ge nGAAFET is compatible with Si technology. Excellent electrical characteristics are achieved and the results are comparable to mature Si nFETs. Indicating vertically stacked high mobility channel is promising candidate for CMOS applications in the future technology nodes to further extend the Moore’s law. Acknowledgements: This work is supported by MOST (MOST 109-2218-E-002-031- and 108-2622-8-002-016-) and MOE (NTU-CC-109L891601), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.