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Gallium oxide (Ga 2 O 3 ) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO 2 gate dielectric both showed a low off-state drain current of about 1.8 × 10 −10 A/mm. The effects of recess depth on the electronic characteristics of Ga 2 O 3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate. [ABSTRACT FROM AUTHOR]

Here, hydrogenated diamond (H-diamond) NOR logic circuits composed of two p-type enhancement-mode (E-mode) metal-oxide-semiconductor field-effect-transistors (MOSFETs) and a load resistor are fabricated and characterized. The fabrication process and the annealing effect on the electrical properties of the NOR logic circuit are demonstrated. There are distinct logical characteristics for the as-received and 300 °C annealed NOR logic circuits. When one or both input voltages for the E-mode MOSFETs are −10.0 V and “high” signals, output voltages respond 0 V and “low” signals. Instead, when both input voltages are 0 V and “low” signals, output voltage responds −10.0 V and a “high” signal. After annealing at 400 °C, the NOR logical characteristics are damaged, which is possibly attributed to the degradation of the H-diamond MOSFETs. [ABSTRACT FROM AUTHOR]

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage. [ABSTRACT FROM AUTHOR]

A novel In0.53Ga0.47As/InP heterostructure trench-gate power MOSFET employing impact ionization at the hetero junction of n- In0.53Ga0.47As drift region and n+InP drain region has been proposed. The impact ionization supports the band-to-band tunneling at heterojunction, which further increases the drain current. It results in reduced ON-state resistance and improved transconductance without compromising with the breakdown voltage as compared with the conventional silicon trench-gate MOSFET (CTGMOS). Using 2-D numerical simulations, we demonstrate that the proposed device exhibits ~440% improvement in peak transconductance, ~92% reduction in on-state resistance, ~10% increase in breakdown voltage, ~16% increase in switching speed, and ~93% improvement in figure of Merit (RON.QGD) as compared with CTGMOS. [ABSTRACT FROM AUTHOR]

We have developed a 2-dimensional analytical model to study the subthreshold swing and channel conductance of a gate and channel engineered double gate MOSFET. Basic diffusion equation has been considered to model the drain to source current of the device in subthreshold region and expressions of the device parameters like subthreshold swing and channel conductance have been derived. Subthreshold swing variations of the device with varied materials, channel, and effective oxide layer thickness and channel length have also been investigated. Changes in subthreshold swing owing to different doping profile concentrations have been explored. Effect of similar device parameters on the channel conductance of the device has been examined as well. Another important observation of the work is the pseudo flat band condition of the device structure based on the intersecting point of body potentials of the device at different thickness of the channel. The analytical results of the proposed model have been validated with the numerical results from commercially available 2-dimensional device simulator. [ABSTRACT FROM AUTHOR]

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology. [ABSTRACT FROM AUTHOR]

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods. [ABSTRACT FROM AUTHOR]

The design of CMOS circuits using nanoscale MOSFET has become very difficult nowadays as device modeling faces new challenges such as short channel effects and mobility degradation. Gate engineering and channel engineering reduces these challenges and improves the mobility of the carriers, resulting in improved characteristics such as drain current and transconductance. In this review paper, the effect of gate and channel engineering on the characteristics (both D.C and high frequency (a.c)) of multigate MOSFETs have been investigated and presented. [ABSTRACT FROM AUTHOR]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

This paper presents a detailed investigation of the static and Mixed − Mode analysis of the accumulation-mode cylindrical gate all around (AM-CGAA) MOSFET. Consequently, the work extends to the design and analysis of the inverter characteristics like noise margin (NM), effect of voltage scaling and transient response, etc. using the proposed device. Accumulation-mode devices are an alternative to conventional MOSFETs that do not require high cost ultrafast annealing technique for fabrication of smaller length devices. Hence, we prefer to demonstrate the short channel effects (SCEs) and DC characteristics of both n- and p-type AM-CGAA devices at different channel lengths. Further the action of inverter has been systematically explored using the complementary device architecture. The switching and transient characteristics of the inverter is analyzed and compared with experimental data reported in literature. Noise margin and delay performances have also been demonstrated which are found to be in good agreement with the information available in the literature for nano-scale devices. Moreover, the proposed device shows better on/off ratio, near to ideal sub-threshold slope (SS), low drain induced barrier lowering (DIBL) value and acceptable CMOS functionalities. [ABSTRACT FROM AUTHOR]

This paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first- and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, we propose a multi-channel charge-based capacitance measurement (MCCBCM) technique for parasitic capacitances extraction of MOSFETs. The proposed technique is developed from a leakage- and parasitic-insensitive charge-based capacitance measurement technique, which is applied to measure gate-to-channel capacitance in certain regimes. Using the MCCBCM technique, we can measure all of the parasitic capacitance components of an MOSFET which are related to its terminals, such as the gate-to drain capacitance ( CGD ), gate-to-source capacitance ( CGS ), gate-to-bulk capacitance ( CGB ), and so on. We designed a complex control methodology for the MCCBCM circuit. Specific control methods are provided for different parasitic capacitance components when MOSFETs work in different regimes. We can measure capacitances of sub-femto-farad level in all regimes, including the accumulation, depletion, and inversion regimes. [ABSTRACT FROM PUBLISHER]

This paper presents a high-temperature (HT) gate drive and protection circuit for Silicon–Carbide (SiC) power mosfets entirely built from commercial off-the-shelf HT discrete components. To estimate cost reduction, a brief comparison was made between the proposed circuit and a commercial circuit using silicon-on-insulator integrated circuits. To evaluate performance, power tests were conducted up to 180 °C in a thermal chamber. Eventually, the proposed circuit achieved a 90% cost reduction, and all functions were validated by experiments at 180 °C. This demonstrated that the proposed circuit is a cost-effective solution for contemporary HT applications. [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]

A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determines the drain current. The model is supported by experimental measurements in JL nanowire transistors with channel length varying from 95 to 25 nm and doping concentration 2 \times 10^19 cm ^\mathrm -3 . The overall results reveal the very good accuracy of the proposed analytical compact model, making it suitable for circuit simulation tools. [ABSTRACT FROM PUBLISHER]

The voltage source driver (VSD) is widely used in a conventional gate drive circuit of the power factor correction (PFC) converter. However, the fixed drive current of the VSD circuit could not optimize the switching losses, and the turn-off voltage spike across the power switch is freewill. In this letter, a real-time variable turn-off current strategy of a power switch for the PFC converter is presented. The turn-off current can be modulated real timely with the input voltage varying periodically, and the voltage spike across power switch can be controlled under the peak value that set at the peak input voltage region. The operation principle, design considerations, and the analysis of turn-off switching losses with the proposed strategy are presented by a boost PFC converter in detail. Furthermore, a prototype of the boost PFC converter was built to verify the effectiveness of the proposed strategy. As a result, the turn-off voltage spike is well limited and the efficiency is effectively improved compared with the VSD. The proposed idea can be also further extended to any other PFC converters. [ABSTRACT FROM AUTHOR]

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness t\mathrm{ si} , thick gate oxide thickness t\mathrm{ ox} , and short channel length Lg , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope \eta and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage V_{\mathrm{ dd,min}} for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis. [ABSTRACT FROM AUTHOR]

The quasi-saturation (QS) effect in a power MOSFET has been discovered several decades ago. As the field has evolved and the dimensions in power MOSFETs have changed from tens of micrometers to submicrometer levels, and the gate geometry has evolved from planar to trench, the origin and the effect of the QS need to be re-assessed. This letter first discusses the origin of the QS effect in the state-of-the-art power MOSFETs and subsequently analyses the phenomenon of majority carrier injection (or diffusion) and its contribution to the increased carrier concentration in the drift region, specific to quasi-saturation. [ABSTRACT FROM AUTHOR]

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches. [ABSTRACT FROM AUTHOR]

It is demonstrated that nanoprobing technique is superior in localizing silicide defect rapidly in metal-oxide-semiconductor field-effect transistor (MOSFET). Cobalt silicide (CoSi 2) as an interfacial material below tungsten contact plug, various types of defects about CoSi 2 often cause leakage current in MOSFET, so close studies of problematic silicide is significant regarding MOSFET reliability enhancement. When one MOSFET in a combinational logic circuit is suspected of anomaly, because this kind of circuit is composed of several devices which are sometimes arranged in an active area (AA) of unique geometric shape, it is impossible to collect MOSFET characteristic correctly based on regular nanoprobing flow since conventional method hits limit for combined circuits measurement. Such circumstance almost impedes failure analysis (FA) in device level. Nevertheless, relying on our alternative strategy of multi-probe configuration, a novel nanoprobing analysis flow is adopted for device examination. It is shown that exact I-V characteristic of failed device can be captured by proposed workflow. Following I-V curve analysis further reveals an evident electrical signature of abnormal abrupt junction. It corresponds to an active area shorting with its surrounding nwell region. In addition, sophisticated leakage current behaviors are exhaustively interpreted by simplified models. Eventually, we confirmed CoSi 2 encroachment from the active area into nwell by the means of transmission electron microscopy (TEM) analysis. This paper presents an effective analysis to identify leaky junction of MOSFET in logic circuit that is rarely reported before. Furthermore, our exploration exhibits impressive flexibility of nanoprobing analysis in terms of localizing unusual silicide defect, so nanoprobe analysis is clearly an attractive option to optimize MOSFET manufacturing. • Propose a novel nanoprobing workflow to identify minute silicide encroachment into well of MOSFET. • Sophisticated leakage current behaviors are exhaustively interpreted by simplified models. • Demonstrate the merit of multi-probe configuration regarding analysis of faulty combinational logic circuit. [ABSTRACT FROM AUTHOR]

One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO2 DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions. [ABSTRACT FROM AUTHOR]

A method for modeling the distributive effects of RC transmission line is developed which is applicable to cases in which one end or both ends are connected to the input signal. Nonuniform recursive segmentation is used. The segments are categorized into three types, with each modeled by a distinctive and asymmetric lumped circuit in $\pi $ topology. The number of segments is determined by the frequency range required. The new method is applied to model the distributed MOSFET gate and bipolar junction transistor base. Both frequency and transient response characteristics are much better modeled compared with existing methods. [ABSTRACT FROM AUTHOR]

For the first time, a full analytical model of the electric field in the gate oxide of 4H-polytype silicon carbide (4H-SiC) power double-implanted MOSFET devices is shown. It takes into account all the relevant physical and geometrical parameters of the device and avoids the use of any fitting parameters. To validate the results of the full-analytical model, comparisons with numerical simulations are reported for device structures having different values of the drift doping concentration and drift thickness as well as of the junction FET (JFET)-region width. Moreover, because the model equations are in closed form, they can be used to derive an adequate JFET-region geometry by fixing the maximum electric field in the oxide and the maximum blocking voltage for a given drift region. [ABSTRACT FROM AUTHOR]

In this work, we propose a junctionless MOSFET with asymmetric gates (AG-JL MOSFET). This device is a double gate structure with a lateral offset between the gate, and this leads to different characteristic than a conventional double gate structure. Specifically, the asymmetric gate modulates the effective channel length depending on whether the device is in the ON or OFF state, which this leads to more ideal device characteristics. A comprehensive device performance comparison including the I ON /I OFF ratio, subthreshold slope (SS), and drain-induced barrier lowering (DIBL) between the proposed device and a conventional device is presented. The proposed device exhibits superior performance when compared a conventional device, and results show that it is also less sensitive to process variations. [ABSTRACT FROM AUTHOR]

We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI substrate, with the novel recessed channel and source/drain structures. Various channel lengths ( L\mathrm {ch} ) from 500 to 30 nm and channel thicknesses ( T\mathrm {ch} ) from 90 to 10 nm are implemented into the Ge CMOS devices and comprehensive geometry dependence analysis is carried out in terms of both L\mathrm {ch} and T\mathrm {ch} . With shrinking T\mathrm {ch} , the gate electrostatics are enhanced significantly but the on-state performance is found to be deteriorated simultaneously. It is also confirmed that Ge nMOSFETs are more sensitive to T\mathrm {ch} than pMOSFETs due to the phosphorus diffusion inside Ge. CMOS circuits, such as inverters, NANDs, NORs, and ring oscillators, are further investigated. [ABSTRACT FROM PUBLISHER]

Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. The device parameters such as the thick silicon thickness, thick gate oxide thickness, high doping density, and short channel length can severely degrade the NM due to serious SCE. By contrast, both the small subthreshold slope $\eta $ and the balanced transistor strength S can suppress the NM degradation more efficiently. The required minimum supply voltage V_{\mathrm {\mathbf {dd,min}}} for the subthreshold CMOS logic gate is derived by the criterion of the NM larger than thermal noise to ensure the correct logic gate operation. Being similar to drain-induced barrier lowering, allowable NM corresponding to the minimum channel length can also be uniquely controlled and determined by the scaling factor according to the scaling theory. [ABSTRACT FROM PUBLISHER]

A novel monitoring test structure is proposed for plasma process-induced charging damage (PID) based on charge-based capacitance measurement (CBCM), referred to as PID–CBCM. By eliminating antenna capacitance interferences, a remarkably smaller gate capacitance (tens of fF) can be obtained for effectively evaluating the influence of PID on metal oxide semiconductor field-effect transistors (MOSFETs). Moreover, the interface trap density can be extracted simultaneously using PID–CBCM implemented with modified charge pumping measurements. Furthermore, another type of PID–CBCM structure under unique measurement conditions has been developed to evaluate drain current (Id) as a function of gate voltage (Vg). The new structure works by extracting the threshold voltage (Vth) shifts on the basis of capacitance–voltage (C–V) characteristics after applying a stress voltage to the gate oxide of devices under test in the PID–CBCM structure. Based on these approaches, three meaningful characteristics of the PID are obtained: 1) Vth shifts extracted from C–V characteristics; 2) Vth shifts extracted from Id–Vg characteristics; and 3) interface trap density extracted from charge-pumping current. Thus, the effects of PID on MOSFET can be monitored over suitably small areas such as scribe-line and chip areas. [ABSTRACT FROM PUBLISHER]

The purpose of this paper is to compare the operations of silicon-based solid-state quantum computer with classical logic gate made of double-gate (DG) nano-MOSFETs. Quantum gates, such as quantum NOT gate, controlled-NOT (CNOT) and quantum register are studied. On the other hand, classical computer gates, such as NOT gate, NOR gate, NAND gate, XOR gate and XNOR gate are described. Silicon-based solid-state quantum computer operates well at extremely low cryogenic temperature (77K) as shown by oscillation of electron density profiles of the silicon-based nanodevices. Unitary matrix which specifies a valid quantum gate is proven in this study. The intrinsic delay of the classical NOT gate is calculated from simulation output data and the current-voltage (I-V) characteristic of the DG nano-MOSFET, which is used to construct the NOT gate, is plotted and studied. The motivation of this study is to investigate ways to implement quantum computer with silicon-based DG nano-MOSFET implanted with phosphorus donor atoms. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

The high ON-resistance and the limited breakdown voltage (BV) are the two major issues for the p-channel lateral double-diffused MOSFET (pLDMOS). To solve the two issues, an ultralow specific ON-resistance ( R\mathrm{\scriptscriptstyle ON,\textrm {sp}} ) pLDMOS with improved BV is proposed and investigated by simulation. It features an extended gate (EG) with accumulation effect over the drift region and a P+ floating layer (PFL) in the N-sub. In the ON-state, the EG induces the hole accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode makes R\mathrm{\scriptscriptstyle ON,\textrm {sp}} almost independent of the drift region doping concentration ( Nd ) and contributes to a much lower R\mathrm{\scriptscriptstyle ON,\textrm {sp}} , which greatly breaks through the silicon limit of R\mathrm{\scriptscriptstyle ON,\textrm {sp}}\propto \textrm {BV}^{2.5} . In the OFF-state, the EG not only modulates the surface electric field ( E -field) distribution to enhance the BV, but also helps deplete the drift region to increase the optimized Nd , and thus further reduce R\mathrm{\scriptscriptstyle ON,\textrm {sp}} . Moreover, the PFL is not depleted, and thus equipotential in the lateral direction. Therefore, the PFL not only modulates the bulk E$ -field distribution at the source and drain sides but also introduces an additional vertical diode to sustain a higher BV. Owing to the effects mentioned above, the simulated results show that the EG PFL pLDMOS decreases R\mathrm{\scriptscriptstyle ON,\textrm {sp}} by 68% and increases the BV by 47% compared with the conventional pLDMOS. [ABSTRACT FROM AUTHOR]

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained. [ABSTRACT FROM AUTHOR]

Extrinsic parasitic series resistance and mobility degradation are two important parameters limiting the performance of multifinger microwave MOSFETs. In this paper, we present a method to extract these parameters from measured drain-voltage versus gate-voltage characteristics at given constant values of drain current. Measured data of multifinger microwave MOSFETs are used to test and verify the developed method. The method requires only simple dc measurements on a single test device. [ABSTRACT FROM AUTHOR]

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - \mu \text{m} , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility. [ABSTRACT FROM AUTHOR]

This paper presents an accurate and computationally efficient method to calculate the drain–source saturation voltage V\mathrm{ dsat} of dual-gate (i.e., four-terminal) junction field-effect transistors. The method accounts for velocity saturation and for channel thickness modulation by any combination of MOS or p-n junction gates. In three iterations, it achieves an error of less than 2%. Our algorithm converges significantly faster than the direct application of the Newton–Raphson method because of careful selection of an initial value and the leverage of the convex and concave nature of the curves whose intersection defines V\mathrm{ dsat} . The method is applied to both the exact model for I\mathrm{ ds} and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

This letter investigates the oxide trap properties in n-channel metal-oxide–semiconductor field-effect transistors with HfO2 and Hf1-xZrxO2/metal gate-stacks by an analysis of random telegraph signals. According to the multiphonon emission theory, the extracted relaxation energies show gate voltage dependence in devices with HfO2-based stacks. This dependence results from the different strengths of vibrations of the nearest neighbor Hf atoms of the oxygen vacancy in the immediate vicinity of the oxide trap. Furthermore, this dependence also induces an abnormal gate voltage dependence in terms of the activation energy required for electron capture. These results are confirmed by comparisons between two HfO2-based devices (HfO2 and Hf1-xZrxO2). [ABSTRACT FROM AUTHOR]

A novel 4H-SiC trench metal–oxide–semiconductor field-effect transistor (MOSFET) with an L-shaped gate (LSG) is proposed and studied via numerical simulations in this letter. Adoption of an additional LSG region that surrounds the bottom corner of the trench allows the peak electric field in the SiO2 dielectric to be significantly relieved by charge compensation, and the device breakdown voltage can be greatly enhanced without causing significant degradation of the output characteristics. In high-voltage blocking states, the electric field at the bottom corner of the trench is weakened, which leads to improved device performance. The peak electric field value in the SiO2 dielectric decreases by 32.3% when compared with that of a conventional 4H-SiC trench MOSFET, while the breakdown voltage increases by 80.4%. [ABSTRACT FROM AUTHOR]

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1]. Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$, and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications. [ABSTRACT FROM PUBLISHER]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the high series resistance associated to the source and drain extensions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. In the present paper, a numerical investigation for the drain current and small signal characteristics is conducted for the DGJ MOSFET by including highly doped extension regions. The proposed approach, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current, small signal parameters, analog/RF behavior and linearity of DGJ MOSFET for high performance analog applications. In this context, I – V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage. [ABSTRACT FROM PUBLISHER]

In this study, the properties of dielectric traps by the impact of Fluorine (F) implantation on 1/ f noise and the random telegraph noise (RTN) of high-k/metal gate (HK/MG) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) were investigated. The incorporation of F has been identified as an effective method to passivate oxygen vacancies, defect sites, and reduce the gate leakage current in pMOSFETs. Compared with a control device, the F-implanted HK/MG devices show that the trap positions were closer to the SiO 2 interfacial layer (IL)/Si channel. Furthermore, we found that F implantation could result in a smaller tunneling attenuation length ( λ ) and smaller slow oxide interface trap density ( N t ). [ABSTRACT FROM AUTHOR]

This paper demonstrates the feasibility of using data extracted from experimental S-parameters to implement models to accurately represent MOSFET behavior under DC and RF regimes with consistency. For this purpose, a method to extract the MOSFET's drain-to-source conductance, the subthreshold swing, the source/drain resistance, the effective gate length, and the threshold voltage is proposed. The method is based on the determination of the inverse of the channel resistance that is directly related to the previously mentioned parameters. Hence, two-port S-parameter measurements of common-source configured RF-MOSFETs with different gate lengths are performed, varying the gate-to-source voltage from the subthreshold region to strong inversion. In order to verify the validity and consistency of the method, excellent correlation of DC and RF models with experimental data is achieved. [ABSTRACT FROM AUTHOR]

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si. [ABSTRACT FROM AUTHOR]

In this paper, a physics based model has been presented for the Cylindrical Surrounding Double Gate (CSDG) Nano-wire MOSFET. The analytical model is based on the solution of 2-D Poisson's equation in a cylindrical coordinate system using super-position technique. CSDG MOSFET is a cylindrical version of double gate MOSFET which offers maximum gate controllability over the channel. It consists of an inner gate and an outer gate. These gates render effective charge control inside the channel and also provide excellent immunity to short channel effects. Surface potential and electric field for inner and outer gate are derived. The impact of channel length on electrical characteristics of CSDG MOSFET is analysed and verified using ATLAS device simulator. The model is also extended for threshold voltage modelling using extrapolation method in strong inversion region. Drain current and transconductance are compared with conventional Cylindrical Surrounding Gate (CSG) MOSFET. The excellent electrical performance makes CSDG MOSFET promising candidates to extend CMOS scaling roadmap beyond CSG MOSFET. [ABSTRACT FROM AUTHOR]

2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate–source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator. [ABSTRACT FROM AUTHOR]

The scaling of MOSFET transistors makes the use of new device geometries, such as multigate FETs, a need to solve the limitations of the conventional bulk technology. In this context we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. The modeling of rounded corners in GAA and FinFET devices is imperative because there are no perfectly square corners in the cross-section of real devices. In this model the 2D inversion charge distribution function (ICDF) is described analytically for devices of different sizes and for different operation regimes. The model reproduces accurately simulated data obtained with a state-of-the-art simulator that solves self-consistently the Poisson and Schrödinger equations in the devices under consideration. The analytical ICDF is used to better understand the device physics and to calculate the inversion charge centroid and the gate-to-channel capacitance for different device geometries and biases for modeling purposes. [ABSTRACT FROM AUTHOR]