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The article focuses on reusable intellectual property (IP) as the new abstraction in systems on chips (SOCs). It mentions the difference of the traditional design flow and the IP-centric flow. It cites the ideal assembly process beginning with system-level stimulation as IP selection verification process, the importance of rapid prototyping and the integrated circuit (IC) implementation all coming from once source. It also notes the advanced microcontroller bus architecture (AMBA).

The article elaborates on the development of and present trends on central processing units (CPU) in field-programmable gate arrays (FPGA). A discussion on the various attempts to adapt CPU cores in an FPGA fabric, which includes the ColdFire microprocessor by Freescale Semiconductor and the ARM7 processor family from ARM Ltd., and the difficulties encountered is presented. The various approaches of Altera Corp., Xilinx, Inc., Actel Corp., and Lattice Semiconductor Corp. in developing CPU cores and the capabilities of these cores are discussed.

The article explores whether intellectual-property (IP) reuse may be the best system-level chip-design method. Although rare, it is stated that successful reuse depends on treating IP blocks as black boxes. Also discussed is how an emerging IP-integration flow overlays the traditional register-transfer-level (RTL)-to-Graphid Design System 2 (GDSII) flow. Detailed, as well, are the many opportunities that exist for automation to make this flow into a methodology. INSET: USING AND ADOPTING IP-XACT.

The article discusses the latest developments in system-on-chip (SOC) design as of June 2010. It examines the important role played by intellectual-property (IP) reuse, power management and advanced processes in the SOC design flow. According to Virage Logic technical marketing director Lisa Minwell, they also deal with design-for-manufacturing (DFM) regulations in SOC design. The opinion of Open-Silicon's Taher Madraswala on the subject is also cited.

The article discusses field-programmable gate arrays (FPGA) and the networking industry. It mentions that FPGAs are less competitive with firmware-programmed application specific integrated circuits (ASIC) and application-specific standard products (ASSP) but it could stay in the market by having faster transceivers and faster fabric in smaller and less expensive devices. It concludes that moving to an application directed FPGA, with certain functional blocks hard-embedded in a field-programmable chip is necessary to meet the industry's needs.

The article discusses the costs and various digital and analog methods of testing integrated circuits (IC). While the cost of automatic-test-pattern generation (ATPB), built-in self-tests (BIST) and structural techniques have been under control, analog complexity continues to raise the cost of testing analog and mixed-signal (AMS) circuits. Analog testing strategies include characterization, the use of BISTs and structural testing. Adaptive testing involves the use of statistical analysis of production test data.

The article reports on the triple-play high-definition (HD) service of U.S. cable and telephone operators. The new very-high-speed-digital-subscriber-line (VDSL) technology will provide voice, data, and video service to telephone, cable, and wireless customers. The author discusses traffic shaping and a fast and thorough packet inspection as possible solutions to networking problems like running out of bandwidth and security. He cites that new generation silicon chips will require a faster speed and a capacity to perform deep packet inspection.

The article discusses the board design that is accessible for debugging and verification during the development of the product. Particular focus is given to a systematic approach for attaining this goal, which involves understanding the functions of the board and preparing measures to verify the proper state of these functions. Also discussed is the advantage of field-programmable gate arrays (FPGAs) over central processing units (CPUs).

The article offers guidance on outsourcing an integrated circuit design (IC). It discusses the importance of selecting the right vendor as well as the creation of adequate project management structure as necessary conditions to the successful design of an IC. The cited criteria in selecting a vendor are technical capability, scalability, and economics while information included in the statement of work include price negotiations and architectural descriptions. Also noted is the importance of having different shops do the design work and the verification.

This article explains that the recession has stimulated interest in programmable analog chips and it is expected that the demand for them will increase. It explores several challenges facing programmable analogs, including what design method to use with these chips and the use of traditional-intuition based analog. Also discussed are various solutions to these challenges, such as using metaphor for understanding the chips.

The article discusses the use of a universal serial bus (USB) 3.0 as an interface for cables and connectors. Standard Microsystems Corp. vice president of engineering Mike Pennell relates that the connection between a USB 3.0 and device controller is more complex than fire-retardant (FR)-4 material. The author shares that the process of getting a data stream through a USB 3.0 channel depends on the transmitter-emphasis circuit.

The article focuses on the power estimation of field-programmable gate array (FPGA) designs by designers. It suggests that designers should incorporate accurate power estimates in the whole design process so as to achieve power-management proficiencies. Raj Kothandaraman, Wipro Technologies' lead FPGA designer, remarks that power estimation begins at the specification phase.

The article discusses the need for field-programmable gate array (FPGA) designers to estimate, monitor, and measure power consumption. It describes how Wipro Technologies developed an internal design method that allows teams to collect data on power estimates for various kinds of structures and algorithm decisions. Early power estimation in FPGA design can be refined depending on knowledge of the process or application. Also explained is the use of power analyzers that can read data from design simulation tests.

The article discusses issues related to the verification of a logic design for field programmable gate array (FPGA) in Europe. It investigates the role of simulation in an FPGA design, as well as its advantages and limitations. It outlines the strengths and weaknesses of in-FPGA verification which are claimed to complement those of simulation. How design teams balance simulation and FPGA-based testing is examined.

The article explores whether the role of simulation in a Field-Programmable Gate Array (FPGA) design be the same as it is in an Application-Specific Integrated Circuit (ASIC) design and whether the verification team still, at some point, just put the design in the target FPGA and start testing it at speed. People who work most closely with FPGA users were asked in order to find out what design teams are doing today. Few ASIC design teams who use FPGA prototypes in their verification processes were also asked for their views. INSET: SHINING SOME LIGHT ON THE COVERAGE GAPS.

The article offers information on verification metrics. It stresses that the manager must be able to blend a variety of metrics into one picture and that he or she must understand what each sort of metric really means. It states that functional coverage is the earliest means of measuring verification and is the mainstay of many design teams. With this, the article suggests that the manager should look at the frequency of bug reports and assemble a team that could start with functional-coverage metrics. It also discusses how other companies manage and collect verification-coverage metrics.

The article analyzes the integration of multiple processors with the systems on chips (SOCs). Architects added application accelerators for performing specific and clearly defined tasks with greater speed and less energy. Intel makes use of multiple simpler central processing units (CPUs) on one die that allows it to save on energy cost of higher clock frequencies. The operating frequency needed for each multiple processor core is reduced through splitting a set of tasks among the cores. SOCs' evolution possesses power and scaling advantages while debugging is considered the biggest challenge in using multiple cores.

The article contends that advanced power management techniques in integrated circuit design can cause vast difficulties in the verification process. According to the author, most logic-level power-management techniques are implemented to reduce static and dynamics power. To reduce static power, electronic circuit designers use high-threshold-voltage transistors as much as possible, reduce the voltage on the supply pins, or turn the power supply off altogether. For reducing dynamic power, the design engineer's options are to reduce the supply voltage or reduce the frequency, according to the author.

The article discusses the misconception of within the electronic-system-level (ESL) design. According to the author, many failures, false claims and overly-limited tools later and several designers put ESL in the same category as some commentators once classed gallium arsenide including a permanent technology of the future. However, this claims is inaccurate as some of those early claims success.

The article explores the roles of electronic-system-level (ESL) technology in electronic design flows. ESL tools are used by project leaders to develop a software-based virtual prototype, by integrating it into the driver code and testing the software system. At MC2 Technology Group, ESL is used to develop the correct algorithms for digital-signal processing (DSP) and field programmable gate arrays (FPGA). Meanwhile, the intellectual-property (IP)-development group within Synopsys used ESL to develop a virtual-prototyping facility from its product line to manage both hardware and software components.

The article focuses on the challenge in integrating the small-signal radio frequency (RF) circuits of various radios into the System on Chip (SoC), and the advantage of using silicon intellectual property ( IP). It relates that IP reuse is absolutely necessary to meet schedules and maintain reasonable design complexity. Moreover, it asserts that although reusing IP has become common for some very-high-frequency blocks, design reuse is virtually unknown for RF circuits in radio applications.

The article examines whether reusing silicon intellectual property (IP) is possible to meet schedules and maintain reasonable design complexity, as system on chip (SOC) for mobile devices integrate radio circuits. At stake in these examination is a large fraction of the die area in the mobile-system SOC which occurs because radios tend to be large and because the advanced handset will require lots of radios on one SOC. The examination showed that SOC development depends on IP reusability and that radio frequency (RF) circuitry is notoriously hard to reuse for some very compelling reasons. It also found that the reuse of third-party blocks is likely to be difficult and slow to emerge.

The article examines problems faced by a systems on a chip (SOC) team in integrating high-speed serial input/output (I/O) blocks. The potential of high-speed serial I/O as an alternative to the wide parallel buses that were common on processor chips and SOC has been observed by system designers. Among the challenges faced by an SOC team is the physical interface. According to Hemant Shah of Cadence, the only means one may feel good about his intellectual property (IP) selection is to model the block in the board environment where the chip will be used.

The article discusses issues related to evaluating and calibrating system on chips (SOCs). According to the article, chip designers must be able to create autocalibration methods that can compensate critical circuits for process, voltage, temperature, impedance and noise variations while the chip is in use. William Orme, general manager of the CoreInsight debugging program at ARM, says that designers resisted adding to the core area for debug but eventually, in-core debug became cost-effective in the overall cost of the SOC. INSET: MEMS ACCELEROMETERS NEED INSTRUMENTATION, TOO.

The article presents information on the how design teams are choosing the system-on-chip processes, according to a number of design managers and service providers. Because a chip has a technical requirement that dictates a particular process choice, Bob Klosterboer believes high interface-voltage levels sometimes dictate a solution. Designers can address the issue of the need for large amounts of integrated nonvolatile memory by adding modules to a standard logic process. Finding the best process involves lifetime costs, intellectual property (IP) needs, design requirements and analysis of risk.

The article addresses the changes in the interconnect architecture of system on chip (SOC). There are increasing indications that the centralized-bus approach to SOC interconnect is simply becoming unpopular. As the number of processing nodes on an integrated circuit increases and as the data traffic that those nodes produce or consume increases and becomes more varied, the demand for raw bandwidth becomes a problem. The traditional tool for provisioning the classic SOC bus is Microsoft Excel. The problem of examining and provisioning on-chip interconnect is a matter of providing the right kind of interconnect between just the right blocks.

The article discusses the implications of the development of fourth generation wireless service (4G) for System-on-Chip (SoC) architectures. 4G could be the fountainhead of an entirely new way of thinking about SoC architectures or it could drive a simple evolution of the modern baseband wireless integrated circuits (IC). It could lead to entirely new kinds of mobile services for consumer clients.

The article focuses on the fourth generation of wireless service or 4G which could be the fountainhead of a new way of thinking about system-on-chip (SOC) architectures or the start of the evolution of baseband wireless integrated circuits. It predicts that the mobile device will somehow achieve a downlink peak data rate of at least 100 Mbps. It cites that one challenge that will be faced by evolutionary architecture is MIMO which is used to improve the quality of the wireless link. It offers scenarios on the future of 4G.

The article talks about the demand that system architects at least consider the integration of the radio hardware into a system on chip (SOC). It is inferred that the demand raises some critical questions, such as which architectures are the best to employ for the receiver and the transmitter. It states that the architect reaches an informed decision only by assessing various factors, including market expectations, lifecycle cost, performance requirements and project risk. According to the article, many of the problems associated with radios on SOC respond to the aggressive use of digital circuitry for calibration and control and to design experience.

The article discusses the need for electronic designers to develop system-on-chip (SOC) with provisions for debugging. The author discusses the different problems presented by testing and debugging integrated circuits. With the growing complexity of SOC designs, design teams are dedicating additional planning, implementation and silicon area to circuitry that supports debugging rather than test. Electronics company Broadcom assigned a corporate-level team of about 70 engineers who work with all the chip-design teams in the company on both debugging and testing, according to Kris Hublitz, senior director of test-development engineering.

The article discusses major concerns facing camera designers in choosing from partitioning options when using complimentary metal oxide semiconductor (CMOS)-image sensor technology. The technology offers a wide range of partitioning options, from multichip boards to cameras-on-chip designs. Some of the factors affecting partitioning desion include the physical limitations posed by cameras' packaging restrictions, boundaries of intellectual property ownership or design team competence, influence of underused resources in the camera and algorithm.

The article discusses the testing of audio integrated circuits in the U.S. System-on-Chip (Soc) platforms designers are now assessing the new challenge and joining experienced audio-integrated circuits designers who have lived with it. The manufacturing test for these chips will depend on their architecture and will need as science. Design for test will take on a new importance for audio functions as user's expectations for high fidelity increase.

The article discusses the challenging task being faced by system-on-chip (SOC) designers and test engineers as they are expected to significantly increase high-definition (HD) video capability and audio quality in set-top boxes, television monitors, disk players and mobile media players. According to the author, circuit design is not the only problem encountered in high-resolution audio development. Factors such as characterization and testing should also be considered, the author added. Moreover, the quality of high-end audio is difficult to quantify even under characterization standards and almost impossible to verify in a manufacturing-test environment.

The article talks about the problems associated with achieving timing closure in system-on-chip design. It presents opinions from several design shops and design teams regarding the difficulties involved in timing closure. Some of the factors and issues associated with achieving timing closure are higher speeds, the use of third-party and the pursuit of power management. Managers provided steps for taming timing closure, which include lessening the design to lower level of abstraction, projecting timing on the level of abstraction, fixing margins to reduce net failures and fixing the outlying nets. Jay Jayaprakash of Open-Silicon identified a pyramid they use in their timing closure strategy. He stressed that managers should agree with the strategy of their customers. INSETS: STATISTICAL ANALYSIS TAKES ON TIMING VARIATIONS;FOR DRAM, TIMING CLOSURE IS A DIFFERENT GAME.

The article focuses on consumer electronics. There is an increased pressure among consumer-electronics design teams. This is due to global competition, low entry barriers to start-ups and emerging local wireless and media standards. According to Arun Mittal, senior vice president and general manager of the power-management and supply business unit of Infineon, there are two kinds of schedule pressure. He says in some cases the vendor is already present in the market enhancing the offering. However, in other cases, the customer is entering a new market area and must hit a particular window such as the Christmas gift-buying season. INSET: DRM LOOMS AS NIGHTMARE FOR DESIGNERS.

The article offers information on virtualization. A system is virtualized when it has undergone three steps: when a boundary has isolated the system from its environment, when designers have identified the inputs and outputs that cross the boundary along with the transforms that produce the outputs and when designers are able to produce a functionally equivalent block or one that accepts the same inputs and produces the same outputs under the same circumstances within an electronic system. Virtualization is expected to unleash a revolution as great as that of the microprocessor in the future.

The article explores the challenges posed by the growing demand for video on handheld devices to system designers and architects. Fast Forward Video is an original equipment manufacturer which has been building JPEG-based digital video-recording subsystems since 1999. Silicon vendors face having to provide not only full systems built on their chips, but also multiple levels of access to reference designs. Some functions of the underlying architecture include the viability of providing different levels of access to a reference design, the effectiveness with which the user can manipulate the design and the range over which they can configure the design.

The article provides information on chip designs. Open-Silicon has added a significant number of stages to its design flow to ensure manufacturability at the 90-nanometer process. Design understanding is diffusing down toward process engineering. Foundry engineers kept finding new problems with each design and creating new design rules to prevent them. There are two rulings used by the design team including mandatory and recommended rules. Moreover, there are problems that are being encountered by design teams. These include impractical compliance and impossibility of important structures. INSET: DFM RAISES GLOBAL ISSUES.

This article highlights the growing skepticism among microprocessors designers about the future of system on chip (SOC) technology. SOC is the technology being used for tool integration in microprocessor design and development. The advance of SOC technology is made by vacuuming up all the digital functions in a system until there is nothing of important cost or function left outside the microprocessor. Technology forecasters have identified precision analog or radio frequency (RF) blocks as the next frontier for SOC integration. Manufacturers of cellular-phone handsets, such as Infineon and Texas Instruments, are already exploring RF blocks for SOC integration.

The article focuses on Xilinx's Spartan-6 and Virtex-6, two complete families of field-programmable gate arrays (FPGAs) having a common tool set and a common pool of Internet Protocol (IP). The two products are different embodiments of the same concept for different product points. The story behind the development of the two products is described. According to executive Victor Peng, customers said they could see the company's organizational boundaries in their products.

The article focuses on the efforts of the design team at SiGe Semiconductor to produce the SE2593A radio frequency front end module that is both cost effective and competitive. A background is given on the implementation of the A-band amplifier in gallium arsenide and selection of pseudomorphic high electron mobility transistor process. Also a vital part of the design process which the team performed is an extensive electromagnetic simulation. The results showed the convergence of the multitrack design flow and reduction of customer support problem.

The article focuses on the collaboration of Altera Corp. with Taiwan Semiconductor Manufacturing Co. for the development of 40-nanometer Stratix IV field programmable gate arrays (FPGA). An overview of the chip design effort, which includes the exploration of a system level simulation environment for understanding the impact of process, circuit design and design tool choices, along with the creation of test chips, is provided. Also a vital part of the collaboration is the intellectual property design process parallel with the chip design effort.

The article discusses the view of Jack Sun, vice president of research and development of Taiwan Semiconductor Manufacturing Corporation (TSMC), on the relationships between foundry engineers and chip-design teams. He said that variability is the main problem in the foundry-design relationship but stated that there are models to characterize the variations. Sun shared that TSMC is using immersion lithography, which can produce accurate prediction on the actual shapes of silicon. He said that TSMC is also using a conventional silicon-gate and silicon-oxide-dielectric gate stack.

The article discusses the virtualization of electronic system, which is considered the fundamental force that has motivated the evolution of the electronics industry. The author expresses that virtualization has made it possible for electronic systems to act as if they had hardware and simulate reality which has made them more intelligent. He added that these capabilities have intensified the growth of electronics and brought new levels of insight to engineers and scientists.

The article reports on the availability of the BA22 processor core that is preconfigured by Beyond Semiconductor through a license from Cast Inc. (CI). It discusses the claims of CI on the density of instruction stream, low implementation and power consumption of the preconfigured core that has an Eclipse software. It focuses on the similarity of the application throughput of the processor to a Cortex R4.

The article features the Bluetooth radio released by Orca Systems.

The article discusses ways of reducing complexities in computer systems by resorting to reusable intellectual property (IP) as new level of abstraction for system-on-chip (SOC) design. It explains how IP blocks are abstractions of register-transfer level (RTL) inside them and how they can be fitted together for creating SOC including how IP-centric flow is effective from traditional flow. It highlights ways of selecting IP and explains how assembly of IP is essence of IP-centric flow.

The article presents the high-k/metal-gate (HKMG) stack as a critical application for film deposition. It indicates that the integrated circuit (IC) industry is at an early stage with HKMG, a process where one oxide film is replaced with four or five complete processes which include two layers of oxide, atomic-layer deposition of hafnium-oxide and nitridization. It suggests the necessity of being able to deposit unimaginably thin films over complex topology to create transistors.

The article offers information on series of equipment and chemistry changes introduced by Applied Materials for increasing transistor performance in peripheral circuitry of advanced dynamic random-access memory (DRAM). The aim of changes, it says, are on three components including the Versa extremely low-resistance (XLR) Tungsten physical vapor-deposition (PVD) tool and the decoupled-plasma-nitridation (DPN) high-dose (HD) tool. It also notes the high-aspect-ratio (HAR) Cobalt PVD system.

The article reports on an automated process that was recently launched by fabless semiconductor vendor KaiSemi Ltd. to convert field-programmable gate array (FPGA) to drop-in application-specific integrated circuit (ASIC) replacements. The first step in the process is a design review, in which the customer provides FPGA netlist and a standard-delay-format (SDF) file, functional test vectors, and pin definitions. Successful operation of the design in production and the completeness of the test-vector set are indicators of the convertibility of a netlist.