INTEGRATING HIGH-SPEED SERIAL I/O: NO SNAP FOR SOC DESIGNERS.

The article examines problems faced by a systems on a chip (SOC) team in integrating high-speed serial input/output (I/O) blocks. The potential of high-speed serial I/O as an alternative to the wide parallel buses that were common on processor chips and SOC has been observed by system designers. Among the challenges faced by an SOC team is the physical interface. According to Hemant Shah of Cadence, the only means one may feel good about his intellectual property (IP) selection is to model the block in the board environment where the chip will be used.