138 results on '"Sturtevant, John"'
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2. Compact modeling of stochastics and application in OPC
3. EUV full-chip curvilinear mask options for logic via and metal patterning
4. Implant layers: leading-edge noncritical lithography. (Feature)
5. Rapid full-chip curvilinear OPC for advanced logic and memory
6. Probability prediction of EUV process failure due to resist-exposure stochastic: applications of Gaussian random fields excursions and Rice's formula
7. Stochastic model prediction of pattern-failure
8. Process window-based feature and die failure rate prediction
9. Impact of aberrations in EUV lithography: metal to via edge placement control
10. Akaike information criterion to select well-fit resist models
11. Full chip two-layer CD and overlay process window analysis
12. Edge placement errors in EUV from aberration variation
13. Aerial image metrology for OPC modeling and mask qualification
14. Effective use of aerial image metrology for calibration of OPC models
15. Interlayer verification methodology for multi-patterning processes
16. Importance sampling in Gaussian random field EUV stochastic model for quantification of stochastic variability of EUV vias
17. Bayesian analysis for OPC modeling with film stack properties and posterior predictive checking
18. Modeling metrology for calibration of OPC models
19. Bayesian inference for OPC modeling
20. Multi-layer VEB modeling: capturing interlayer etch process effects for multi-patterning process
21. Enabling yield at 45nm: managing process variability
22. Statistical modeling of SRAM yield performance and circuit variability
23. Fast source optimization by clustering algorithm based on lithography properties
24. A holistic methodology to drive process window entitlement and its application to 20nm logic
25. An efficient lithographic hotspot severity analysis methodology using Calibre PATTERN MATCHING and DRC application
26. Efficient etch bias compensation techniques for accurate on-wafer patterning
27. A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method
28. Topography aware DFM rule based scoring for silicon yield modeling
29. 20nm CMP model calibration with optimized metrology data and CMP model applications
30. A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT)
31. Automation for pattern library creation and in-design optimization
32. A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction
33. Design layout analysis and DFM optimization using topological patterns
34. Incorporating DSA in multipatterning semiconductor manufacturing technologies
35. Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
36. Quantitative evaluation of manufacturability and performance for ILT produced mask shapes using a single-objective function
37. Breaking through 1D layout limitations and regaining 2D design freedom Part I: 2D layout decomposition and stitching techniques for hybrid optical and self-aligned multiple patterning
38. Layout dependent effects analysis on 28nm process
39. Standard cell design in N7: EUV vs. immersion
40. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
41. Layout optimization with assist features placement by model based rule tables for 2x node random contact
42. Yield-aware mask assignment using positive semi-definite relaxation in LELECUT triple patterning
43. An efficient auto TPT stitch guidance generation for optimized standard cell design
44. Finding practical phenomenological models that include both photoresist behavior and etch process effects
45. Walk the walk
46. 14-nm photomask simulation sensitivity
47. Technology-design-manufacturing co-optimization for advanced mobile SoCs
48. Yield-aware decomposition for LELE double patterning
49. Robust and automated solution for correcting hotspots locally using cost-function based OPC solver
50. Decomposition-aware layout optimization for 20/14nm standard cells
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