Search

An accurate estimation of the success probability and data complexity of linear cryptanalysis is a fundamental question in symmetric cryptography. In this paper, we propose an efficient reconfigurable hardware architecture to compute the success probability and data complexity of Matsui's Algorithm 2 which is the central technique in linear cryptanalysis for block ciphers. Using this dedicated architecture, we are able to investigate the complexity of the algorithm for up to 40-bit block ciphers for low-correlation lineaer approximations and high advantages. Performing experiments on larger block lengths ensures that any empirical observations are not due to differences in statistical behavior for artificially small block lengths. Rather surprisingly, we observed in previous experiments a significant deviation between the theory and practice for Matsui's Algorithm 2 for larger block sizes in a vast range of parameters. The new hardware architecture allows us to verify the existing theoretical models for the complexity estimation in linear cryptanalysis. The designed hardware architecture is realized on two Xilinx Virtex-6 XC6VLX240T FPGAs for smaller block lengths, and on RIVYERA platform with 128 Xilinx Spartan-3 XC3S5000 FPGAs for larger block lengths. [ABSTRACT FROM PUBLISHER]

In this paper a novel modular superscalar execution core is presented for a medium grain reconfigurable hardware. The processor can be configured for varying path widths, reservation station depths, and reorder buffer sizes with minimal redesign effort. An analysis comparing the superscalar core with a five-stage execution core shows that a speedup of 2.073 can easily be achieved while increasing area by only 29%. [ABSTRACT FROM PUBLISHER]

We present a practical FPGA-based accelerator for solving Boolean Satisfiability problems (SAT). Unlike previous efforts for hardware accelerated SAT solving, our design focuses on accelerating the most time consuming part of the SAT solver — Boolean Constraint Propagation (BCP), leaving the choices of heuristics such as branching order, restarting policy, and learning and backtracking to software. Our novel approach uses an application-specific architecture instead of an instance-specific one to avoid time-consuming FPGA synthesis for each SAT instance. By avoiding global signal wires and carefully pipelining the design, our BCP accelerator is able to achieve much higher clock frequency than that of previous work. In addition, it can load SAT instances in milliseconds, can handle SAT instances with tens of thousands of variables and clauses using a single FPGA, and can easily scale to handle more clauses by using multiple FPGAs. Our evaluation on a cycle-accurate simulator shows that the FPGA co-processor can achieve 3.7-38.6x speedup on BCP compared to state-of-the-art software SAT solvers. [ABSTRACT FROM AUTHOR]

There is a growing demand for high-performance computation cores in embedded devices built over reconfigurable hardware. As a result, various soft core architecture techniques have been proposed, each targeting different application classes. This work presents SPREX, an FPGA-friendly Runahead soft processor architecture that targets applications with unstructured instruction level parallelism. The architecture of choice for such applications has traditionally relied on a mix of superscalar, out-of-order, and speculative execution. Unfortunately, the implementation of these techniques does not map well on reconfigurable hardware. This work shows that by exploiting the key characteristics of reconfigurable fabrics, and by tuning the architecture for the embedded environment, a fast and practical Runahead soft processor is viable. Runahead has been shown to offer many of the benefits of conventional architectures for the applications this work targets. We show that the proposed Runahead architecture improves performance of a simple 5-stage pipeline by 9% on the average and by as much as 36%. [ABSTRACT FROM PUBLISHER]

Soft errors are a reliability threat for reconfigurable systems implemented with SRAM-based FPGAs. They can be handled through fault tolerance techniques like scrubbing and modular redundancy. However, selecting these techniques statically at design or compile time tends to be pessimistic and prohibits optimal adaptation to changing soft error rate at runtime. We present the GUARD method which allows for autonomous runtime reliability management in reconfigurable architectures: Based on the error rate observed during runtime, the runtime system dynamically determines whether a computation should be executed by a hardened processor, or whether it should be accelerated by inherently less reliable reconfigurable hardware which can trade-off performance and reliability. GUARD is the first runtime system for reconfigurable architectures that guarantees a target reliability while optimizing the performance. This allows applications to dynamically chose the desired degree of reliability. Compared to related work with statically optimized fault tolerance techniques, GUARD provides up to 68.3% higher performance at the same target reliability. [ABSTRACT FROM AUTHOR]

The ever-growing complexity of today's embedded system, and the extra functional requirements like temporal or energy consumption constraints are one of the more exciting challenges for today's embedded system designers. Keeping the design space as open as possible, especially with regards to the hardware (HW) or software (SW) assignments of the system functions, are key points to minimize the project risk. In this paper, we propose a HW/SW Component-Based System Engineering framework for Real-Time Operating Systems (RTOS) services. The proposed approach combines the flexibility and power of software component based approach with the adaptability and performance of reconfigurable hardware architectures. This study focuses on the RTOS timing services case study. We show in this paper the value of such an approach especially in a context of precise time-driven requirements. [ABSTRACT FROM PUBLISHER]

This paper presents a method to virtualize the communications into a distributed heterogeneous embedded Multiprocessor System-on-Chip (MPSoC) platform containing reconfigurable hardware computing units. We propose a new concept of middleware, implemented in software and in hardware to provide the designer a single programming interface. The middleware offers some mechanisms like access to distant operating system (OS) services and interprocess communication. It abstracts both implementation and mapping. The embedded application then executes regardless of where or how processes are implemented. We are currently validating the concept on a real-time image processing application. [ABSTRACT FROM PUBLISHER]

This work presents the virtual environment implementation for project simulation and conception of supervision and control systems for mobile robots, which are capable of operating and adapting in different environments and conditions. The purpose of this virtual system is to facilitate the development of embedded architecture systems, emphasizing the implementation of tools that allow the simulation of the kinematic conditions, dynamic and control, with real time monitoring of all important system points. To accomplish this, an open control architecture is proposed, integrating the two main techniques of robotic control implementation in the hardware level: systems microprocessors and reconfigurable hardware devices. The utilization of a hierarchic and open architecture, distributing the diverse actions of control in increasing levels of complexity, the use of resources of reconfigurable computation are made in a virtual simulator for mobile robots. The validation of this environment is made in a nonholonomic mobile robot and in a wheelchair; both used an embedded control rapid prototyping technical for best navigation strategy implementation. After being tested and validated in the simulator, the control system is programmed in the control board memory of the mobile robot or wheelchair. In this way, an economy of time and material are obtained, sooner validating the entire model virtually for later operating the physical implementation of the navigation system. [ABSTRACT FROM PUBLISHER]

The Particle Swarm Optimization or PSO is a heuristic based on a population of individuals, in which the candidates for a solution of the problem at hand evolve through a simulation process of a social adaptation simplified model. Combining robustness, efficiency and simplicity, PSO has gained great popularity as many successful applications are reported. The algorithm has proven to have several advantages over other algorithms that based on swarm intelligence principles. The use of PSO solving problems that involve computationally demanding functions often results in low performance. In order to accelerate the process, one can proceed with the parallelization of the algorithm and/or mapping it directly onto hardware. This paper presents a novel, massively parallel PSO co-processor which was implemented by using reconfigurable hardware. The implementation results show that the proposed architecture is very promising as it achieved superior performance in terms of execution time when compared to the direct software execution of the algorithm. [ABSTRACT FROM PUBLISHER]

Heterogeneous systems show a lot of promise for extracting highperformance by combining the benefits of conventional architectures with specialized accelerators in the form of graphics processors (GPUs) and reconfigurable hardware (FPGAs). Extracting this performance often entails programming in disparate languages and models, making it hard for a programmer to work equally well on all aspects of an application. Further, relatively little attention is paid to co-execution--the problem of orchestrating program execution using multiple distinct computational elements that work seamlessly together. We present Liquid Metal, a comprehensive compiler and runtime system for a new programming language called Lime. Our work enables the use of a single language for programming heterogeneous computing platforms, and the seamless co-execution of the resultant programs on CPUs and accelerators that include GPUs and FPGAs. We have developed a number of Lime applications, and successfully compiled some of these for co-execution on various GPU and FPGA enabled architectures. Our experience so far leads us to believe the Liquid Metal approach is promising and can make the computational power of heterogeneous architectures more easily accessible to mainstream programmers. [ABSTRACT FROM AUTHOR]

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. Up to 30 SpaceWire interfaces, 5 copper-based SpaceFibre interfaces, and 270 GPIOs can be realized and combined with one to five dynamically reconfigurable Xilinx FPGAs and up to 20 GByte of working memory. The implemented approach for dynamic reconfiguration enables partial reconfiguration at 400 MByte/s. Blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. [ABSTRACT FROM PUBLISHER]

Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in different application domains. However little has been explored in the avionic communication domain, where halting the system during runtime for changing the hardware is non-trivial. In this paper we present a runtime reconfigurable architecture using I/O Intellectual Property (IP) cores, used in avionic applications. The system provides a modular I/O interface for communication, using an FPGA Mezzanine Card (FMC). User application can dynamically install and execute the necessary hardware for communication with external avionic sub-systems using FMC. The system thus provides a highly modular and cost effective autonomous solution for an embedded avionic communication system using Dynamic Partial Reconfiguration (DPR). The above described solution has been tested using a Xilinx ML605 prototyping board providing a software interface with a Xilinx Microblaze processor core. The architecture has been evaluated with the JPEG application in terms of area utilization, reconfiguration latency and execution time. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization. [ABSTRACT FROM PUBLISHER]

Modern compute systems continue to evolve towards increasingly complex, heterogeneous and distributed architectures. At the same time, functionality and performance are no longer the only aspects when developing applications for such systems, and additional concerns such as flexibility, power efficiency, resource usage, reliability and cost are becoming increasingly important. This does not only raise the question of how to efficiently develop applications for such systems, but also how to cope with dynamic changes in the application behaviour or the system environment. The EPiCS Project aims to address these aspects through exploring self-awareness and self-expression. Self-awareness allows systems and applications to gather and maintain information about their current state and environment, and reason about their behaviour. Self-expression enables systems to adapt their behaviour autonomously to changing conditions. Innovations in EPiCS are based on systematic integration of research in concepts and foundations, customisable hardware/software platforms and operating systems, and self-aware networking and middleware infrastructure. The developed technologies are validated in three application domains: computational finance, distributed smart cameras and interactive mobile media systems. [ABSTRACT FROM PUBLISHER]

In this article the architecture of intrusion detection system based on the use of a hardware implementation of the classification of network packets, which allows you to increase the speed of processing information to protect against network intrusions during the operation in information and communication systems. [ABSTRACT FROM AUTHOR]

Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling mechanism and the corresponding implementations for fixed-point adders and multipliers. We implemented the architecture on Xilinx Virtex-5 XC5VLX110T FPGAs, and the results show that the area and latency overheads are 1% ~ 24% depending on the structure and configuration. This implies the overhead can be minimized if the ALU structure and configuration are chosen carefully for specific applications. As a case study, we apply this architecture to binary cascade iterative refinement (BCIR). 4X speedup is observed in this case study. [ABSTRACT FROM PUBLISHER]

Bio-inspired hardware has made great progress in the field of fault-tolerance during the past decades. This paper presents a novel architecture, the virtual-PIG (VPIG), due to the lack of an appropriate platform for the bio-inspired hardware research. The virtual-PIG is derived from PIG (Processing Integrated Grid) and RISA (Reconfigurable Integrated System Array). The VPIG cluster consists of a MCU and four cells which are similar to the PIG. The architecture of the VPIG is analyzed in details, and its FPGA implementation is also described. It is noteworthy that our MCU has the capability of the customizable instruction. To verify the VPIG, three experiments were conducted, including self-replication, 1-bit full adder evolution and 2-bit counter with self-repair. The experimental results show that our proposed VPIG has the feature of self-replication, self-evolution and self-repair, making it very suitable for bio-inspired hardware applications. [ABSTRACT FROM PUBLISHER]

Unlike other digital signal processing techniques such as the Fast Fourier Transform for one-dimensional (1D) and two-dimensional (2D) data (FFT1 and FFT2) that assume signal linearity and stationarity, the Hilbert-Huang Transform (HHT) utilizes relationships between arbitrary signal's local extrema to find the signal instantaneous spectral representation. This is done in two steps. Firstly, the Huang Empirical Mode Decomposition (EMD) is separating input signal of one variable s(t) into a finite set of narrow-band Intrinsic Mode Functions IMF1(t), IMF2(t)… IMFk(t) that add up to the signal s(t). The IMFs comprise the signal adaptive basis that is derived from the signal, as opposed to artificial basis imposed by the FFT or other heritage frequency analysis methods. Secondly, the HHT is applying the Hilbert Transform to each IMFi(t) signal constituents to obtain the corresponding analytical signal Si(t). From the analytical signal the HHT generates the Hilbert-Huang Spectrum. Namely, a single instantaneous frequency ωi(t) for signal Si(t) at each argument t is obtained for each of the k-Huang IMFs. This yields the Hilbert-Huang spectrum ω(IMF1(t)), ω(IMF2(t))… ω(IMFk(t)) at each domain argument t for s(t) that was not obtainable otherwise. The HHT and its engineering implementation — the HHT Data Processing System (HHT-DPS) for 1D was developed at the NASA Goddard Space Flight Center (GSFC). The HHT-DPS is the reference system now used around the world. However, the state-of-the-art HHT-DPS works only for 1D data, as designed, and it is not a real-time system. This paper describes the development of the reference HHT Data Processing Real-Time System (HHTPS-RT) with 2D capabilities or HHT2 to process large images as the development goal. This paper describes the methodology of research and development of the new reference HHT2 Empirical Mode Decomposition for 2D (EMD2) system and its algorithms that require high capability computing. It provides this system prototype test results and also introduces the HHT2 spectrum concepts. It concludes with suggested areas for future research. [ABSTRACT FROM PUBLISHER]

A Trusted Platform Module (TPM) is a microcontroller-based chip, which provides a hardware-based security to the user's data, cryptographic keys, and other secrets. For this purpose, the TPM is equipped with hardwired cryptographic engines such as RSA, SHA-1, and HMAC that rely on correspondingly uncompromised cryptographic algorithms. For example, the RSA (asymmetric) engine on the TPM utilizes the RSA algorithm for encrypting and decrypting the user data as well as for signature generation and verification. Therefore, in case of a compromised RSA algorithm, not only the data protected by the TPM is lost but also the generated signatures become invalid. One possible solution to this problem is to replace (i.e., update) the RSA engine on the TPM with a new uncompromised asymmetric engine (e.g., ECC). However, the current TPMs are in general implemented as Application Specific Integrated Circuits (ASICs), thus they can not be modified after manufacture. Further, the update of an engine on the TPM leads to a loss of trust kept in the system before an update. Thus, in this contribution, we propose dedicated procedures for regaining the trust in the system after the RSA engine update utilizing the novel Sustainable Trusted Platform Module (STPM) architecture. [ABSTRACT FROM PUBLISHER]

In this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented to execute task requirements in a dynamic, flexible, efficient and adaptive way. In this technique not only the logic functions are modifiable (as in the case of Field Programmable Gate Array, FPGA) but also the physical position of the logic elements that form the circuit. Furthermore, a new technologic strategy that allows implementing large crossbars of memFETs is introduced. The memFET is an electrically reconfigurable field effect and resistive switching device that can be used to perform logic functions and memory blocks. Into an appropriate structure such as a crossbar array, memFET allows the dynamic logic reconfiguration of the crossbar and simplify both the design and the implementation of computing hardware. [ABSTRACT FROM PUBLISHER]

This paper presents a bio-inspired self-organizing approach for multicellular embryonic architecture, this approach is based on the lateral activation model from biological embryonic development theory. The lateral activation model clearly depicts intracellular chemical reaction and intercellular chemical exchange, and can provide the positional information for each cell, which is precisely the key source of the self-organizing capacity of real organism. This approach is different from the existing self-organizing approaches in other multicellular embryonic architectures. The cutting and dissociating experiments show that our multicellular embryonic architecture possesses powerful self-organizing capacities, including the dissociated-and-reaggregated capacity as hydrae. [ABSTRACT FROM PUBLISHER]

In this paper we propose a reconfigurable lightweight Internet Protocol Security (IPSec) hardware core. Our architecture supports the main IPSec protocols; namely Authentication Header (AH), Encapsulating Security Payload (ESP), and Internet Key Exchange (IKE). In this work, the cryptographic algorithms and their modes of operation, which are at the heart of the IPSec protocols, are implemented in hardware. Instead of re-implementing common IPSec configurations, which are deemed “too heavy” for pervasive devices, we evaluate efficient implementations of standardized and/or well-known lightweight and hardware-friendly algorithms. In particular, we examine different versions of Present, Gr⊘stl, Photon, and a very compact ECC core. As a consequence, we present IPSecco, a core with adequate security and only moderate resource requirements, making it suitable for lightweight devices. We selected the Xilinx Spartan family of Field Programmable Gate Arrays (FPGA) as target platform due its low-power footprint and reduced costs compared to other FPGAs. Our results show that it is possible to realize a high performance IPSec core even on members of the Spartan-3 family. [ABSTRACT FROM PUBLISHER]

One of the main drawbacks that significantly impacts the performance of dynamically reconfigurable systems (like FPGAs), is their high reconfiguration overhead. Configuration prefetching is one method to reduce this penalty by overlapping FPGA reconfigurations with useful computations. In this paper we propose a speculative approach that schedules prefetches at design time and simultaneously performs HW/SW partitioning, in order to minimize the expected execution time of an application. Our method prefetches and executes in hardware those configurations that provide the highest performance improvement. The algorithm takes into consideration profiling information (such as branch probabilities and execution time distributions), correlated with the application characteristics. Compared to the previous state-of-art, we reduce the reconfiguration penalty with 34% on average, and with up to 59% for particular case studies. [ABSTRACT FROM PUBLISHER]

This paper gives an analysis of how intelligent control can be used to provide a viable solution in the development of a control system for a reconfigurable machine tool (RMT). Firstly, the principle of RMT is briefly explained and the challenges that hinder their development are inspected in order to bring forward the gap to be addressed by this paper. The objective in this paper is to look at the work that has been done by other scholars in the field of control and then integrating the knowledge from these in developing an open architecture (OA) based intelligent control system suitable for the RMT. The key focus areas in this paper are the analysis of commonly used controllers in industrial applications and the benefits of using open architecture control (OAC). Lastly a proposal on how the fuzzy-PID controller can be used in an OAC system for the RMT is given. [ABSTRACT FROM PUBLISHER]

Widespread WLAN has used Advance Encryption Standard in Counter with Cipher Block Chaining Message Authentication Code Protocol (AES CCMP) as security services. As the next-generation WLAN adopts multiuser MIMO technology, multiple AES blocks are needed because this technology supports multiple packet transmission in parallel. To minimize the cost increase due to multiple AES blocks, we propose a pipelined AES architecture which processes multiple packets in parallel. By using a pipelined AES architecture instead of multiple AES blocks, efficiency is improved greatly since this pipelined architecture enables to sharing of the AES core. To find the optimum number of stages, we implemented pipelined architectures with various numbers of stages. The results show that a 3-stage pipeline is most efficient, and we achieve 4.34 Gpbs throughput with 2.39 Mbps/slice implementation cost of 1,817 slices and 0 BRAM using Xilinx Virtex 5. This efficiency results from the pipelined architecture's high operating frequency and resource sharing. [ABSTRACT FROM PUBLISHER]

Partial reconfiguration is possible to deliver virtually unlimited hardware resources since it enables dynamic allocation and de-allocation of tasks onto a reconfigurable architecture, while the rest tasks continue to operate. However, in order to benefit from this flexibility, partial reconfiguration has to be appropriately applied. Among others, the placement of partial configuration data is a critical issue since it affects the fragmentation of hardware resources. In this paper we introduce a novel methodology for supporting partial reconfiguration with the usage of a Just-in-Time (JIT) Compilation framework. Experimental results with a number of benchmarks showed that the introduced solution performs application P&R 7.34× faster, as compared to the state-of-the-art tools, while it also leads to significant lower fragmentation of hardware resources. [ABSTRACT FROM PUBLISHER]

This paper proposes a flexible programming model (FPM), which addresses the automatic parallel execution for functional tasks on heterogeneous multiprocessors. Guided by the simply annotated source codes, a front-end source to source compiler is provided to identify the parallel regions and generate the sources codes. A runtime middleware analyzes the inter-task data dependencies and schedules the tasks with renaming techniques automatically. FPM has been verified by the prototype built on state-of-art FPGA. Examples demonstrate that our model can largely ease the burden of programmers as well as uncover the task level parallelism. [ABSTRACT FROM PUBLISHER]

Adaptation of hardware in relation to the requirements of a specific application is well known and investigated in the domain of Field Programmable Gate Arrays (FPGA) based reconfigurable system architectures. In these system approaches, a number of predefined blocks, mainly accelerators for processors, are loaded from an external storage and are transferred to the FPGA configuration memory in order to manipulate the on-chip functionality. A novel approach is to adapt the micro architecture of a processor in order to achieve a temporal application-specific behavior. In combination with the well known techniques of dynamic reconfiguration of a FPGA, novel degrees of freedom are available for an energy efficient run-time dynamic system approach. This paper presents one adaptation mechanism, in which the pipeline depth is adapted according to the control flow and data flow of an application. The concept and also the realization are described and evaluated in terms of efficiency with some benchmarks. [ABSTRACT FROM PUBLISHER]

This paper describes a bio-inspired architectural approach to design highly adaptive and reconfigurable systems in the context of mobile robotics. The aim is to design the hardware architecture of an intelligent controller for a robot that exhibits several behaviors such as landscape learning, obstacle avoidance, path planning, sensory-motor control. The concerned robot evolves in an indoor unknown environment and uses the visual informations coming from its input sensors to reach its goal. The Embodied Computing approach presented in this paper is employed in this context to integrate the reconfiguration management as a part of the behavior of the global system. Thus the controller will be able to self-organize its reconfigurable processing elements in order to adapt its architecture to the environment and to the robot actions. We propose in this paper a hardware implementation of the approach based on artificial neural networks. We present the results of our first prototype onto the last technology of FPGA. [ABSTRACT FROM PUBLISHER]

The Phylogenetic Likelihood Function (PLF) is an important statistical function for evaluating phylogenetic trees. To this end, the PLF is the computational kernel of all state-of-the-art likelihood-based phylogenetic inference programs. Typically, it accounts for more than 85% of total execution time in such programs. We present a substantially improved hardware architecture for computing the PLF based on previous experiences with implementing the PLF on reconfigurable logic. Our new design is optimized for computing the PLF on four-state (DNA) input data. It is also adapted to the computational requirements of real-world tree inference programs and completely independent of the specific tree search algorithm at hand. Furthermore, we describe how our architecture can be modified and adapted to handle general n-state data, such as protein (20 states) or RNA secondary structure data (6, 7, or 16 states, depending on the model). Finally, we designed an interface mechanism such that our PLF hardware architecture can interact with the widely-used phylogenetic inference tool RAxML. We deploy FPGA technology to verify the correctness of the architecture and to evaluate performance. [ABSTRACT FROM PUBLISHER]

Coarse Grained Recongurable Multimedia Architectures(CGRMAs) have become increasingly important in recent years, due to its potential to greatly accelerate a wide variety of applications. The lack of compilation technology for all kinds of CGRMAs causes a bottleneck in the current design process. In this paper, we present a Level Depth Based Mapping (LDBM) algorithm, the objective is to support CGRMAs. Experimental results using LDBM on a typical CGRMAs show that the LDBM algorithm can get the less using time of reconfigurable cell array (RCA) and the fewer number of I/O edges between blocks than Level Based Mapping (LBM) based on the same pipelined architectures. On the other hand, LDBM can obtain the better utilization rate of RCA. [ABSTRACT FROM PUBLISHER]

During the last few years, there is an increasing interest in mixing software and hardware to serve efficiently different applications. This is due to the heterogeneity characterizing the tasks of an application which require the presence of resources from both worlds, software and hardware. Controlling effectively these resources through an integrated tool flow is a challenging problem and towards this direction only a few efforts exist. In fact, a framework that seamlessly exploits both resources of a platform for executing efficiently an application has not yet come into existence. Moreover, reconfigurable computing often incorporated in such platforms due to its high flexibility and customization, has not yet taken off due to the lack of exploiting its full capabilities. Thus, the capability of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) to be dynamically reconfigured, i.e. reprogramming part of the chip while other parts of the same chip remain functional, has not yet taken off even in small-scale basis. The inherent difficulty in using the tools to control this technology has kept it back from being adopted by academia and industry alike. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively and easily a system specification on a platform combining software and reconfigurable resources. The FASTER framework accepts as input a high-level description of the application and the architectural details of the target platform, and through certain steps it can enable the full use of the capabilities of the platform, while at the same time it should be flexible enough so as to balance efficiently performance, power and area. One of the main novelties is the incorporation of partial reconfiguration as an explicit design concept at an early stage of the design flow. We target different applications from the embedded, desktop and high-performance computing domains. In all cases we will demonstrate the effectiveness of the proposed framework in exploiting the inherent parallelism of applications and enabling the runtime adaptation of the platforms to the changing needs of the applications. [ABSTRACT FROM PUBLISHER]

Contrast enhancement is crucial to generating high quality images in the applications of image processing such as digital image or video photography, LCD processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a parameter-controlled reconfigurable architecture to decrease hardware cost and improve hardware utilization for the proposed contrast enhancement algorithm. The experiment results show that the proposed method can provide the average frame rate 48.23 fps at high definition resolution 1920 x 1080 which means the proposed hardware architecture can run in real-time. [ABSTRACT FROM PUBLISHER]

As the CPU/FPGA hybrid architecture becomes one of the most important forms, the research of the schedule on hybrid tasks is a hot-spot. The schedule approaches of hybrid tasks can be classified into two categories. One is about non-preemptive multitasking, the other is preemptive multitasking. For the second one, as it requires architecture support, the existing researches are fewer. This paper presents an architecture which supports preemptive multitasking, an algorithm to select the appropriate migration point and a new schedule algorithm based migration and also introduces naming service to deal with communication problems after tasks migrated. Experimental results show that the algorithm based migration increases acceptance rate for hardware tasks to 12.94\%.The architecture proposed can support the preempting well, and improve the performance. [ABSTRACT FROM PUBLISHER]

This Paper explores using a non-linear system to construct dynamic logic architecture-cellular neural networks (CNN). The proposed CNN schemes can discriminate the two input signals and switch easily among different 16 kinds of operational roles by changing parameters. Each logic cell performs more flexibly, that makes it possible to achieve complex logic operations and construct computing architecture with less logic cells. We also proposed a new formula of hysteresis CNN to ensure that the output is strict binary. [ABSTRACT FROM PUBLISHER]

In this paper we propose to apply the Dynamic Partial Reconfiguration (DPR) technology to embedded systems intended for Intelligent Environments. To reach this goal, we have developed a system based on a Field Programmable Gate Array (FPGA) in which high performance hardware modules can be reconfigured on-line according to the necessities of the system at each moment. Two different implementations have been carried out to measure the time required to reconfigure each module and also to measure the FPGA resources that can be saved if we keep configured only the modules that are required at each time. The Obtained results show how this technique offers advantages in cost, size and power when applied to embedded systems for intelligent environments. [ABSTRACT FROM PUBLISHER]

This paper presents a fully numeric amplitude-demodulation based technique to enhance simple electromagnetic analyses. The technique, thanks to the removal of the clock harmonics and some noise sources, allows efficiently disclosing the leaking information. It has been applied to three different modular exponentiation algorithms, mapped onto the same multiplexed architecture. The latter is able to perform the exponentiation with successive modular multiplications using the Montgomery method. Experimental results demonstrate the efficiency of the applied demodulation based technique and also point out the remaining weaknesses of the considered architecture to retrieve secret keys. [ABSTRACT FROM PUBLISHER]

Resource run-time managers have been shown particularly effective for coordinating the usage of the hardware resources by multiple applications, eliminating the necessity of a full-blown operating system. For this reason, we expect that this technology will be increasingly adopted in emerging multi-application reconfigurable systems. [ABSTRACT FROM PUBLISHER]

Financial engineering is a very active research field as a result of the growth of the derivative markets and the complexity of the mathematical models utilized in pricing the numerous financial products. In this paper, we present an FPGA-based parallel processor optimized for solving the Black-Scholes partial derivative equation utilized in option pricing which employs the two most widely used finite difference schemes: Crank-Nicholson and explicit differences. As our measurements demonstrate, the presented architecture is expandable and the speedup triggered is increased almost linearly with the available silicon resources. Although the processor is optimized for this specific application, it is highly programmable and thus it can significantly accelerate all applications that use finite differences computations. Performance measurements show that our FPGA prototype triggers a 5× speedup when compared with a 2GHz dual-core Intel CPU (Core2Duo). Moreover, for the explicit scheme, our FPGA processor provides an 8× speedup over the same Intel processor. [ABSTRACT FROM PUBLISHER]

Disparity estimation in stereoscopic vision is a vital step for the extraction of depth information from stereo images. This paper presents the hardware implementation of a disparity estimation system that enables good performance in both accuracy and speed. The architecture implements an adaptive support weight stereo correspondence algorithm, which integrates information obtained from image segmentation, in an attempt to increase the robustness of the matching process. The proposed system integrates optimization techniques that make the algorithm hardware-friendly and suitable for embedded vision systems. A prototype of the architecture was implemented on an FPGA, achieving 30 fps for 640×480 image sizes. The quality of the disparity maps generated by the proposed system is also better than other existing hardware implementations featuring fixed support local correspondence methods. [ABSTRACT FROM PUBLISHER]

The design of electric vehicles require a complete paradigm shift in terms of embedded systems architectures and software design techniques that are followed within the conventional automotive systems domain. It is increasingly being realized that the evolutionary approach of replacing the engine of a car by an electric engine will not be able to address issues like acceptable vehicle range, battery lifetime performance, battery management techniques, costs and weight, which are the core issues for the success of electric vehicles. While battery technology has crucial importance in the domain of electric vehicles, how these batteries are used and managed pose new problems in the area of embedded systems architecture and software for electric vehicles. At the same time, the communication and computation design challenges in electric vehicles also have to be addressed appropriately. This paper discusses some of these research challenges. [ABSTRACT FROM PUBLISHER]

Efficiently managing the parallel execution of various application tasks onto a heterogeneous multi-core system consisting of a combination of processors and accelerators is a difficult task due to the complex system architecture. The management of reconfigurable multi-core systems which exploit dynamic and partial reconfiguration in order to, e.g. increase the number of processing elements to fulfill the performance demands of the application, is even more complicated. This paper presents a special virtualization layer consisting of one central server and several distributed computing clients to virtualize the complex and adaptive heterogeneous multi-core architecture and to autonomously manage the distribution of the parallel computation tasks onto the different processing elements. [ABSTRACT FROM PUBLISHER]

Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set architecture (ISA) can be adapted to increase performance or reduce resource/power consumption. To benefit from this run-time flexibility automatic selection of an appropriate ISA for each function of a given application is envisioned. This demands a cycle-accurate simulator that is capable of measuring the performance characteristics of an ISA dependent on the target application. However, simulation speed of a cycle-accurate simulator of our reconfigurable VLIW-like processor instances featuring dynamic operation execution would become relatively slow due to the superscalar-like microarchitecture. Within this paper we address this problem by presenting our cycle-approximate simulator approach containing a heuristic dynamic operation execution and memory model that provides a good trade-off between performance and accuracy. Additionally, the simulator features measurement of instruction level parallelism (ILP) that could be theoretically exploited by VLIW processor instances running on our architecture. The theoretical ILP could be used as an indicator for the ISA selection process without the need to simulate any combination of the different ISAs and applications. [ABSTRACT FROM PUBLISHER]

Biologically Inspired Computing places its emphasis on robustness, adaptability, and emergent organization considering the interaction of many processes. Bio-inspired algor [ABSTRACT FROM PUBLISHER]

Programmable hardware built on a regular architecture can partially alleviate the problem of increased defect densities associated with transistor scaling by dynamically wiring around the defects~\citePaul2006. The fine granularity of FPGAs is however unsuitable for effectively exploiting runtime reconfiguration because of the high overheads involved. A coarse grain reconfigurable array with malleable communication links -- reMORPH -- is proposed in this paper. The compute tile uses DSP48E and BRAM embedded blocks in a Xilinx FPGA and has a very low footprint of about 200 slice LUTs. The semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each ``epoch" of computation. The ``epoch" or phases of the application are obtained via profiling or static data flow analysis. Some of the links between the compute tiles are changed during the reconfiguration phase which drastically reduces the context switch overhead enabling high performance/area applications to be built on this fabric. [ABSTRACT FROM PUBLISHER]

Elliptic curve scalar multiplication is the central operation in elliptic curve cryptography. The paper presents a parallel architecture to accelerate scalar multiplications on Koblitz curves. The scalar multiplier architecture converts the scalar into \tau-NAF representation and processes the zero digits of the scalar in parallel to point additions. Since the conversion from integer to \tau-NAF is a time consuming operation, the proposed architecture uses recently developed \emph{double lazy reduction} algorithm for conversion of scalar. The scalar multiplier processes two consecutive \tau-NAF digits in every iteration. This facilitates parallel processing of large number of consecutive zero digits during a single point addition and practically no time is spent for processing the zero digits of the scalar. The proposed techniques are incorporated in a scalar multiplier and validated on Xilinx Virtex IV FPGA. Experimental results show that our architecture in F2^{163} has the best performance and has the computation time comparable with the fastest known implementation, which uses window based scalar multiplication algorithm. [ABSTRACT FROM PUBLISHER]

The FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. This is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost. [ABSTRACT FROM PUBLISHER]

This paper presents a new approach to implement the dynamic reconfigurable logical systems based on Cellular Neural Networks (CNN), comparing with utilizing the chaos computing system, which is easier to implement in engineering applications and more stable. We provided and experimentally demonstrated the basic principle for obtaining a full-adder by using uncoupled CNN cells. The actual circuit to implementing the full-adder and transforming from adder to subtractor also has been presented. [ABSTRACT FROM PUBLISHER]

In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality. [ABSTRACT FROM PUBLISHER]

This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA using different floating-point representation precision: single, double and 40-bits. The architectural approach is divided into five principal parts, four modules and one unit, namely Change Row Module, Pivo Module, Matrix Elimination Module, Normalization Module and finally the Gauss-Jordan Control-Circuit Unit. This division allows the work with other smaller arithmetic units that are organized in order to maintain the accuracy of the results without the need to internally normalize and de-normalize the floatingpoint data. The implementation of the operations and the whole units take advantage of the resources available in the Virtex-5 FPGA. The error propagation and resource consumption of the implementation, specially the internal RAM memory blocks that are used, constitute improvements when compared with previous work of the authors and other more elaborated architectures whose implementations are significantly more complex than the current one and thus unsuitable for its application. The approach is validated by implementing benchmarks based on solutions in FPGA and software (e.g. Matlab) implemented previously. [ABSTRACT FROM PUBLISHER]