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Describes a simple nomenclature for defects on metal-oxide-semiconductor (MOS) devices. Outline of the revised nomenclature; Discussion of three classes of physical models of border traps; Details of the long-term buildup and annealing of radiation-induced trapped charge in non-radiation-hardened MOS transistors.

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.

LM111 voltage comparators exhibit a wide range of total-dose-induced degradation. Simulations show this variability may be a natural consequence of the low base doping of the substrate PNP (SPNP) input transistors. Low base doping increases the SPNPs collector to base breakdown voltage, current gain, and sensitivity to small fluctuations in the radiation-induced oxide defect densities. The build-up of oxide trapped charge ([N.sub.OT]) and interface traps ([N.sub.IT]) is shown to be a function of pre-irradiation bakes. Experimental data indicate that, despite its structural similarities to the LM111, irradiated input transistors of the LM124 operational amplifier do not exhibit the same sensitivity to variations in pre-irradiation thermal cycles. Further disparities in LM111 and LM124 responses may result from a difference in the oxide defect build-up in the two part types. Variations in processing, packaging, and circuit effects are suggested as potential explanations.

The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single- event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are 1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or 2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. We call this structure the BUSFET - Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of [10.sup.18] [cm.sup.-3], a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x[10.sup.17] [cm.sup.-3], a thicker silicon film (300 nm) must be used.

This paper addresses key issues for the cost-effective use of COTS (Commercially available Off The Shelf) microelectronics in radiation environments that enable circuit or system designers to manage risks and ensure mission success. We review several factors and tradeoffs affecting the successful application of COTS parts including (1) hardness assurance and qualification issues, (2) system hardening techniques, and (3) life-cycle costs. The paper also describes several experimental studies that address trends in total-dose, transient, and single-event radiation hardness as COTS technology scales to smaller feature sizes. As an example, the level at which dose-rate upset occurs in Samsung SRAMs increases from 1.4x[10.sup.8] rad(Si)/s for a 256K SRAM to 7.7x[10.sup.9] rad(Si)/s for a 4M SRAM, indicating unintentional hardening improvements in the design or process of a commercial technology. Additional experiments were performed to quantify variations in radiation hardness for COTS parts. In one study, only small (10-15%) variations were found in the dose-rate upset and latchup thresholds for Samsung 4M SRAMs from three different date codes. In another study, irradiations of 4M SRAMs from Samsung, Hitachi, and Toshiba indicate large differences in total-dose radiation hardness. The paper attempts to carefully define terms and clear up misunderstandings about the definitions of 'COTS' and 'radiation-hardened (RH)' technology.

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis. [ABSTRACT FROM PUBLISHER]

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- V\textit {th} transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V\textit {th} , while the low- V\textit {th} transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( V\textit {gs}=V\textit {dd} ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- V\textit {th} transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics. [ABSTRACT FROM PUBLISHER]

We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits. [ABSTRACT FROM PUBLISHER]

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits. [ABSTRACT FROM PUBLISHER]

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. We show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI. [ABSTRACT FROM PUBLISHER]

The corruption of floating gate bits due to high-energy protons is analyzed in 41-nm single level NAND Flash memories. Proton-induced upsets at low doses are not negligible in deeply-scaled single-level cell Flash memories, due to a combination of direct and indirect ionization effects, which may lead to threshold voltage shifts larger than 2 V. Upsets cross sections are around 10 ^-19~\ cm^2, and increase with proton energy. Variability of energy deposition in the sensitive volume, the sequence of direct and indirect ionizing events, as well as the threshold voltage and electric field reduction associated with each event were included in a model of proton-induced upsets. [ABSTRACT FROM AUTHOR]

Advances in microelectronics performance and density continue to be fueled by the engine of Moore's law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moore's law to alternatives to traditional CMOS technologies. [ABSTRACT FROM AUTHOR]

The radiation response of lateral power MOSFETs in total dose and energetic particle environments is explored. Results indicate that lateral power MOSFETs can be quite susceptible to single-event burnout. Tradeoffs involved in developing radiation hardened lateral power MOSFETs for point-of-load applications are studied using experiments and device simulations. Both design and fabrication process techniques can be used to significantly improve the single-event effect performance of lateral power MOSFETs, but the trade space between electrical and radiation performance must be carefully considered to produce an optimized design for point-of-load applications. [ABSTRACT FROM AUTHOR]

We characterize by different spectroscopic techniques the radiation effects on ytterbium- (Yb) and ytterbium/erbium (Yb/Er)-doped optical fibers. Their vulnerability to the environment of outer space is evaluated through passive radiation-induced attenuation (RIA) measurements during and after exposure to 10 keV X-rays, 1 MeV γ-rays, and 105 MeV protons. These fibers present higher levels of RIA (1000×) than telecommunication-type fibers. Measured RIA is comparable for γ-rays and protons and is on the order of I dB/m at 1.55 μm after a few tenths of a kilorad. Their host matrix codoped with aluminum (Al) and/or phosphorus (P) is mainly responsible for their enhanced radiation sensitivity. Thanks to the major improvements of the Er-doped glass spectroscopic properties in case of Yb-codoping, Yb/Er-doped fibers appear as very promising candidates for outer space applications. In the infrared part of the spectrum, losses in P-codoped Yb-doped fibers are due to the P1 center that absorbs around 1.6 μm and are very detrimental for the operation of Er-codoped devices in a harsh environment. The negative impact of this defect seems reduced in the case of Al and P-codoping. [ABSTRACT FROM AUTHOR]

Direct charge collection measurements are presented, which prove that the presence of tungsten near sensitive volumes leads to extreme charge collection events through nuclear reactions. We demonstrate that, for a fixed incident particle linear energy transfer (LET), increasing particle energy beyond a certain point causes a decrease in nuclear reaction-induced charge collection. This suggests that a worst-case energy exists for single-event effect (SEE) susceptibility, which depends on the technology, device layout, and the incident ions' fixed LET value. A Monte Carlo approach for identifying the worst-case energy is applied to certam bulk-Si and silicon-on-insulator (SOI) technologies. Simulation results suggest that the decrease in charge collection beyond the worst-case energy occurs because the secondary particles produced from the high-energy nuclear reactions have less mass and higher energy and are therefore less ionizing than those produced by lower-energy reactions. [ABSTRACT FROM AUTHOR]

Proton-induced single-event effects hardness assurance guidelines are developed to address issues raised by recent test results in advanced IC technologies for use in space environments. Specifically, guidelines are developed that address the effects of proton energy and angle of incidence on single-event latchup and the effects of total dose on single-event upset. The guidelines address both single-event upset (SEU), single-event latchup (SEL), and combined SEU and total ionizing dose (TID) effects. [ABSTRACT FROM AUTHOR]

A new technique is developed to measure precisely and accurately the width of propagating voltage transients induced by irradiation of inverter chains. The technique is based on measurement of the supply current in a detection inverter, and permits a direct determination of the transient width with a 50 GHz bandwidth. [ABSTRACT FROM AUTHOR]

The propagation of single event transients (SET) is measured and modeled in SOI and bulk inverter chains. The propagation-induced pulse broadening (PIPB) effect is shown to determine the SET pulse width measured at the output of long chains of inverters after irradiation. Initially, narrow transients, less than 200 ps at the struck inverter, are progressively broadened into the nanosecond range. PIPB is induced by dynamic floating body effects (also called history effects) in SOI and bulk transistors, which depend on the bias state of the transistors before irradiation. Implications for SET hardness assurance, circuit modelling and hardening are discussed. Floating body and PIPB effects are usually not taken into account in circuit models, which can lead to large underestimation of SET sensitivity when using simulation techniques like fault injection in complex circuits. [ABSTRACT FROM PUBLISHER]

We characterized the responses of three erbium-doped fibers with slightly different concentrations of rare-earth ions (240-290 ppm) and Al2O3 (7-10 wt.%) during proton and γ-ray exposures. We have simultaneously measured the radiation-induced attenuation (RIA) around the Er3+ ion pumping wavelength (980 nm) and the associated changes of the Er3+ emission around 1530 nm. The three erbium-doped fibers show similar radiation responses. All fibers exhibit RIA levels between 9 × 10-3 and 1.7 × 10-2 dB m-1 Gy-1 at 980 nm and between 4 × 10-3 and 1.1 × 10-2 dB m-1 Gy-1 at 1530 nm. Protons and -y-rays lead to similar radiation damages, with small differences between the protons of different energies (50 MeV and 105 MeV). Furthermore, we have performed online measurements of the spectral dependence of RIA from 600 to 1600 nm and offline measurements from 1200 to 2400 nm. The three fibers exhibit the same spectral response. Losses decrease monotonically from the visible to the infrared part of the spectrum. We have performed spectral decomposition of these RIA curves with the help of absorption bands previously associated with radiation-induced point defects. Our analysis shows that the main part of the RIA (600-1700 nm) in erbium-doped glass can be explained by the generation of Al-related point defects. The other defects related to the germanium and phosphorus doping of the silica seem to have a lower contribution to the induced losses. The Er3+ ion properties seem to be mainly unaffected by proton exposure, suggesting a solvation shell around the Er3+ ion formed by Al2O3 species. [ABSTRACT FROM AUTHOR]

The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a "propagation-induced pulse broadening" (PIPB) effect is observed. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification. [ABSTRACT FROM AUTHOR]

Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASA's MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process. [ABSTRACT FROM AUTHOR]

The effects of heavy ion energy and nuclear inter- actions on the single-event upset (SEU) and single-event latchup (SEL) response of commercial and radiation-hardened CMOS ICs are explored. Above the threshold LET for direct ionization-induced upsets, little difference is observed in single-event upset and latchup cross sections measured using low versus high energy heavy ions. However, significant differences between low- and high-energy heavy ion test results are observed below the threshold LET for single-node direct ionization-induced upsets. The data suggest that secondary particles produced by nuclear interactions play a role in determining the SEU and SEL hardness of integrated circuits, especially at low LET. The role of nuclear interactions and implications for radiation hardness assurance and rate prediction are discussed. [ABSTRACT FROM AUTHOR]

Transistors and ICs were irradiated at dose rates from 0.2 to 2 × 109 rad(SiO2)/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO2)/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8 × 10³ to 106 rad(SiO2)/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2 × 109 rad(SiO2)/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple "overtests" at dose rates from 50 to 300 rad(SiO2)/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO2)/s environments is to use radiation sources that mimic the system environment. [ABSTRACT FROM AUTHOR]

The impact of heavy ion energy on SEU and SEL in commercial and radiation-hardened CMOS SRAMs is explored. Provided the ion range is large enough for the ions to reach the sensitive device region, standard low-energy heavy ion testing is conservative with respect to high-energy heavy ions, at least for LETs above the threshold for direct ionization-induced upsets. However, below the threshold LET for direct ionization-induced effects we find some differences between low- and high-energy tests. These differences are attributed to the effects of nuclear reaction-induced secondary particles. Implications for hardness assurance testing and error rate calculations are discussed. [ABSTRACT FROM AUTHOR]

The effect of proton angle of incidence on proton-induced single-event latchup (SEL) is investigated in detail at room and elevated temperatures in present-day SRAMs. SRAMs from seven different vendors were irradiated at proton energies from 50 to 200 MeV, at temperatures of 25 °C and 75 °C, and at angles of incidence from 0° (normal) to 85° (grazing). The effects of angle of incidence were also investigated for neutron-induced SEL. The angle of incidence can significantly impact SEL hardness. For one SRAM at a temperature of 75 °C, characterizing SEL cross section at grazing angle resulted in a 16 times increase in SEL cross section. Large increases in SEL cross section with angle were also observed for other SRAMs characterized at room temperature. These increases in SEL cross section with angle of incidence are much larger than those measured previously for older SRAM technologies. The mechanism for the effect of angle of incidence on SEL cross section is not due simply to the deposition of more energy in the sensitive volume caused by an increase in path length as the angle of incidence is increased. To investigate possible mechanisms nuclear scattering calculations were performed and combined with device simulations. Simulation results suggest that the mechanism is a consequence of the linear energy transfer (LET) and range distributions of secondary ions produced by proton-material (or neutron-material) interactions coupled with an increase in SEL sensitivity (decrease in LET threshold) as angle of incidence is increased. These results have significant impact on SEL hardness assurance testing, especially for system applications where latchups cannot be tolerated. To best ensure that SEL hardness requirement are met, SRAMs should be characterized at both grazing and normal angles of incidence, and at maximum temperature, voltage, and proton energy. [ABSTRACT FROM AUTHOR]

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 μm to 70 nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies. [ABSTRACT FROM AUTHOR]

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80° C after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents. [ABSTRACT FROM AUTHOR]

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25° and 85 °C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490 MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25 MeV-cm²/mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs ≥40 MeV-cm²/mg. [ABSTRACT FROM AUTHOR]

Under conditions that were predicted as "safe" by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process. [ABSTRACT FROM AUTHOR]

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations., The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-μm generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency. [ABSTRACT FROM AUTHOR]

In this work, we investigate how externally applied mechanical stress impacts the total dose hardness and enhanced low-dose-rate sensitivity of linear bipolar ICs fabricated with different passivation layers. To determine the effects of externally applied stress and/or radiation exposure on the current gain, various compressive or tensile stresses were applied to lateral PNP bipolar transistors at the wafer level, using a cantilever method. The devices were then exposed to 10-keV X-rays or Cs-137 γ-rays. The effect of externally applied stress on pre and post irradiation gain degradation is found to be relatively minor compared to the effects of changes in passivation layers on the radiation response of devices. [ABSTRACT FROM AUTHOR]

The impact of total ionizing dose and displacement damage on single-event upset and single-event latchup hardness assurance testing of present-day commercial SRAMs is studied over a wide range of proton energies and fluence levels. Commercial SRAMs from six different vendors were irradiated at proton energies from 8 to 500 MeY and at total doses from 0 to 100 krad(Si) using multiple radiation sources. For some SRAMs, the single-event upset cross section increased with total dose. The amount of increase in SEU cross section strongly depended on the bias configuration during total dose irradiation and single-event upset characterization. For most of the SRAMs that showed an increase in single-event upset cross section with total dose, the static power supply leakage current also increased. Light emission microscopy photographs identified the source of the increase in power supply leakage current for these SRAMs as originating in peripheral transistors outside the memory array. This suggests a new single-event upset mechanism for present-day devices, which may be due to a reduction in the internally supplied memory array bias level with total dose, increasing memory cell sensitivity to single-event upset The proton energy at which the single-event latchup cross section saturated varied considerably between devices. For one technology, the single-event latchup cross section did not saturate until the proton energy was increased to 200 MeV. These data indicate that single-event latchup hardness assurance testing should be performed at high proton energies (>100 MeV). For fluence levels less than 1011 protons/cm2 at a proton energy of 105 MeV, proton-induced displacement damage had no observable affect on single-event latchup cross section. The implications of these effects on single-event upset and latchup hardness assurance testing are discussed. [ABSTRACT FROM AUTHOR]

Mechanisms for single-event gate rupture (SEGR) in MOS capacitors and linear integrated circuits (ICs) are explored at ion energies greater than 1GeV. We find that SEGR thresholds depend strongly on ion energy, but are independent of oxide defects, bias polarity, doping concentration, and ionizing dose. The number of SEGR strikes across a MOS capacitor was measured, and the SEGR response cross section distinctly shows an electric field threshold. The importance of having stiffening and speedup capacitors at the device is discussed. [ABSTRACT FROM AUTHOR]

This paper investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF- state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar. like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies. [ABSTRACT FROM AUTHOR]

We examine the total-dose radiation response of capacitors and transistors with stacked Al&sub2;O&sub3; On oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increase monotonically with dose and depends strongly on both Al&sub2;O&sub3; and SiOxNy thickness! The thinnest dielectrics, of most interest to industry, are extrenely hard to ionizing irradiation, exhibiting only ∼50 mV of shift at a total dose of 10 Mrad(SiO&sub2;) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by ∼SO% and induce a small amount of capacitance-voltage hysteresis. Al&sub2; O&sub3; /SiOxNy dielectrics which receive a ∼1000°C dopaut activation anneal trap ∼12% more of the initial charge than films annealed at 550°C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO&sub2;). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics. [ABSTRACT FROM AUTHOR]

NMOS transistors were irradiated using X-ray, Co-60 gamma, electron, and proton radiation sources. The charge yield was estimated for protons of different energies and electrons, and compared with values obtained for X-ray and Co-60 irradiations. [ABSTRACT FROM AUTHOR]

Analyzes the radiation hardness of various silicon-on-insulator (SOI) technologies by taking into account the physical and electrical structure of the elementary transistors. Evolution of SOI technologies; SOI transistor structures; Discussion on single-event-effects.

A new method for studying semiconductor device operation with cross-sectional scanning capacitance microscopy (SCM) is described. The technique uses a modified, commercial SCM system to image device cross sections while dc voltages are incrementally applied to bias test structures between nonconducting and conducting states. The novel test structure design and packaging simplify sample preparation while enabling the application of voltages to discrete regions of the semiconductor device. By recording sequential SCM images as a function of bias voltage, the process of switching a device "off" and "on" can be visualized to study carrier movement in the active region of the device. Two sample SCM sequences of metal-oxide-semiconductor field-effect transistors, one fabricated on a bulk silicon substrate and the other on a silicon-on-insulator substrate, are presented to show typical carrier movement in these devices. [ABSTRACT FROM AUTHOR]

Presents a study that examined the total dose radiation response of hafnium-silicate capacitors. Investigation of the effects of commonly used reliability screens on the capacitors; Analysis of baking and bias effects; Assessment of the net-oxide charge-trapping efficiency of the capacitors.

Presents a study that examined hardness loss in a radiation-tolerant bipolar-voltage comparator. Background on the LM139 quad-voltage comparator; Assessment of the comparator's modifications; Analysis of the degradation mechanism of V[subOS].

Presents a study that examined the mechanism of the reliability degradation of dielectric films due to high-energy ion irradiation using a percolation approach. Analysis of parameters that affect postirradiation reliability degradation; Investigation of the enhancement of the reliability of degradation due to increasing ion fluence incident; Results and implications.

Presents a study that investigated increased saturation upset cross sections observed in some silicon-on-insulator integrated circuits. Background on advanced commercial integrated circuits; Examination of the simulation methodology; Analysis of simulations and the mechanism for charge collection.

Presents a study that investigated the correlation of radiation-induced charge buildup in metal oxide semiconductor (MOS) transistors caused by energetic protons and electrons to the buildup caused by X-rays and Co-60 gamma rays. Examination of the effect of proton energy on the nMOS threshold voltage shift; Assessment of mechanisms concerning the electric field dependence of the voltage shifts; Analysis of the charge yield parameters.

Investigates differences in radiation-induced device degradation for X-ray, Co-60 gamma and proton irradiations at energies from 20 to 200 MeV. Experimental details; Experimental results and discussion.

Examines the radiation response of metal-oxide-silicon capacitors after alternating current and direct current bias irradiations using both thermally stimulated-current and capacitance-voltage analysis. Assessment of alternating and switched bias irradiations; Experimental results; Electron-hole ratio.