Total Ionizing Dose Hardness Assurance Issues for High Dose Rate Environments.

Transistors and ICs were irradiated at dose rates from 0.2 to 2 × 10⁹ rad(SiO₂)/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO₂)/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8 × 10³ to 10⁶ rad(SiO₂)/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2 × 10⁹ rad(SiO₂)/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple "overtests" at dose rates from 50 to 300 rad(SiO₂)/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO₂)/s environments is to use radiation sources that mimic the system environment. [ABSTRACT FROM AUTHOR]