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In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects. [ABSTRACT FROM AUTHOR]

Despite its relatively high hole mobility, the electrical performance of p-type SnO thin-film transistors (TFTs) lags behind that of n-type oxide TFTs. In this study, we present an approach to enhance the performance of p-type SnO TFTs by utilizing an atomic-layer-deposited SnO/high-k structure, with crystalline HfO2 (c-HfO2) serving as a high-k dielectric. However, the grain boundaries on the c-HfO2 surface influenced the microstructure and orientation of the SnO layer, resulting in a random orientation and surface roughening. To address this issue, we modified the c-HfO2 surface with an amorphous ultrathin Al2O3 layer to eliminate the grain boundaries on the deposition surface. This enabled the alignment of the (00l) SnO planes parallel to the substrate surface and provided a smooth surface. Moreover, the introduction of ultrathin Al2O3 into SnO/high-k stacks substantially improved the electrical performance of p-type SnO TFTs. Our findings highlight the potential of integrating van der Waals semiconductors with high-k dielectrics, facilitating opportunities for advanced device applications. [ABSTRACT FROM AUTHOR]

In this paper, In0.22ZnδSn0.78−δO1.89−δ (δ = 0.55) films with a single spinel phase are successfully grown at the low temperature of 300 °C through careful cation composition design and a catalytic chemical reaction. Thin‐film transistors (TFTs) with amorphous In0.22ZnδSn0.78−δO1.89−δ (δ = 0.55) channel layers have a reasonable mobility of 41.0 cm2 V−1 s−1 due to the synergic intercalation of In and Sn ions. In contrast, TFTs with polycrystalline spinel In0.22ZnδSn0.78−δO1.89−δ (δ = 0.55) channel layers, achieved through a metal‐induced crystallization at 300 °C, exhibit a remarkably high field‐effect mobility of ≈83.2 cm2 V−1 s−1 and excellent stability against external gate bias stress, which is attributed to the uniform formation of the highly ordered spinel phase. The relationships between cation composition, microstructure, and performance for the In2O3–ZnO–SnO2 ternary component system are investigated rigorously to attain in‐depth understanding of the roles of various crystalline phases, including spinel Zn2−ySn1−yIn2yO4 (y = 0.45), bixbyite In2−2xZnxInxO4 (x = 0.4), rutile SnO2, and a homologous compound of compound (ZnO)k(In2O3) (k = 5). This work concludes that the cubic spinel phase of Zn2−ySn1−yIn2yO4 (y = 0.45) film is a strong contender as a substitute for semiconducting polysilicon as a backplane channel ingredient for mobile active‐matrix organic light‐emitting diode displays. [ABSTRACT FROM AUTHOR]

Broadband phototransistors have attracted considerable attention for numerous applications. Transistors based on amorphous oxide semiconductors (AOSs) provide an excellent photosensor platform because of the reasonably high mobility, extremely low off-state current, low-cost fabrication capability, and large-area scalability of AOSs. To create photo-responsivity for visible to near-infrared (NIR) light in an AOS transistor, lead sulfide quantum dots (PbS QDs) with a cutoff wavelength of 1300 nm were incorporated using a spin-coating process. The distance between PbS QDs was tailored by short tetrabutylammonium iodide ligands through a ligand exchange process. To reduce the operation voltage of the AOS phototransistor, indium gallium oxide (IGO) and hafnium oxide (HfO2) films were used as the semiconducting n-type channel and gate insulator, respectively. The IGO and HfO2 films were grown by plasma-enhanced atomic layer deposition (PEALD). The fabricated PbS QD/IGO phototransistors with an HfO2 gate insulator exhibited remarkable switching properties, such as a high carrier mobility of 20.1 cm2 (V−1 s−1), a low subthreshold gate swing of 0.060 V decade−1, and a high ION/OFF ratio of 2.2 × 108. Additionally, they also exhibited a photo-responsivity of 211 A W−1 and a detectivity of 8.9 × 1011 Jones at 1300 nm even at an ultralow power operation (VGS = ±1 V, VDS = 0.1 V). Moreover, the fabricated devices showed a reasonable uniformity with near-zero VTH in different batches and exhibited the modest degradation after the storage of 15 days to air atmosphere even though they were not encapsulated by a suitable passivation layer. The relevant physical rationale is discussed based on structural, optical, and electrical analyses. The results suggest that a phototransistor with a PbS QD/IGO/HfO2 stack can provide large-area scalable and low-voltage operation routes for visible to NIR imaging, communication, and sensing applications. [ABSTRACT FROM AUTHOR]

We report the effects of sputter‐based multi‐stack interlayer on the electrical contact properties of a‐IGZO TFTs. The a‐IGZO TFTs with a multi‐stack interlayer of TiN and IGTO showed remarkable outcomes, including the lowest specific contact resistivity (ρC) and the highest field‐effect mobility (μFET). This research suggests a highly effective approach to reduce the contact resistivity of oxide semiconductors by nearly two orders magnitude. [ABSTRACT FROM AUTHOR]

In this Letter, we report a demonstration of p-channel tin monoxide (SnO) thin-film transistors (TFTs) with high field-effect mobility (μFE) exceeding 10 cm2/Vs and hysteresis-free like behavior. We demonstrate that maintaining metallic states before encapsulation is a key process to enhance μFE in p-type SnO thin-films. Sustaining this meta-stability involves the following two processes during fabrication: (1) postdeposition annealing (PDA) in two steps and (2) encapsulation in the middle of each PDA. This simple process not only suppresses creation of oxidized states such as adverse Sn4+ but also facilitates the lateral growth of crystals with improved crystallinity by interfacial energy stabilization. The resultant SnO TFT reveals a record-high μFE up to 15.8 cm2/Vs with a negligible hysteresis of 0.1 V. This study suggests a practical route to grant high μFE to p-channel SnO TFTs without any dopant or complex postdeposition treatment. [ABSTRACT FROM AUTHOR]

The high‐performance amorphous In‐Ga‐Sn‐O (a‐IGTO) thin‐film transistors (TFTs) was fabricated with plasma‐enhanced atomic layer deposition (PEALD)‐derived Al2O3 high‐k gate dielectric at a maximum processing temperature of 150 °C. During the deposition of Al2O3 dielectric on a‐IGTO films, the hydrogen (H) and excess oxygen (Oi) defects from the Al2O3 act significant role on TFTs operation. The amounts of H and Oi can be controlled by adjusting oxygen plasma density in radio‐frequency (rf) of PEALD. The optimized a‐IGTO TFT exhibit high‐performance electrical properties with field‐effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are considered as one of the most promising candidates for back‐end‐of‐line transistors for monolithic 3D integration due to various advantages, such as complementary metal–oxide–semiconductor (CMOS)‐compatible method, low fabrication temperature, and promising electrical characteristics. As such, the demand for p‐type oxide semiconductors that are comparable to their n‐type oxide counterparts is increasing. However, the inferior electrical characteristics of p‐channel field‐effect transistors based on oxide semiconductors hinder their widespread application. Thus, the development of high‐performance p‐type oxide semiconductors is essential for their implementation in next‐generation electronics, which have requirements such as innovative form factors, high power efficiencies, and superior transparency. Herein, strategies for improving the device performances of p‐type oxide semiconductors fabricated via CMOS‐compatible methods are reviewed from a material science and device physics perspective, and a brief history of p‐type oxide semiconductors is discussed. Furthermore, critical issues for p‐type oxide semiconductors, such as the transport mechanism, bias stress stability, high off‐current, and ambipolar behavior, are discussed. [ABSTRACT FROM AUTHOR]

In this study, we examine the effect of oxygen vacancies (${V}_{O}$) near the back surface of p-type tin monoxide (SnO) semiconductors on the device performance of its thin-film transistors (TFTs). Non-stoichiometry of the SnO surface layer was controlled through oxidant exposure conditions during alumina (Al2O3) growth using plasma-enhanced atomic layer deposition (PEALD). During the initial period of Al2O3 deposition, trimethylaluminum precursors absorbed oxygen from the SnO layer and created the ${V}_{O}$ , which can form a ${V}_{O}$ -rich region at the Al2O3/SnO interface. By modulating the oxygen plasma density during the PEALD process, the ${V}_{O}$ was effectively controlled, allowing the electrical characteristics to transition from ambipolar behavior to ${p}$ -channel only conduction. This study demonstrates the importance of the back surface of SnO, suggesting a new perspective of ambipolar behavior in p-type SnO semiconductors. [ABSTRACT FROM AUTHOR]

Development of high‐performance p‐channel thin‐film transistors (TFTs) can be an essential building block for next‐generation display technologies which require a great power efficiency. While an n‐channel InGaZnO TFT has been practically demonstrated, the counterparts are still challenging because of their ionic bonding nature. Here we report high‐performance p‐channel hexagonal tellurium (Te) TFT which exhibits outstanding device performances with a field‐effect mobility of 21.2 cm2/Vs, a current modulation ratio of 2.3 × 105, a subthreshold swing of 0.2 V/dec, and a threshold voltage of ‐0.3 V. This study shows a strong potential of p‐channel Te TFT for next‐generation display applications. [ABSTRACT FROM AUTHOR]

A low on–off current modulation ratio (ION/OFF) in p-type tin monoxide (SnO) field-effect transistors (FETs) is a critical bottleneck hampering their widespread application to transparent complementary metal oxide semiconductors (CMOSs) or monolithic integrated devices. To solve this problem, this study focuses on the source/drain (S/D) contact region. Also, a new perspective on the origin of the high off-current in SnO FETs, an electron injection from the drain electrode into the channel by Fermi-level pinning (FLP) at the off-state, is suggested. In this work, a metal–interlayer–semiconductor (MIS) S/D contact structure is adopted to suppress this adverse electron injection. An ultrathin interlayer (IL) of MIS contact alleviates metal-induced gap state (MIGS) penetration which is a primary cause of the severe FLP. A considerable enhancement is achieved by using the MIS contact structure: the off-current value decreased by approximately 20-fold from 5.1 × 10−8 A to 2.4 × 10−9 A; the ION/OFF value increased 10-fold from 2.7 × 102 to 2.8 × 103, which is interpreted by increased MIS contact-mediated electron SBH. This work presents a new approach that can be easily used alongside previously reported methods to suppress the off-current, providing enhanced switching capability of p-type SnO FETs using a simple method. [ABSTRACT FROM AUTHOR]

Development of p‐type inorganic semiconductors for high performance thin‐film transistor (TFT) can be an essential ingredient for next‐generation display applications which requires a low power consumption. However, the conventional p‐type oxide semiconductors exhibit the poor electrical characteristics, which is mainly attributed to the inefficient conduction path formation from oxygen 2p orbitals. Here, we report a new p‐type material, tin oxyselenide (SnSeO) semiconductors for high performance p‐channel TFTs. The SnSeO was designed with the concept that valence band maximum (VBM), hole conduction path, becomes delocalized by hybridizing selenium 4p and tin 5s orbitals. The SnSe0.56O0.44 thin‐film exhibited the highest Hall mobility of 15.0 cm2 V‐1 s‐1 and hole carrier density of 1.2 x 1017 cm‐3. In addition, the SnSe0.56O0.44 TFT showed the excellent field‐effect mobility of 5.9 cm2 V‐1 s‐1 and current modulation ratio of 3.0 x 102. This high mobility is explained by the low hole effective mass through valence band engineering, which was confirmed by density functional theory calculation. Moreover, complementary metal oxide semiconductor (CMOS) inverter using the p‐type SnSe0.56O0.44 with n‐type IGZO showed excellent intrinsic gain of 15.7. This anion hybridization can provide a facile route to the realization of a high performance p‐channel TFT for next‐generation displays. [ABSTRACT FROM AUTHOR]

We present a universal metal–interlayer–semiconductor (MIS) contact model to demonstrate the effect of Fermi-level unpinning, considering both the extrinsic interface-state density (${D} _{\textsf {it}}$) and the density of metal-induced gap states (${D} _{\textsf {MIGS}}$) at the semiconductor surface. Previous studies on MIS contact modeling have quantified only the impact of ${D} _{\textsf {MIGS}}$ on Fermi-level pinning. However, the extrinsic interface states such as interface traps and local vacancies significantly affect the contact resistivity degradation in MIS contacts. Moreover, field emission (FE) and thermionic FE (TFE) current density models in MIS contact are described in detail, for the extraction of the specific contact resistivity ($\rho _{c}$). The physical validity of the proposed model is demonstrated by comparing its calculated $\rho _{c}$ with those obtained in prior experimental studies employing a GaAs substrate (Ti/ZnO/n-GaAs and Ti/TiO2/n-GaAs). The $\rho _{c}$ values for the MIS contacts are also evaluated with various ${D} _{\textsf {it}}$ levels and the interlayers. This model is promising for the development of a comprehensive next-generation MIS contact for the sub-10-nm complementary metal–oxide–semiconductor technology. [ABSTRACT FROM AUTHOR]

High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10‐8 A to 2.4 × 10‐9 A and the enhancement of the ION/OFF from 2.7 × 102 to 2.8 × 103 compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs. [ABSTRACT FROM AUTHOR]

In general, the electronic and optical properties of oxide films can significantly benefit from highly textured crystallinity. However, oxide films grown by atomic layer deposition (ALD), a powerful technique for the synthesis of high-quality, nanoscale thin films, usually exhibit amorphous or randomly oriented polycrystalline phases. Here, we demonstrate the growth of highly textured rutile phase ALD TiO 2 films through rational substrate design. Both a - and c -axis preferentially oriented TiO 2 films are obtained by varying the lattice parameters of the initial ALD growth surface. Under optimized conditions, we find that it is possible to deposit high-quality, c -axis preferentially aligned TiO 2 films with a bulk dielectric constant approaching 185, rivaling the single crystal limit. These films display a remarkably high dielectric constant of 117 despite thin thickness of 5.2 nm. Moreover, the addition of a single doping sequence of Al 2 O 3 successfully suppresses leakage currents to levels compatible with modern dynamic random access memory cells, all the while maintaining the high bulk dielectric constant of 137. These results clearly highlight the prospect of utilizing crystal orientation engineering in ALD thin films for emerging semiconductor devices.

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In 0.84 Ga 0.16 O or In 0.75 Zn 0.25 O), and a barrier layer (BL) (Ga 2 O 3 ) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μ FE ) with band-like transport, steep gate swing ( SS ), and positive threshold voltage ( V TH ) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In 0.75 Zn 0.25 O/Ga 2 O 3 NL TFT showed remarkable electrical performance: μ FE of 77.1 ± 0.67 cm 2 /(V s), V TH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and I ON/OFF of 8.9 × 10 9 with a low operation voltage range of ≤2 V and excellent stabilities (Δ V TH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Ultraviolet to infrared broadband spectral detection capability is a technological challenge for sensing materials being developed for high-performance photodetection. In this work, we stacked 9 nm-thick tellurium oxide (TeO x ) and 8 nm-thick InGaSnO (IGTO) into a heterostructure at a low temperature of 150 °C. The superior photoelectric characteristics we achieved benefit from the intrinsic optical absorption range (300-1500 nm) of the hexagonal tellurium (Te) phase in the TeO x film, and photoinduced electrons are driven effectively by band alignment at the TeO x /IGTO interface under illumination. A photosensor based on our optimized heterostructure exhibited a remarkable detectivity of 1.6 × 10 13 Jones, a responsivity of 84 A/W, and a photosensitivity of 1 × 10 5 , along with an external quantum efficiency of 222% upon illumination by blue light (450 nm). Simultaneously, modest detection properties (responsivity: ∼31 A/W, detectivity: ∼6 × 10 11 Jones) for infrared irradiation at 970 nm demonstrate that this heterostructure can be employed as a broadband phototransistor. Furthermore, its low-temperature processability suggests that our proposed concept might be used to design array optoelectronic devices for wide band detection with high sensitivity, flexibility, and stability.

In this work, high-performance amorphous In 0.75 Ga 0.23 Sn 0.02 O ( a -IGTO) transistors with an atomic layer-deposited Al 2 O 3 dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (O i ) in the Al 2 O 3 film, which was controlled by adjusting the oxygen radical density (P O2 : flow rate of O 2 /[Ar+O 2 ]) in the radio-frequency (rf) plasma during ALD growth of Al 2 O 3 , significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and O i in Al 2 O 3 /IGTO stacks according to P O2 were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low P O2 of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high P O2 condition of 20% introduced O 2 molecules (or O i ) into the Al 2 O 3 film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and O i in Al 2 O 3 by controlling the P O2 , we fabricated high-performance IGTO transistors with a high field-effect mobility (μ FE ) of 58.8 cm 2 /Vs, subthreshold gate swing ( SS ) of 0.12 V/decade, threshold voltage ( V TH ) of 0.5 V, and I ON/OFF ratio of ∼10 9 even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the V TH shifts for exposure to PBS and NBS for this duration were 0.1 V and -0.15 V, respectively.