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The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation. [ABSTRACT FROM AUTHOR]

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si 0. 7 Ge 0. 3 material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high- k dielectric material HfO˙2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices. [ABSTRACT FROM AUTHOR]

The progress in semiconductor technology has played a crucial role in enhancing human existence by introducing significant innovations. The pursuit of high-performance devices utilizing novel materials has emerged as a crucial avenue for surmounting the existing limitations of silicon-based technologies. This paper presents an evaluation of the diverse short channel effects (SCEs) exhibited by the double gate n-FinFET structure, considering the influence of temperature on channel materials using metal gate (MG) as Gallium Arsenide (GaAs) alongside High-K dielectric oxide materials such as Hafnium Oxide (HfO2), Lanthanum Oxide (La2O3) and Lanthanum Aluminum Oxide (LaAlO3) in comparison with traditional Silicon Dioxide (SiO2). The investigation and presentation of the impact of gate length (Lg), channel width (Wch), doping, and varying Temperature (275k-450k) on several short channel effects (SCEs), namely Drain Induced Barrier Lowering (DIBL), Subthreshold Slope (SS), threshold voltage (Vth) roll-off, Transconductance (gm) and ON-OFF current ratio (ION / IOFF) have been thoroughly examined using the aforementioned materials. The utilization of FinFET technology using HK-MG presents notable benefits in terms of mitigating the subthreshold swing while concurrently maintaining a low drain-induced barrier lowering (DIBL) effect. [ABSTRACT FROM AUTHOR]

In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of a vertical dopingless double gate junctionless field-effect transistor (VDL-DG-JLFET) on a silicon-on-insulator (SOI) substrate, utilizing the charge plasma concept. 2D TCAD numerical simulations have been carried out to evaluate and compare switching and analog/ RF performance parameters with a vertical double gate junctionless accumulation field-effect transistor (VDG-JAMFET). The results demonstrate that the VDL-DG-JLFET exhibits superior gate control and delivers substantial enhancements in critical parameters such as drive current (ID), reduction of drain-induced barriers (DIBL), subthreshold swing (SS), and the on-current to off-current ratio (ION/IOFF) when juxtaposed with the VDG-JAMFET. Additionally, the VDL-DG-JLFET demonstrates improved transconductance (gm), cut-off frequency (fT), and maximum oscillation frequency (fmax) compared to the VDG-JAMFET. These findings collectively highlight the superior attributes of the VDL-DG-JLFET in comparison to the VDG-JAMFET, reinforcing its potential for advanced electronic applications. [ABSTRACT FROM AUTHOR]

This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). [ABSTRACT FROM AUTHOR]

This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gateall-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metalinsulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an increase in ferroelectric thickness leads to a negative DIBL value due to the ferroelectric charge. Additionally, there exists an inverse relationship between ferroelectric thickness and channel length to achieve a DIBL value of 0. This condition is satisfied only with the increase of the ferroelectric thickness as the channel radius and insulator thickness increase. The DIBLs increase with higher remanent polarization and lower coercive field, remaining constant when the ratio of remanent polarization and coercive field is maintained. [ABSTRACT FROM AUTHOR]

This work investigates the effect of single and dual-k spacer materials consisting of different dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low-k spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The drain-induced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture’s performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: $I_{ON}$ to $I_{OFF}$ ratio of approximately $10^{5}$ , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS-FET is also analyzed with single-k and dual-k spacers. The performance of single-k and dual-k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.

The motivation of this study was to solve the high $\rm I_{D,off}$ problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses. As a result, $\rm I_{D,off}$ increases and $\rm BV_{DSS}$ decreases as the dose increases. When it exceeds 1.0E15 cm $^{-2}$ , the occurrence of tail-type $\rm I_{D,off}$ and $\rm BV_{DSS}$ that deviate from the normal distribution increases. Implanted nitrogen enhances the diffusion of dopants in the LDD bulk but suppresses it on the silicon surface. As a result, the depletion curvature at the LDD edge becomes a negative shape and increases the electric field. We performed the same experiment on logic MOSFETs to comprehensively analyze other electrical effects. Nitrogen improves the HCI immunity of MOSFETs but degrades for 2.5 Volt and 8 Volt MOSFETs when the dose is above 1.0E15 cm $^{-2}$ . The short-channel effect of 2.5 Volt MOSFET is insensitive to nitrogen but is suppressed in CORE MOSFET when the dose is over 1.3E15 cm $^{-2}$ . Nitrogen changes $\rm I_{D,sat}$ through interactions with co-implanted species and nitrogen dose. As a result, nitrogen co-implanted with phosphorus shows a parabolic-like $\rm I_{D,sat}$ trend. However, in the case of CORE MOSFET implanted with arsenic, $\rm I_{D,sat}$ does not show a parabolic-like trend but increases continuously. This experiment did not find much benefit from nitrogen implantation for 2.5 Volt and 8 Volt MOSFETs. For all MOSFETs, it is recommended that the nitrogen dosage not exceed 1.0E15 cm $^{-2}$ .

In this work, we present the novel application of SiNx stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiNx passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as Vds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiNx passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as Vds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiNx stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications.

Moore's law claims that recent technological developments have already resulted in a significant rise in the number of transistors on a chip. By switching from a conventional MOSFET built with a single control gate to one with numerous control gates, the device's manageability has been significantly improved. Apart from this dielectric spacer plays a vital role in enhancing the device's performance drastically. This work compares the performance of fully depleted Silicon on Insulator (SOI) FinFETs constructed with single-k and dual-k dielectric spacers, adjusting the channel doping concentration as 1 × 1019/cm3, 1 × 1018 /cm3, and 1 × 1017 /cm3. Among the single dielectric spacers investigated are air, SiO2, HfO2, and a dual spacer combination with HfO2+SiO2 between the source (S) and drain (D) terminals. The leakage current will be successfully reduced, and short channel effects (SCEs) will be improved with FinFETs that include dual dielectric spacer dielectric materials in the design. The performance of CMOS inverter for various dielectrics is also performed and its effect on a single dielectric spacer is analyzed. The performance of the designed FinFET with single-k and dual-k spacers is analyzed using the Visual-TCAD 3D Cogenda tool and circuit aspects are performed using the CADENCE platform. Exciting device DC properties are established, including ION to IOFF ratio of 105, DIBL of 13 mV/V, sub-threshold swing (SS) of 72 mV/dec, and low threshold voltage (Vth) of 0.16 V for channel doping concentration of 1 × 1019 cm−3 of the dual-k HfO2+SiO2 spacer combination. Single spacer dielectrics are effective for low power, while multiple spacer dielectrics efficiently limit leakages and effectively increase switching speed. [ABSTRACT FROM AUTHOR]

The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO2) with a stacked gate oxide of 0.5 nm of SiO2 with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si3N4, Al2O3, ZrO2, and HfO2. It was found that the use of strained silicon and replacing only the SiO2 device with the stacked SiO2 and HfO2 device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. [ABSTRACT FROM AUTHOR]

With the miniaturization of thin film transistor (TFT), it exhibits severe short channel effect (SCE) including drain‐induced barrier lowering (DIBL). In this paper, the authors have manufactured a novel side wrapped TFT to enhance gate electrode's control over the channel and optimize the electric field distribution, which leads to stronger DIBL immunity. [ABSTRACT FROM AUTHOR]

This manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec). [ABSTRACT FROM AUTHOR]

Nanotube Junction-less Double-Gate-All-Around (NJL-DGAA) MOSFETs using Si nanomaterials or nano particle emerged as an appealing option for the design of high-speed ULSI processors. Changes in ambient temperature, on the other hand, have an effect on its performance such as hot carrier injection (HCI) degradation, analog/RF performance, and electrostatic performance that must be examined. The influence of temperature and oxide changes on the performance parameters of the Nanotube Junctionless Double-Gate-All-Around (NJL-DGAA) MOSFET has been investigated in this research for performance enhancement utilising the Silvaco 3D simulator. NJL-DGAA MOSFETs are evaluated for a variety of parameters including subthreshold swing (SS), ON-current, DIBL, OFF-current, and transconductance at temperatures changes from 250°K to 350° K. In addition, the analog/RF performance of NJL-DGAA MOSFETs for various semiconductor high k gate dielectric materials was investigated. Enhance thickness of the oxide layer with a high semiconductor dielectric constant to equivalent-oxide-thickness (EOT) and reduce leakage current, which are correlated with transistor speed. According to the performance evaluation, NJL-DGAA provides better analog/RF performance for high-frequency and low-power applications at high k gate dielectric material. [ABSTRACT FROM AUTHOR]

In this work, we have proposed and analysed the Triple Material Dual Gate Cylindrical Nanowire (TMDG CNW) device structure at the 10 nm technology node for improved device performance over conventional nanowire. The proposed structure was validated using the Sentaurus TCAD tool. By incorporating three materials with different work functions as gate electrodes, using a dielectric stack and halo doping in the channel region, the device performance has been enhanced and immunity to short channel effects (SCE) has been improved further. An additional gate-coaxial inner gate other than the outer gate has been added to the TMDG CNW structure, which further improves the device performance. The proposed device has higher drain current, good immunity to SCE and process variations, better gate control over the channel, and overall better device performance. This gate/channel engineered nanowire FET with an additional coaxial inner gate has been reported for the first time. [ABSTRACT FROM AUTHOR]

With technology scaling and to meet the desired design for low power and high-speed circuit, innovative design is being studied. The simulation study of vertical Quad gate oxide stacked junction-less Nano-sheet being a most promising device structure within a Nano scale regime, with the use of oxide, work function, and channel engineering for single, double, and triple fins Nano-sheet have been successfully demonstrated and implemented. From the reference model of tri-gate junction-less (TGJLFET) the structure is modified with a new design approach the with same design parameters. The First approach is by adding the fourth gate to the TGJLFET structure forms a new structure of quad gate junction-less Nano-sheet. The second approach is by extending the fins and adding source and drain pads with an underlap structure. The Third approach is adding the fin stacking and the fourth approach is adding gate oxide stacking to three fins vertical quad gate oxide stacking junction-less Nano-sheet (QGOSJLNS), all the approaches are simulated using a 3D visual TCAD environment. The improvement in the performance of the Nano-sheet device is denoted after comparing it with TGJLFET. Investigated performance includes leakage current, sub-threshold swing (SS), Drain induced barrier lowering (DIBL), threshold voltage (Vth), transconductance (Gm), the potential at core and surface fins of the Nano-sheet. Further, DC analysis of 3D QGOSJLNS an inverter is simulated and studied using 3D V-TCAD environment from Cogenda Pvt Ltd. [ABSTRACT FROM AUTHOR]

• A novel material and device structure which has never been reported in literature. • A novel material (In 0.53 Ga 0.47 As) & device structure which is junctionless double surrounding gate In 0.53 Ga 0.47 As nanotube (NT) MOSFET using triple and quadruple metal gate work function engineering has been used. • For a reasonable comparison between junctionless (JL) CGAA and inversion mode CGAA NT, the doping concentration in JL have been optimized for two concern (i) to get the same I ON current as IM device (ii) and to get the same threshold voltage (V TH) as IM. This result in 12.9 times and 102 times smaller I OFF in matching I ON and V TH optimized device respectively as compare to IM. • A comparison have been done with literature. • This device show better DIBL∼28.10mV/V, almost an ideal SS∼60mV/dec and higher I ON /I OFF ∼1.42 × 107 ratio as compared to literature result of CGAA device type. In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS), shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and thorough investigation of new device structures and advanced materials. The current study focuses on the implementation of Triple Metal (TM) and Quadruple Metal (QM) gate work function engineering techniques on both junctionless (JL) and inversion mode (IM) Double surrounding Gate (DSG) In 0.53 Ga 0.47 As nanotube (NT) MOSFET. The objective is to analyze the drain current (I D) characteristics for a gate length of 3 nm using Silvaco ATLAS 3D TCAD. In order to make a fair comparison between JL and IM In 0.53 Ga 0.47 As NT, the doping concentration of TM and QM JL In 0.53 Ga 0.47 As NT is tuned to achieve two specific objectives. Firstly, the goal is to produce the same I ON as IM In 0.53 Ga 0.47 As NT. Secondly, the aim is to achieve the same threshold voltage (V TH) as IM In 0.53 Ga 0.47 As NT. It was discovered that the I OFF for JL devices is approximately 2.93 times smaller compared to IM devices in the TM situation, while considering matching I ON and V TH. The JL devices have an I OFF that is 12.9 times smaller and an I OFF that is 102 times smaller compared to the IM device for the QM situation. This is achieved by matching the I ON and V TH values. It achieves a lesser drain-induced barrier lowering (DIBL) of approximately 28.10 mV/V, a virtually perfect subthreshold slope (SS) of roughly 60mV/dec, and a larger current ratio of I ON /I OFF , which is approximately 1.42 × 107. [ABSTRACT FROM AUTHOR]

We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO2/ZrO2, La2O3, and TiO2 with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the "knowledge" from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design. [ABSTRACT FROM AUTHOR]

In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a non-intentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications. [ABSTRACT FROM AUTHOR]

Graphene nanoscroll, because of attractive electronic, mechanical, thermoelectric and optoelectronics properties, is a suitable candidate for transistor and sensor applications. In this research, the electrical transport characteristics of high-performance field effect transistors based on graphene nanoscroll are studied in the framework of analytical modeling. To this end, the characterization of the proposed device is investigated by applying the analytical models of carrier concentration, quantum capacitance, surface potential, threshold voltage, subthreshold slope and drain induced barrier lowering. The analytical modeling starts with deriving carrier concentration and surface potential is modeled by adopting the model of quantum capacitance. The effects of quantum capacitance, oxide thickness, channel length, doping concentration, temperature and voltage are also taken into account in the proposed analytical models. To investigate the performance of the device, the current-voltage characteristics are also determined with respect to the carrier density and its kinetic energy. According to the obtained results, the surface potential value of front gate is higher than that of back side. It is noteworthy that channel length affects the position of minimum surface potential. The surface potential increases by increasing the drain-source voltage. The minimum potential increases as the value of quantum capacitance increases. Additionally, the minimum potential is symmetric for the symmetric structure (Vfg = Vbg). In addition, the threshold voltage increases by increasing the carrier concentration, temperature and oxide thickness. It is observable that the subthreshold slope gets closer to the ideal value of 60 mV/dec as the channel length increases. As oxide thickness increases the subthreshold slope also increases. For thinner gate oxide, the gate capacitance is larger while the gate has better control over the channel. The analytical results demonstrate a rational agreement with existing data in terms of trends and values. [ABSTRACT FROM AUTHOR]

The physical modelling of the tunnel field effect transistor (TFET) is done in this study. The Silvaco TCAD tool is used to design and simulate the TFET structure. The FET device has attracted a lot of attention as the ideal tool in creating biosensors because of its appealing properties such as ultra-sensitivity, selectivity, low cost, and real-time detection capabilities in sensing point of view. These devices have a lot of potential as a platform for detecting biomolecules. Short channel effects, specificity, and nano-cavity filling have all been improved in FET-based biosensors. FET-based biosensors are appropriate for label-free applications. Random dopant variations and a thermal budget are seen during the construction of a JLFET. To overcome this problem, the charge-plasma-based concept was established in FETs in this study. Different metallurgical functions for electrodes were employed in this biosensor to behave as a p-type source and n-type drain. To alleviate the short channel effects, a dual material gate work function for the gate electrode was devised, as well as a double gate architecture. Biomolecules can be neutral or charge-based, and both types of biomolecules can be identified using a proof-of-concept FET-based biosensor. Changes in the drain current (Id) of the device were achieved by varying dielectric values and charges in the cavity region with variable cavity lengths. [ABSTRACT FROM AUTHOR]

The conventional Double Gate (DG) MOSFET has confronting problems like increased Short Channel Effects (SCEs). In this paper, channel engineered Core Insulator Double Gate (CIDG) MOSFET has been proposed for low power digital circuitry. In the proposed device, a layer of insulator is placed in the core of the channel. By the use of rectangular core insulator, performance parameters of the device are improved as there is significant reduction in the leakage current. Analysis of the structure is done after the validation of simulation results with the reference data of DG MOSFET. It has been revealed that CIDG MOSFET produces lower Ioff, increased Ion/Ioff, improved Drain Induced Barrier Lowering (DIBL) and Sub-threshold Slope (SS) at 20 nm. The retrieved values of Ioff, Ion/Ioff, SS and DIBL for 20 nm channel length of CIDG MOSFET show 59.101% decrement, 136.077% increment, 4.018% decrement and 34.753% decrement, respectively. The CIDG MOSFET also displays betterment in transconductance generation factor, output conductance, intrinsic gain, early voltage and cut off frequency. [ABSTRACT FROM AUTHOR]

A new high-performance inverted-T shaped 14 nm heterojunction FinFETs has been proposed that originate from the rectangular fin structures. The rationale for proposing this topology is to enable the integration of millions of transistors on integrated circuits (ICs), which can then be used in advanced processors from major semiconductor companies. This paper proposed 14-nm heterojunction FinFET of inverted-T shaped fin and its comparative simulation analysis done with the previous rectangular and rectzoidal shaped FinFET in terms of various parameters i.e. on current, off current, on/off ratio, subthreshold swing, DIBL and fin footprint. Process variation is also done on the proposed 14-nm heterojunction FinFET of inverted T shaped fin on various parameters i.e. fin material,fin width, Ge mole fraction in Si1-xGex, temperature and doping. The proposed design shows the higher on (Ion) current (11.05x10−6 A), higher (Ion/Ioff) current ratio (3.25 x1013) and minimum value of off current (3.40x10−19A) with the minimum value of the subthreshold swing (56.83 mV/dec) and minimum value of DIBL (26.3 mV/V) which is better than the rectangular and rectzoidal fin structure based FinFET. A comparative analysis is also shown for proposed designs of 14 nm inverted-T FinFET with the use of Si and SiGe materials alternatively for source and fin regions to evaluate for transistor on-off performances. [ABSTRACT FROM AUTHOR]

This brief proposes an ultra-low-power current reference in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back-gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/°C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a temperature range of −30°C to 70°C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. [ABSTRACT FROM AUTHOR]

Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger I ON and I OFF is significantly reduced by ⁓105 orders, which is due NC effect, compared to baseline NW. SS avg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (t fe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at t fe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications. [ABSTRACT FROM AUTHOR]

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson's equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool. [ABSTRACT FROM AUTHOR]

In this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly. The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device. [ABSTRACT FROM AUTHOR]

Increased threshold voltages have been observed during linear-mode operation of short-channel bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) employing shallow source and drain extension technology at cryogenic temperatures. These increases were suppressed during saturation-mode operation, which resulted in the increase of a threshold voltage variation between linear- and saturation-modes as if drain-induced barrier lowering occurred. Numerical simulations revealed that these increases originate from enhanced depletion in the extension region and subsequent increases in channel resistance at cryogenic temperatures. These data suggest that shallow extensions should be designed more carefully in the case of MOSFETs intended for cryogenic operation. [ABSTRACT FROM AUTHOR]

For Ultra Large-Scale Integration (ULSI), the most promising device is multi gate Fin Field Effect Transistor (FinFET), as it offers reduced leakage current and better short channel performance. Modern design methodologies for 5 nm node NMOS FinFET transistors are examined in this paper to realize low power and low off state current (Ioff) needs. Changing the punch through stop implant dose, source and drain junction placement, gate work function, Drain Induced Barrier Lowering (DIBL), and sub-threshold slope in combination with cut-in voltage yields the Ioff and Ion (on state current). Source drain expansion design, Fin doping concentration, and gate work function selection are exploited such that a FinFET device provides the requirements of low power and ultra-low power transistors. [ABSTRACT FROM AUTHOR]

This article presents the analytical modeling of the subthreshold drain current of junctionless channel-modulated double-material double-gate (J L - C M - D M D G ) MOSFET. The first time under the full depletion mode, the center channel potential and threshold voltage ( V T H ) have been derived. The center channel potential has been produced by solving the 2D Passion's equation with ideal boundary conditions. The behavior of threshold voltage ( V T H ) and subthreshold drain current of the J L - C M - D M D G MOSFET by varying physical device parameters such as doping concentration ( N D n ), channel thickness ( t S i ), and channel length ratio ( L 1 : L 2 ) has been examined. The drain-induced barrier-lowering (D I B L ) as an indicator of short-channel effects has been studied. The model results have been verified with simulation data extracted from a 2D ATLAS TCAD simulator. [ABSTRACT FROM AUTHOR]

In this article, we present a high‐performance SiGe junctionless FinFET (JLFinFET) on insulator by selective growth of buried oxide (SELBOX) layer device with better electrostatics. The mole fraction x = 0.1, 0.2, 0.3, 0.4, 0.5, and 0.7 with fin width 10 nm and gate length of 20 nm are considered for simulation using technology computer aided design (TCAD) Sentaurus device. With Si0.9Ge0.1 JLFinFET on insulator by SELBOX layer, nearly an ideal subthreshold swing of 61.51 mV/decade and enhanced on‐current, off‐current has been achieved. Evaluation of on‐off current ratio, DIBL, SS for different parameters, such as doping concentration (1015‐1019/cm3), channel length (10‐40 nm), temperature (200‐700°K) on JLJFinFET on insulator by SELBOX layer are presented. Three‐dimensional device simulation using the TCAD software tool Sentaurus Device is used to simulate and the results are compared with a SELBOX JLFinFET. [ABSTRACT FROM AUTHOR]

In this paper, an analytical channel potential model of an experimental nano-scaled triple gate MOSFET has been developed that is valid in the subthreshold regime. The potential model is derived by applying the Schwarz–Christoffel transformation method and conformal mapping techniques. The model is derived by superposing the influence of top gate on the potential barrier with the 2D potential solution, which is obtained by considering the presence of only two side gates. From that, the threshold voltage model of the device is also evaluated. To validate our model, the result has been compared with numerical simulation data from 3D TCAD Sentaurus that shows good accuracy for channel length (as short as 30 nm) considered for our device. [ABSTRACT FROM AUTHOR]

In this article, n‐channel junction‐less transistors (JLTs) with gate lengths in the range of 20–250 nm, having crystalline‐silicon (c‐Si) and polycrystalline‐silicon (poly‐Si) channels are characterized for the short channel effects (SCEs). The shift of the threshold voltage with the gate length and the drain induced barrier lowering (DIBL) are determined by three dimensional numerical simulations using technology computer aided design (TCAD) software. Conductive channels are considered to be fin like structures surrounded by oxides and gate materials on three sides. The effect of important device parameters are considered. Degradation of SCEs with shortening of the gate length is predicted as expected from two dimensional simulations. In addition, simulations indicate improvements for lower doping. Thinner channels show better DIBL and threshold shift. The fin height dependence is more complicated where undesirable peak in DIBL is observed for mid‐range heights near 200 nm. DIBL sharply drops for lower fin heights but the threshold shift becomes worse. Overall a small gate device of 20 nm with short fins of similar size can be expected to give a threshold shift of less than 30 mV and DIBL about 70 mV/V and, the use of three dimensional dielectric pockets leads to near zero shift of the threshold voltage. The performance of the two material types are comparable. [ABSTRACT FROM AUTHOR]

In this paper, a Multi-gate asymmetric hetero-dielectric oxide gate all around nanowire MOSFET device (MG-AHD–GAA-NW) is proposed for the low power standby, memory and sensor applications. The architecture of the proposed device is supported by segmented multiple gate with asymmetric hetero-dielectric oxide high-K(HfO2/TiO2) on the source side and SiO2 on drain side. Firstly, the effect of silicon thickness on conventional single gate cylindrical GAA MOSFET is studied. On reducing the thickness of silicon, a decrease in OFF current is observed. Further, to achieve best performance of the device at reduced silicon thickness(tSi = 5 nm) with quantum confinement effects, the proposed device is introduced. It is observed that at reduced silicon thickness (tSi = 5 nm), a low leakage current of 10−14A and ON current of 10−5A is obtained. The comparison of MG-AHD–GAA-NW with conventional single gate cylindrical GAA at tSi = 5 nm shows decrease in OFF current and increase in ON/OFF current ratio by 67.4% and 230% in MG-AHD–GAA-NW at same silicon thickness respectively. The proposed model is analysed by the various performance metrics such as transconductance(gm), and device efficiency(gm/ID).The proposed device exhibits lower DIBL of 16.7 mV/V, improved subthreshold slope of 62.28 mV/decade, higher ON/OFF current ratio of 8.87 × 108, higher transconductance and optimal threshold voltage. The effect of traps in semiconductor/gate oxide interface on device performance is also studied. Finally, to achieve the best performance of the device at circuit level implementation, the results of PMOS are matched with NMOS using work function engineering and thus V-shaped curve is obtained for both type of MOSFET followed by CMOS inverter as an application is also presented using the proposed device structure. [ABSTRACT FROM AUTHOR]

An Underlap Double Gate (U-DG) Symmetric Heterojunction AlGaN/GaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) with varying source and drain underlap lengths have been studied. The analog performance of the devices has been studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/ID) and intrinsic gain (gmR0). This paper also depicts the effect of varying underlap lengths on the RF figure of merits (FOMs) such as the total gate capacitance (CGG), cut-off frequency (fT) and maximum frequency of oscillation (fMAX) using non-quasi-static approach. Studies shows that the increase in underlap length in MOS-HEMT decreases the DIBL and Subthreshold Swing. U-DG AlGaN/GaN MOS-HEMT with 300 nm symmetric underlap device shows superior Power Output Efficiency (POE) of 41% compared to the 200 nm underlap structure and 100 nm underlap length with 35% and 33% respectively. [ABSTRACT FROM AUTHOR]

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for LG = 13 nm corresponding to the (recent) state-of-the-art technology node for the "More Moore" options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (VT), average subthreshold swing (SSavg), OFF-state current (IOFF), ION/IOFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in VT, IOFF, ION/IOFF, and SSavg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of LG (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SSavg, a reduction of about 1 decade and 3 decades in IOFF, and an improvement of nearly 1 decade and 2 decades in ION/IOFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of IOFF, ION/IOFF and SSavg with the lowest possible shifts in VT (∼ 0%) and SSavg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters. [ABSTRACT FROM AUTHOR]

Abstract In this article, n‐channel junction‐less transistors (JLTs) with gate lengths in the range of 20–250 nm, having crystalline‐silicon (c‐Si) and polycrystalline‐silicon (poly‐Si) channels are characterized for the short channel effects (SCEs). The shift of the threshold voltage with the gate length and the drain induced barrier lowering (DIBL) are determined by three dimensional numerical simulations using technology computer aided design (TCAD) software. Conductive channels are considered to be fin like structures surrounded by oxides and gate materials on three sides. The effect of important device parameters are considered. Degradation of SCEs with shortening of the gate length is predicted as expected from two dimensional simulations. In addition, simulations indicate improvements for lower doping. Thinner channels show better DIBL and threshold shift. The fin height dependence is more complicated where undesirable peak in DIBL is observed for mid‐range heights near 200 nm. DIBL sharply drops for lower fin heights but the threshold shift becomes worse. Overall a small gate device of 20 nm with short fins of similar size can be expected to give a threshold shift of less than 30 mV and DIBL about 70 mV/V and, the use of three dimensional dielectric pockets leads to near zero shift of the threshold voltage. The performance of the two material types are comparable.

Due to better scalability and more immunity to short channel effects in recent technology nodes, Quadruple gate FinFET is introduced as a potential candidate among multiple gate FET devices. This article presents an investigation of the impact of gate dielectric constant on DC electrical parameters in Quadruple gate FinFET. Drive current (Ids), leakage current ( I off ), current switching ratio ( I on / I off ), sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are observed by varying gate dielectric constant. Additionally, the influence of the gate dielectric on analog/RF performance parameters in terms of transconductance ( g m ), output conductance ( g d ), intrinsic gain ( g m / g d ), gate capacitance ( C gg ), cutoff frequency ( f t ), and intrinsic delay are reported with the help of a commercial two-dimensional device simulator. Along variation of gate dielectric constant, some linear parameters such as g m 2 , g m 3 , VIP2 are also analyzed for wireless communication. For high-k dielectric, due to enhancement of oxide capacitance, we observed an increase in drive current, transconductance, switching ratio, and gate capacitance. Linearity parameters are also strongly affected by operating gate dielectric. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves ION/IOFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (fT) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT. [ABSTRACT FROM AUTHOR]

In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrödinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO2) thickness on ID has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same IOn current as IM device and (ii) to get the same threshold voltage VTh as IM. This has resulted in 102 and 103 times smaller IOff in matching IOn and VTh optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL ~15 mV/V, almost an ideal SS ~60 mV/dec, and higher IOn/IOff ratio ~2.18 × 108 as compared to available CGAA literature results. [ABSTRACT FROM AUTHOR]

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design.

In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a non-intentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications.

Graphene nanoscroll, because of attractive electronic, mechanical, thermoelectric and optoelectronics properties, is a suitable candidate for transistor and sensor applications. In this research, the electrical transport characteristics of high-performance field effect transistors based on graphene nanoscroll are studied in the framework of analytical modeling. To this end, the characterization of the proposed device is investigated by applying the analytical models of carrier concentration, quantum capacitance, surface potential, threshold voltage, subthreshold slope and drain induced barrier lowering. The analytical modeling starts with deriving carrier concentration and surface potential is modeled by adopting the model of quantum capacitance. The effects of quantum capacitance, oxide thickness, channel length, doping concentration, temperature and voltage are also taken into account in the proposed analytical models. To investigate the performance of the device, the current-voltage characteristics are also determined with respect to the carrier density and its kinetic energy. According to the obtained results, the surface potential value of front gate is higher than that of back side. It is noteworthy that channel length affects the position of minimum surface potential. The surface potential increases by increasing the drain-source voltage. The minimum potential increases as the value of quantum capacitance increases. Additionally, the minimum potential is symmetric for the symmetric structure (Vfg = Vbg). In addition, the threshold voltage increases by increasing the carrier concentration, temperature and oxide thickness. It is observable that the subthreshold slope gets closer to the ideal value of 60 mV/dec as the channel length increases. As oxide thickness increases the subthreshold slope also increases. For thinner gate oxide, the gate capacitance is larger while the gate has better control over the channel. The analytical results demonstrate a rational agreement with existing data in terms of trends and values.

In this paper, a novel method is proposed for the first time to achieve multiple threshold voltage (VT) for Silicon Nanotube FET. Using TCAD simulator, it is shown that threshold voltage can be varied by tuning the halo doping and tube diameter of Silicon Nanotube FET. The typical method to attain multiple threshold voltages is to select the pertinent gate work-function for individual devices. But this is not practically feasible due to the difficult process complexity. In this work, the tuning of halo doping and nanotube diameter can be elected to provide three possible values of VT at 14-nm technology node. Furthermore, short-channel effect like Drain Induced Barrier Lowering (DIBL) is also found to be reduced with HALO doped region at source side. It is also observed that the threshold voltage decreases while increasing the tube diameter. Moreover, HALO doping at drain side is found showing a significant improvement in analog/RF performances of the device which eventually makes the device more suitable for radio-frequency integrated circuit applications. [ABSTRACT FROM AUTHOR]

The CMOS technology has been dominated long enough by the silicon material world and it has been approaching to its limitations. With contracting magnitudes of thicknesses of the gate oxide layer, leakage current worsens which drastically reduces the device reliability. In the nano regime device, the introduction of high-k materials has brought down the Short Channel Effects (SCEs) significantly. They also provide electrical stability and have proven to be scalable. Different devices are evolved for different gate oxides such as SiO2 and high-k materials like Si3N4, Al2O3, ZrO2 and HfO2. These high-k dielectric materials are compared with the performance of SiO2 in a Tri-Gate (TG) SOI FinFET device. TG SOI FinFETs with 14, 10 and 8 nm gate lengths are implemented for all the dielectric materials considering an equivalent oxide thickness of 1 nm for SiO2. Since the devices are developed in the nano regime, the parameters relating to SCEs such as the roll-off of threshold voltage, on-to-off current ratio and DIBL are investigated and analyzed for all the TG SOI FinFETs. Observation of the electrical characteristics of the devices led to the culmination that the Ion current is at the same level for all geometrical gate lengths. But the leakage currents reduced drastically with HfO2 as the gate dielectric material rendering the highest switching speed of the device along with excellent control over the short channel parameters. The results inevitably show that high-k dielectric material based devices provide enhanced performance by reducing the leakage current, thereby attaining degradation in the SCEs. It has also been perceived that the HfO2 based TG SOI FinFET is found to be the most superior among all others even at 8 nm channel length. [ABSTRACT FROM AUTHOR]