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Highly-stable molybdenum/aluminum (Mo/Al) bilayered electrodes have been demonstrated as promising candidates for use in stretchable electronics. The serpentine-shaped Mo/Al bilayer electrode is shown to be operable with up to 220% elongation and no significant change in resistance. In Al-only electrodes, Al penetrates into the polyimide (PI) because of its high chemical reactivity with PI. This issue can be overcome by inserting Mo underneath the Al layer, blocking the reaction between Al and PI and enabling the formation of robust and highly conductive stretchable electrodes. With the proposed bilayer electrodes, stretchable thin-film transistor arrays that can be operated even when elongated up to 220% are realized. The fabricated devices exhibit very stable device performance under highly stretched conditions.

Transistors with inorganic semiconductors have superior performance than organics. However, they are brittle and thus unfavorable for building deformable electronics. Here, authors directly embed such inorganic thin film transistors into serpentine strings to realize highly stretchable and miniaturized electronic circuits.

To realize organic light-emitting diodes (OLEDs) with improved resolution for display applications, a method for achieving high yield device fabrication is needed. Here, the authors report vertically-stacked transistor-driven full-color OLEDs with photolithography-processed intermediate electrodes.

Electronic skin that spatially maps pressure distribution through imaging shows limited performance despite improvements to data acquisition. Here, the authors report ultraflexible, transparent electroluminescent skin capable of high-resolution imaging of pressure distribution over 3D surfaces.

From the very first time that graphene was used as a transparent electrode for OLED applications, the emergence of active-matrix (AM)-graphene OLED displays has been envisioned. Realizing this expectation, however, turned out to be difficult. Two obstacles are the growth and transfer of a large-area graphene film and the patterning of a graphene film into pixels. To solve these problems, a process of patterning a graphene film without surface contamination was developed. The fabrication of OLED panels by the patterned graphene anode on Gen 2(370 × 470 mm)-sized and flexible substrates was successfully demonstrated. In this work, oxide TFT arrays were combined as a switching backplane, and a pixelated graphene OLED was used as an emissive layer, to realize AM-graphene OLED displays. To explore the technical feasibility of flexible AM-graphene OLED displays, the aforementioned components were formed on a flexible substrate. For commercial-level production, all the processes that were used were chosen to be compatible with the conventional display processes.

Since the late 20th century, there has been rapid development in the display industry. Only 30 years ago, we used big cathode ray tube displays with poor resolution, but now most people use televisions or smartphones with very high‐quality displays. People now want images that are more realistic, beyond the two‐dimensional images that exist on the flat screen, and digital holography—one of the next‐generation displays—is expected to meet that need. The most important parameter that determines the performance of a digital hologram is the pixel pitch. The smaller the pixel pitch, the higher the level of hologram implementation possible. In this study, we fabricated the world‐smallest 3‐μm‐pixel‐pitch holographic backplane based on the spatial light modulator technology. This panel could display images with a viewing angle of more than 10°. Furthermore, a comparative study was conducted on the fabrication processes and the corresponding holographic results from the large to the small pixel‐pitch panels.

Presented is a flexible dual-mode display operable in reflective and emissive mode according to ambient light for optimal visibility on a nonplanar surface. Flexible-backplane-embedding organic light-emitting diodes (OLEDs), thin-film transistors (TFTs), and control electrodes for liquid crystal (LC) shutter are realized by the laser lift-off (LLO) method and the newly developed polyimide (PI) delamination technique. A novel color-filterless LC shutter with color dyes is merged with this flexible backplane for operation in reflective mode. This work opens up a promising approach to building displays that are adaptive to the surrounding environment for better usability.

Optical absorbers have been a topic of intense research due to their importance in many applications. In particular, multi-band and perfect absorption features in a desired frequency range are essential in broadband applications. In this work, we numerically studied the absorption properties of subwavelength metallic gratings coated with a dielectric layer. Here, the structure is considered to be an integration between a resonant cavity and a subwavelength metallic grating. Two appropriately designed structures can exhibit multi-band absorption properties. In addition to the numerical simulation results, we elaborate on determining the appropriate structural parameters that yield the desired spectral absorption profile in the visible range. We also numerically identify critical coupling conditions for perfect absorption.

In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 μm × 50 μm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger’s ridges and valleys through the fingerprint sensor array.

We developed a high-resolution active matrix spatial light modulator on a glass substrate. To integrate a switching device on the glass substrate, we designed a high-performance oxide thin-film transistor with a minimum channel length of 1 μm and a maximum processing temperature of 380°C. To drive a large number of data lines, we used multiple source drivers and data drivers as well. For an optical modulation, we optimized a liquid crystal of a high anisotropic refractive index of 0.25 with a cell gap of 2.5 μm, which was effectively operated until pixel pitch is 1.6 μm. Hologram was successfully reconstructed by fabricated SLM with 7-μm pixel pitch. For the other approach for a high-resolution spatial light modulator, we tested a phase change material of Ge2Sb2Te5 [GST]. The variation of refractive index between a polycrystalline phase and an amorphous phase of the GST film is used for a hologram reconstruction. By optimizing the underlying oxide thickness, we can show a color hologram without color filters. [ABSTRACT FROM AUTHOR]

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme for designing a tunable pixel layer based on a Ge2Sb2Te5 (GST) alloy thin film. We show that the phase change of GST can significantly affect the reflection characteristic when the GST film is embedded into a dielectric encapsulation layer. We investigate the appropriate positions of the GST film within the dielectric layer for high diffraction efficiency, and we prove that they are antinodes of Fabry-Perot resonance inside the dielectric layer. Using the proposed scheme, we can increase the diffraction efficiency by about ten times compared to a bare GST film pixel, and 80 times for the first-to-zeroth-order diffraction power ratio. We show that the proposed scheme can be designed alternatively for a broadband or wavelength-selective type by tuning the dielectric thickness, and we discuss a multiphase example with a double-stack structure. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effects of pre-reducing Sb-doped SnO2 (ATO) electrodes in viologen-anchored TiO2 (VTO) nanostructure-based electrochromic devices. We find that by pre-reducing an ATO electrode, the operating voltage of a VTO nanostructure-based electrochromic device can be lowered; consequently, such a device can be operated more stably with less hysteresis. Further, we find that a pre-reduction of the ATO electrode does not affect the coloration efficiency of such a device. The aforementioned effects of a pre-reduction are attributed to the fact that a pre-reduced ATO electrode is more compatible with a VTO nanostructure-based electrochromic device than a non-pre-reduced ATO electrode, because of the initial oxidized state of the other electrode of the device, that is, a VTO nanostructure- based electrode. The oxidation state of a pre-reduced ATO electrode plays a very important role in the operation of a VTO nanostructure-based electrochromic device because it strongly influences charge movement during electrochromic switching. [ABSTRACT FROM AUTHOR]

Multilayered ZnO-SnO2 heterostructure thin films consisting of ZnO and SnO2 layers are produced by alternating the pulsed laser ablation of ZnO and SnO2 targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and SnO2 layers. The performance parameters of amorphous multilayered ZnO-SnO2 heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and SnO2 layers. A highest electron mobility of 43 cm2/V∙s, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of 1010 are obtained for the amorphous multilayered ZnO(1.5 nm)-SnO2(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnOSnO2 heterostructure film consisting of ZnO, SnO2, and ZnO-SnO2 interface layers. [ABSTRACT FROM AUTHOR]

The poly(ethylene naphthalate) (PEN) substrates have two sides of bare PEN and primer-coated surfaces treated to provide slip property for film production. Although the primer surface showed porous and inhomogeneous morphologies, a hybrid inorganic/organic double-layered barrier layer can effectively improve the surface roughness and permeability. The fabricated amorphous In-Ga-Zn-O thin-film transistors on the PEN substrates with hybrid barrier showed good performances and did not experience any degradation under the mechanical bending situation at a curvature radius of 3.3?mm. The variation in the threshold voltage was evaluated to be approximately -0.1/1.6?V under the negative/positive bias stress tests, respectively. [ABSTRACT FROM AUTHOR]

Fully transparent amorphous-InGaZnO thin-film transistors (TFTs) with double-gate (DG) configuration were fabricated. Both top-gate and bottom-gate (BG) TFT fabricated with a single gate-stack structure were found to exhibit sound device characteristics with μsat of 17.0 and 18.1 cm2 V-1 s-1, respectively. Confirmed benefits of DG configuration include improved current drivability and threshold voltage tunability. Further, controlling the fixed voltage bias to the BG was observed to enhance device stability under negative-bias-illumination-stress conditions. [ABSTRACT FROM AUTHOR]

Multilayered ZnO-SnO2 heterostructure thin films were produced using pulsed laser ablation of pie-shaped ZnO-SnO2 oxides target, and their structural and field effect electronic transport properties were investigated as a function of the thickness of the ZnO and SnO2 layers. The films have an amorphous multilayered heterostructure composed of the periodic stacking of the ZnO and SnO2 layers. The field effect electronic properties of amorphous multilayered ZnO-SnO2 heterostructure thin film transistors (TFTs) are highly dependent on the thickness of the ZnO and SnO2 layers. The highest electron mobility of 37 cm²/V s, a low subthreshold swing of a 0.19 V/decade, a threshold voltage of 0.13 V, and a high drain current on-to-off ratio of ~1010 obtained for the amorphous multilayered ZnO(1.5 nm)-SnO2 (1.5 nm) heterostructure TFTs. These results are presumed to be due to the unique electronic structure of an amorphous multilayered ZnO-SnO2 heterostructure film consisting of ZnO, SnO2, and ZnO-SnO2 interface layers. [ABSTRACT FROM AUTHOR]

We demonstrated the fabrication of flexible amorphous indium gallium zinc oxide thin-film transistors (TFTs) on high-temperature polyimide (PI) substrates, which were debonded from the carrier glass after TFT fabrication. The application of appropriate buffer layers on the PI substrates affected the TFT performance and stability. The adoption of the SiNx/AlOx buffer layers as water and hydrogen diffusion barriers significantly improved the device performance and stability against the thermal annealing and negative bias stress, compared to single SiNx or SiOx buffer layers. The substrates could be bent down to a radius of curvature of 15mm and the devices remained normally functional. [ABSTRACT FROM AUTHOR]

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 ìW at VDD=6 V. It employs 222 transistors and occupies a chip area of 5.85 mm². [ABSTRACT FROM AUTHOR]

In-Ga-Zn-O (IGZO)-channel oxide thin-film transistors (TFTs) were fabricated on flexible polyethylene naphthalate (PEN) substrates. A lamination and delamination procedure was established that allowed easy handling of the PEN substrate during fabrication. In order to fabricate high-performance flexible IGZO TFTs at lower than normal process temperatures, a 2:1:2 (In:Ga:Zn) IGZO channel composition was proposed. The field-effect mobility, threshold voltage, and subthreshold swing of the fabricated IGZO TFTs were found to be approximately 7.83 cm² V-1, s-1, 1.93 V, and 0.24V/decade, respectively, even when a final heat treatment was conducted at a temperature as low as 150 °C. The stability characteristics of the devices were also examined under gate bias stress and constant current stress conditions. [ABSTRACT FROM AUTHOR]

By inserting H2O treatment steps during atomic layer deposition of a ZnO layer, the turn-on voltage shift from negative bias stress (NBS) under illumination was reduced considerably compared to that of a device that has a continuously grown ZnO layer without any treatment steps. Meanwhile, treatment steps without introducing reactive gases, and simply staying under a low working pressure, aggravated the instability under illuminated NBS due to an increase of oxygen vacancy concentration in the ZnO layer. From the experiment results, additional oxidation of the ZnO channel layer is proven to be effective in improving the stability against illuminated NBS. [ABSTRACT FROM AUTHOR]

The nonvolatile memory thin film transistors (MTFTs) using a solution-processed zinc indium oxide (ZIO) active channel and a poly(vinylidene fluoride-trifluoroethylene) ferroelectric gate insulator was proposed and characterized. The spin-coated ZIO films showed good transmittance (∼90%) in the visible range. The crystalline phases are essentially amorphous even after the annealing at 400°C. All fabricated MTFTs exhibited memory behaviors based on the ferroelectric field effect in their transfer characteristics. The on/off ratio, the off current level, and the field-effect mobility were markedly varied with the changes in the annealing temperature and film composition. These differences may originate from the variations in conduction mechanism. The best device performances were obtained for the MTFT using the 83/17 mol % ZIO channel annealed at 400°C. The memory window at the VG sweep of ±15 V, field-effect mobility, subthreshold swing, and on/off ratio were obtained to be 9.6 V, 3.3 cm² V-1 s-1, 0.86 V/dec, and 8.4 × 106, respectively. The memory on/off ratio of more than 500 was retained after a lapse of 10 h. [ABSTRACT FROM AUTHOR]

The electrical characteristics of metal-insulator-semiconductor (MIS) capacitors with Al/Al2O3/ZnO structures were investigated by capacitance-voltage (C-V) measurements. The ZnO films were prepared by plasma-enhanced atomic layer deposition as a common semiconducting layer. The insulators of Al2O3 were composed of a thin protection layer (PL), a first gate insulator, directly deposited on ZnO, and a main gate insulator by changing the oxygen sources (water vapor, in situ generated O2 plasma, and ozone) during atomic layer deposition (ALD). When the PL was prepared by water, good electrical behaviors in C-V measurements such as no voltage hysteresis and normal flatband voltage (VFB) were observed for the capacitors, regardless of the ALD condition for the deposition of the main gate insulator. For the MIS containing a PL deposited with O2 plasma or ozone, the Al2O3/ZnO interfaces were markedly degraded, in which large hystereses and positive shifts of VFB were observed. [ABSTRACT FROM AUTHOR]

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Znoxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si3N4 and Al2O3, the electrical properties are analyzed. After post-annealing at 200°C for 1 hour in an O2 ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogenbased bonds. From constant-current stress tests of Id = 3 μA, an IGZO-TFT with heat-treated Si3N4 IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior. [ABSTRACT FROM AUTHOR]

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication and characterization of metal-insulator-semiconductor (MIS) capacitors using a ZnO semiconducting layer and Al2O3 insulating layer deposited by plasma-enhanced atomic layer and thermal atomic layer deposition, respectively. The sample stack structure is Al2O3/ZnO/ITO. The effects of the ZnO deposition conditions, such as plasma power, film thickness, and oxygen flow rate, on the electrical characteristics of the MIS capacitors were investigated. The thicknesses of the ZnO and Al2O3 layers were changed independently in order to examine the influence of full depletion of carriers on the capacitance-voltage (C-V) characteristics. It was found that the electrical properties of the ZnO thin films changed according to their thickness. This was attributed to a chemical interaction with the under-indium-tin-oxide (ITO) layers during the long growth time (over 2 h), which made it difficult to determine the semiconductor parameters, such as the carrier density. During the process of Al2O3 film deposition, an interfacial layer was grown between the ZnO and Al2O3 films. This interfacial layer deteriorated the C-V characteristics of the MIS capacitors because of the interface state increment. It was found that there was a certain range of ZnO and Al2O3 thicknesses where the optimal properties were achieved. [ABSTRACT FROM AUTHOR]

Presents information on a study that designed and monolithically integrated amorphous silicon thin-film transistor (a-Si TFT) with molybdenum-tip field emitter arrays (FEA) on glass substrate for active-matrix cathodes AMC). Device structure and fabrication procedure; Characteristics of a-Si TFT; Comparison of aging behavior of AMC and simple FEA; Field emission characteristics of AMC device.

A novel strategy to enhance the bias and illumination stress stability of oxide thin-film transistors (TFTs) is presented. The ultrathin positive charge barrier is employed to block the movement of photo-generated charges toward the interface between gate insulator and semiconductor under negative gate bias and illumination. This method can break through the limitation in stability enhancement caused by the inevitable oxygen vacancy and facilitates the fabrication of highly stable oxide TFTs at low process temperature. [ABSTRACT FROM AUTHOR]

P-type thin-film transistors (TFTs) using room temperature sputtered SnOx (x<2) as a transparent oxide semiconductor have been produced. The SnOx films show p-type conduction presenting a polycrystalline structure composed with a mixture of tetragonal β-Sn and α-SnOx phases, after annealing at 200 °C. These films exhibit a hole carrier concentration in the range of ≈1016–1018 cm-3; electrical resistivity between 101–102 Ω cm; Hall mobility around 4.8 cm2/V s; optical band gap of 2.8 eV; and average transmittance ≈85% (400 to 2000 nm). The bottom gate p-type SnOx TFTs present a field-effect mobility above 1 cm2/V s and an ON/OFF modulation ratio of 103. [ABSTRACT FROM AUTHOR]

We characterized the nonvolatile memory thin-film transistors, which was composed of an amorphous indium-gallium-zinc oxide (α-IGZO) active channel and a ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator, and investigated the impact of an interface controlling layer. Excellent device performances, such as the field-effect mobility of 60.9 cm2 V-1 s-1, the subthreshold swing of 120 mV/dec, and the memory window of 6.4 V at ±12 V programming, were confirmed for the device without any interface layer. However, the memory retention time was very short. The retention behaviors could be dramatically improved when 4 nm thick Al2O3 layer was introduced between the P(VDF-TrFE) and α-IGZO. [ABSTRACT FROM AUTHOR]

This study examined the impact of the passivation layer on the light-enhanced bias instability of Al–Sn–Zn–In–O (AT–ZIO) thin film transistors. The suitably passivated device exhibited only a threshold voltage (Vth) shift of 0.72 V under light-illuminated negative-thermal stress conditions, whereas the device without a passivation layer suffered from a huge negative Vth shift of >11.5 V under identical conditions. The photocreated hole trapping model could not itself explain this behavior. Instead, the light-enhanced Vth instability of the unpassivated device would result mainly from the photodesorption of adsorbed oxygen ions after exposing the AT–ZIO back-surface in an ambient atmosphere. [ABSTRACT FROM AUTHOR]

Copper oxide (Cu2O) thin films were used to produce bottom gate p-type transparent thin-film transistors (TFTs). Cu2O was deposited by reactive rf magnetron sputtering at room temperature and the films exhibit a polycrystalline structure with a strongest orientation along (111) plane. The TFTs exhibit improved electrical performance such as a field-effect mobility of 3.9 cm2/V s and an on/off ratio of 2×102. [ABSTRACT FROM AUTHOR]

We fabricated environmentally stable and transparent organic/oxide hybrid transistor on a glass substrate using the conventional photolithography. The obtained device, which was composed of an In-Ga-Zn-O active layer/soluble polyimide (KSPI) organic insulator, showed a mobility of 6.65 cm⊃2/Vs, a subthreshold swing slope of 350 mV/decade, a threshold voltage (VT) of 3.10 V, and an on–off ratio of 3.9 x 109. The transistor also showed good uniformity characteristics and was found to be environmentally stable for 90 days under ambient conditions. [ABSTRACT FROM AUTHOR]

We fabricated high-performance thin-film transistors (TFTs) with an amorphous-Al-Sn-Zn-In-O (a-AT-ZIO) channel deposited by cosputtering using a dual Al-Zn-O and In-Sn-O target. The fabricated AT-ZIO TFTs, which feature a bottom-gate and bottom-contact configuration, exhibited a high field-effect mobility of 31.9 cm2/V . s, an excellent subthreshold gate swing of 0.07 V/decade, and a high Ion/off ratio of > 10°, even below the process temperature of 250 °C. In addition, we demonstrated that the temperature and bias-induced stability of the bottom-gate TFT structure can significantly be improved by adopting a suitable passivation layer of atomic-layer- deposition-derived Al2O3 thin film. [ABSTRACT FROM AUTHOR]

A two-transistor-type nonvolatile memory cell composed of one-access and one-memory thin-film transistors (TFTs) was demonstrated. ZnO and poly(vinylidene fluoride- trifluoroethylene) were employed as semiconducting channels for both TFTs and ferroelectric-gate insulator for memory TFT, respectively, in which the cell structures and fabrication procedures were so carefully designed and optimized as to effectively incorporate both TFTs on the same glass substrate without any critical process damage even below 200 °C. The fabricated memory cell successfully showed the write and nondestructive readout operations. [ABSTRACT FROM AUTHOR]

We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device. [ABSTRACT FROM AUTHOR]

Thin film transistors with a channel of Zn–In–Sn–O were fabricated via a combinatorial rf sputtering method. It was found that the role of the In atoms is to enhance the mobility and to shift the threshold voltage (Vth) negatively. On the other hand, the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface. The optimized transistor was obtained at a compositional ratio of Zn:In:Sn=40:20:40, which exhibited an excellent subthreshold gate swing of 0.12 V/decade, Vth of -0.4 V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 24.6 cm2/V s. [ABSTRACT FROM AUTHOR]

A comparative study is made of the low-frequency noise (LFN) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Al2O3 and Al2O3/SiNx gate dielectrics. The LFN is proportional to 1/fγ, with γ ∼ 1 for both devices, but the normalized noise for the Al2O3/SiNx device is two to three orders of magnitude lower than that for the Al2O3 device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in Al2O3/SiNx devices. The SiNx interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the Al2O3 dielectric. Hooge's parameter is extracted to ∼6.0 × 10-3 in Al2O3/SiNx devices. [ABSTRACT FROM AUTHOR]

A comparative study was made of the performance and electrical instabilities in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors with Al2O3 and Al2O3/SiNx gate dielectrics. Steeper subthreshold slope is observed in Al2O3 devices, which shows that the density of trap states at the interface of a-IGZO/Al2O3 is lower than that of a-IGZO/SiNx. Under high bias-stresses, a larger degradation is observed in Al2O3/SiNx devices. The device degradation for both devices are mainly attributed to the charge trapping phenomenon, but the different time dependence of threshold voltage shift shows that trapped electrons are more easily redistributed inside the Al2O3 dielectrics. [ABSTRACT FROM AUTHOR]

We have investigated the low-frequency noise (LFN) properties of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFT5) as a function of frequency, bias, and channel length of devices. The measured noise power spectral density of drain current (SiD) shows that the low-frequency noise in a-IGZO TFTs obeys the classical 1/f noise theory, i.e., it fits well to a 1/fγ power law with γ ~ 1 in the frequency range of 10 Hz to 1 kHz. From the dependence of normalized noise power spectral density (SiD/ID²) on the gate voltage, mobility fluctuation is considered as a dominant LFN mechanism in a-IGZO TFTs. The magnitude of SiD/ID² is inversely proportional to the channel length of devices, which indicates that contact noise is insignificant in a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

Abstract-We have fabricated the transparent bottom gate thin-film transistors (TFT5) using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron. sputtering at room temperature, and the AT-ZIO TFT showed a field effect mobility of 15.6 cm[sup2]/Vs even before annealing. The mobility increased with increasing the In[sub2]O[sub3] content and postannealing temperature up to 250 °C. The AT-ZIO TFT exhibited a field effect mobility of 30.2 cm[sup2] /Vs,a subthreshold swing of 0.17 V/dec, and an on/off current ratio of more than 10[sup9]. [ABSTRACT FROM AUTHOR]

Phosphorus (P)-doped ZnO thin films were grown by radio-frequency magnetron sputtering to study the microstructural properties of p-type ZnO. As-grown P-doped ZnO, a semi-insulator, was converted to p-type ZnO after being annealed at 800 °C in an N2 ambient. X-ray diffraction, secondary-ion-mass spectrometry, and Hall effect measurements indicated that P2O5 phases in as-grown P-doped ZnO disappeared after thermal annealing to form a substitutional P at an O lattice site, which acts as an acceptor in P-doped ZnO. Transmission electron microscopy showed that the formation of stacking faults was facilitated to release the strain in P-doped ZnO during post-thermal annealing. [ABSTRACT FROM AUTHOR]

This letter presents technologies to fabricate ultra low-temperature (< 150 °C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al2O3 grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm²/V · s (nMOS) and 42 cm²/V · s (pMOS), on/off current ratio of 4.20 × 106 (nMOS) and 5.7 × 105 (pMOS), small Vth of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS). [ABSTRACT FROM AUTHOR]

In this work, a switchable plasmonic structure is proposed for reflection-type spatial light modulation in the visible range with subwavelength resolution. This structure is based on a metallic grating in which each resonant cavity couples the incident light into a gap surface plasmon mode and then reflects the light modulated in the cavity. By incorporating an ultrathin layer of the phase-change material Ge2Sb2Te5 at the entrance of the cavity, the optical modulation characteristic of the structure can be switched between two modes. Numerical investigations are conducted to verify the proposed structure, with the focused analysis of two common types of binary modulations: amplitude-only and phase-only modulations. [ABSTRACT FROM AUTHOR]

The effects of the atomic composition of Ge2Sb2Te5 (GST), especially the Sb-excess phase, on device reliability were investigated for applications of spatial light modulator (SLM) devices using phase-change materials. Sb-excess GST phases were prepared by cosputtering with two target systems. For Sb-excess GST thin films, amorphous phases were found to be more directly crystallized to more conductive hexagonal-close-packing phases at higher crystallization temperatures without the appearance of a less conductive face-centered-cubic phase with increasing amount of incorporated Sb. The marked changes in crystallization behavior and improved thermal stability were suggested as critical benefits for enhancing the device durability during cyclic operations, considering that the interdiffusion within the GST could be the main origin of the final device failure. The number of cyclic operations of the unit pixel device was markedly improved to more than 103 when the amount of excess Sb was modulated from 0 to 21 at. %. [ABSTRACT FROM AUTHOR]

A novel method is proposed for simulating free space field propagation from a source plane to a destination plane that is applicable for both small and large propagation distances. The angular spectrum method (ASM) was widely used for simulating near field propagation, but it caused a numerical error when the propagation distance was large because of aliasing due to under sampling. Band limited ASM satisfied the Nyquist condition on sampling by limiting a bandwidth of a propagation field to avoid an aliasing error so that it could extend the applicable propagation distance of the ASM. However, the band limited ASM also made an error due to the decrease of an effective sampling number in a Fourier space when the propagation distance was large. In the proposed wide range ASM, we use a non-uniform sampling in a Fourier space to keep a constant effective sampling number even though the propagation distance is large. As a result, the wide range ASM can produce simulation results with high accuracy for both far and near field propagation. For non-paraxial wave propagation, we applied the wide range ASM to a shifted destination plane as well. [ABSTRACT FROM AUTHOR]