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Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate.

Authors :
Himchan Oh
Jae-Eun Pi
Chi-Sun Hwang
Oh-Sang Kwon
Source :
Applied Physics Letters; 12/18/2017, Vol. 111 Issue 25, p1-4, 4p, 1 Diagram, 1 Chart, 4 Graphs
Publication Year :
2017

Abstract

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiN<subscript>x</subscript> capping readily increases their carrier concentration. We report that the SiN<subscript>x</subscript> deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiN<subscript>x</subscript> capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00036951
Volume :
111
Issue :
25
Database :
Complementary Index
Journal :
Applied Physics Letters
Publication Type :
Academic Journal
Accession number :
126987968
Full Text :
https://doi.org/10.1063/1.5011079