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The combination of nanohole arrays with photodetectors can be a strategy for the large-scale fabrication of miniaturized and cost-effective refractive index sensors on the Si platform. However, complementary metal–oxide–semiconductor (CMOS) fabrication processes place restrictions in particular on the material that can be used for the fabrication of the structures. Here, we focus on using the CMOS compatible transition metal nitride Titanium Nitride (TiN) for the fabrication of nanohole arrays (NHAs). We investigate the optical properties of TiN NHAs with different TiN thicknesses (50 nm, 100 nm, and 150 nm) fabricated using high-precision industrial processes for possible applications in integrated, plasmonic refractive index sensors. Reflectance measurements show pronounced Fano-shaped resonances, with resonance wavelengths between 950 and 1200 nm, that can be attributed to extraordinary optical transmission (EOT) through the NHAs. Using the measured material permittivity as an input, the measured spectra are reproduced by simulations with a large degree of accuracy: Simulated and measured resonance wavelengths deviate by less than 10 nm, with an average deviation of 4 nm observed at incidence angles of 30° and 40°. Our experimental results demonstrate that an increase in the thickness of the TiN layer from 50 to 150 nm leads to a sensitivity increase from 614.5 nm/RIU to 765.4 nm/RIU, which we attribute to a stronger coupling between individual LSPRs at the hole edges with spatially extended SPPs. Our results can be used to increase the performance of TiN NHAs for applications in on-chip plasmonic refractive index sensors.

Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001). Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation. Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition. To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs. Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1). Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge. These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925 Yamamoto et al. Solid-State Electron. 60 (2010) 2 Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457 J-H. Lee et al. Science 344 6181(2014) 286 M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

Multilayered Ge nanodots have drawn much attention due to their potential applications in optoelectronics, such as photodetectors and lasers. Many groups studied multilayered Ge nanodots with Si spacers on Si(001) grown by Stranski-Krastanov (SK) growth mode and vertically aligned by local tensile strain induced by buried Ge nanodots (1-2). However, to avoid plastic relaxation caused by a 4.2% lattice mismatch between Si and Ge, thick nanodots and/or large layer numbers are challenging. Additionally, laterally-aligned Ge nanodots without pre-structuring have not been reported. In this study, we demonstrate 3-dimensional (3D) self-ordered Ge nanodots on SiGe virtual substrate (VS) by SiGe/Ge cyclic epitaxial growth and show the effects of fabrication parameters. The 3D self-ordered Ge nanodots were fabricated by reduced-pressure chemical vapor deposition. A Si0.4Ge0.6 VS with step-graded buffer deposited on Si(001) wafer was used. This VS was post-annealed at 1000°C, followed by chemical-mechanical polishing. After HF dip, the substrate was baked at 850°C in H2, then cooled down to 550°C for epitaxial growth. A 52-82 nm thick Si0.48Ge0.52 layer was deposited using a H2-SiH4-GeH4 gas mixture, then a self-assembled Ge nanodots layer via SK growth mechanism was deposited with 7.5-15.0 nm Ge coverage using a H2-GeH4 gas mixture. This Si0.48Ge0.52/Ge deposition cycle was repeated 5 to 20 times to fabricate the 3D self-ordered Ge nanodot stack. Atomic force microscopy (AFM) and scanning electron microscopy (SEM) were used to analyze the morphology and alignment of the Ge nanodots. The facets of the Ge nanodots were studied by analyzing the cross-section cuts of AFM images and confirmed by scanning transmission electron microscopy (STEM). Nano-beam diffraction (NBD) was used to study strain in the superlattice. Fig. 1(a-c) show the AFM images of the 5-cycle superlattices with Ge coverage 7.5 to 15.0 nm. In fig. 1(a), we can see mainly two types of nanodots, diamond (32%) and dome (68%). The height of the diamond-like nanodots is 9 nm with a standard deviation (s) of 2.6 nm while that of the dome-like nanodots is 23 nm with s=1.8 nm. With increasing Ge coverage, dome-like nanodots dominate (fig. 1(b)) and some nanodots merge with the adjacent nanodots (fig. 1(c)). Since the dome-like nanodots show a lower s in height than the diamond-like nanodots do, engineering of self-ordering is more feasible with the dome-like nanodot. Fig. 2(a-b) show the angle view of SEM images of Ge nanodots on 5- and 20-cycle superlattice of 12.5 nm-Ge/52 nm-SiGe. The dome-like nanodots are dominant and laterally aligned. The alignment and the uniformity improve with the increasing cycle number of the superlattice. However, when the thickness of Si0.48Ge0.52 spacer increases, the lateral- and vertical alignment of nanodots become random, and the amount of diamond-like nanodots increases (not shown). To study facets of two types of nanodots, the tilt of each facet was calculated from the cross-section cuts of AFM images. Fig. 3(a) shows an AFM image of the dome-like nanodot. Fig. 3(b) shows the cross-section cuts of fig. 3(a) along . These cross-section cuts are well-overlapped with the high-angle annular dark-field (HAADF) STEM image as shown in the background of fig. 3(b). Therefore, it is possible and reliable to estimate the facets from the cross-section cuts of our AFM images. By this method, we confirmed that the diamond-like nanodot is composed of {105} and the dome-like nanodot is composed of {113} and {159}. This is consistent with a study of Ge dot on Si substrate except for {159} facet (3). Instead of {159} facet, a relatively similar facet {3 15 23} was reported. This difference may result from the less compressive strain in our Ge nanodots because SiGe VS was used. To explain the vertical correlation of Ge nanodots, a HAADF STEM image and in- and out-of-plane strain distributions measured by NBD are shown in fig. 4(a-c). The nanodots are vertically aligned (fig. 4(a)). The SiGe on the nanodot shows a relatively higher lattice parameter along (fig. 4(b)) and lower lattice parameter along (fig. 4(c)) compared to that on Ge wetting layer, indicating tensile strain. This tensile strain area is the preferred position for Ge nanodot formation because of less lateral lattice mismatch. Consequently, the nanodots tend to grow above the buried nanodots. 3D self-ordered multilayered Ge nanodots on SiGe VS were successfully fabricated, and the facets and the vertical correlation of Ge nanodots were studied. References P.S. Chen et al. Materials Science and Engineering B 108 (2004) 213-218 K.L. Wang et al. Proceeding of the IEEE 95 (2007) 1866 J.T. Robinson et al. Nanotechnology 20 (2009) 085708 Figure 1

Dislocation free local SiGe-on-insulator virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 µm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2 / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ~1.4% along direction, which is higher compared to that along direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards directions, resulting in wide dislocation-free area formation in SiGe along due to horizontal aspect ratio trapping.

The integration of both optical and electronic components on a single chip, despite the challenge, holds the promise of compatibility with CMOS technology and high scalability. Among all candidate materials, III-V semiconductor nanostructures are key ingredients for opto-electronics and quantum optics devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the opto-electronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on nanotip-patterned (001)Si substrates using gas-source molecular-beam epitaxy. The substrates are fabricated using CMOS nanotechnology. The dimensionality of the InP structures can be switched between two-dimensional nanowires and three-dimensional bulk-like InP islands by thermally modifying the shape of Silicon nanotips, surrounded by the SiO2 layer during the oxide-off process. The structural and optical characterization of nanowires indicate the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II heterointerface.

Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si0.4Ge0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. The Ge nanodots were formed by Stranski-Krastanov mechanism. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and 〈100〉 alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {519} or {15 3 23} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relatively higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer becomes thicker. The Ge content of the SiGe spacer ranging from 45 to 52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. By maintaining the strain balance, ordering of the 3D aligned Ge nanodots can be improved.

We have demonstrated the high–density formation of super–atom–like Si quantum dots with Ge–core on ultrathin SiO2 with control of high–selective chemical–vapor deposition and applied them to an active layer of light–emitting diodes (LEDs). Through luminescence measurements, we have reported characteristics carrier confinement and recombination properties in the Ge–core, reflecting the type II energy band discontinuity between the Si–clad and Ge–core. Additionally, under forward bias conditions over a threshold bias for LEDs, electroluminescence becomes observable at room temperature in the near–infrared region and is attributed to radiative recombination between quantized states in the Ge–core with a deep potential well for holes caused by electron/hole simultaneous injection from the gate and substrate, respectively. The results will lead to the development of Si–based light–emitting devices that are highly compatible with Si–ultra–large–scale integration processing, which has been believed to have extreme difficulty in realizing silicon photonics.

Self-ordered multilayered Ge nanodots with SiGe spacers on a Si0.4Ge0.6 virtual substrate are fabricated using reduced-pressure chemical vapor deposition, and the mechanism of vertical ordering is investigated. The process conditions of Ge and SiGe layer deposition are H2-GeH4 at 550 °C and H2-SiH4-GeH4 at 500 °C–550 °C, respectively. By depositing the SiGe at 550 °C or increasing Ge content, the SiGe surface becomes smooth, resulting in vertically aligned Ge nanodots to reduce strain energy. Ge nanodots prefer to grow on the nanodot where the SiGe is relatively tensile strained due to the buried Ge nanodot underneath. By depositing at 500 °C and lowering Ge content, checkerboard-like surface forms, and the following Ge nanodots grow at staggered positions to reduce surface energy. The Ge nanodots are laterally aligned along the elastically soft 〈100〉 direction without pre-structuring resulting from the strain distribution.

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 μm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ∼400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5 × 106 cm−2 are achieved for both (111) and (110) substrates.

SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO2 /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations. Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO2/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO2/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850oC in H2 to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH2Cl2-GeH4-HCl gas mixture at 750oC. Finally, the top SiO2 is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations. Fig. 1 shows the AFM image for surface morphology of lateral-selective Si0.6Ge0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO2 and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850oC, Si pillar/SiO2 interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO2/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010]. This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices. References E. A. Fitzgerald et al., J. Appl. Phys., 63, 693 (1988). E. A. Fitzgerald et al., Appl. Phys. Lett., 59, 811 (1991). V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008). Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014). Figure 1

In this work, we used EDX, EELS and FTIR spectroscopy to investigate the stoichiometry of oxygen precipitates in Czochralski silicon wafers. The EDX analysis of a plate-like precipitate demonstrated that the composition of the precipitate is SiO1.93. This result was confirmed by EELS where the characteristic plasmon peak of SiO2 was observed. Additionally, the absorption band of plate-like precipitates at 1223 cm−1 was found in the FTIR spectrum measured at liquid helium temperature. It was demonstrated that this band can only be simulated by the dielectric constants of amorphous SiO2.

Let's talk about your flaws\dots{} The authors present nondestructive examination of the crystallographic properties (including crystal size, facet shape, strain, and defects) of lone InP nanocrystals (NC) grown on Si nanostructures. This sort of three-dimensional structured imaging is of great significance in evaluating the quality of the active nanomaterials in fully processed nanoelectronic and nano-optoelectronic devices, even in an $o\phantom{\rule{0}{0ex}}p\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}d\phantom{\rule{0}{0ex}}o$ manner.

The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ∼1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 108 cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ∼5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

Ge growth on Si is essential e.g. for photonics device integration (e.g. Ge photodiode) into Si based CMOS platform (1). However, due to 4.2% of lattice mismatch between Ge and Si, misfit dislocations (MD) and threading dislocations (TD) are introduced for strain relaxation after exceeding critical thickness. In order to realize low-darkcurrent Ge photodiode, improvement of crystallinity is important. High quality Ge growth techniques by combining various annealing techniques (at 800~850oC) are reported (2-3). However, because of low melting point of Ge (937oC), the Ge growth process is typically integrated at the last part of front-end process. Therefore, these annealing processes are affecting device parameters of existing devices. In previous paper, we reported Ge/SiGe superlattice (SL) fabrication and found improvement of TD density (TDD) by increasing Si composition of SiGe in the SL (4). Here we report TDD improvement of Ge by introducing the SL without annealing. Ge growth with SiGe/Ge SL is carried out using reduced pressure chemical vapor deposition system. Si(100) wafers are used. After an HF last cleaning, the wafer is loaded into reactor and baked at 1000oC and cooled down to 600oC in H2 and further cooled down to 350oC in N2. After that 100 nm-thick seed Ge is deposited using N2-GeH4 gas. Then the wafer is heated up to 500oC in H2 and Ge/SiGe superlattice is fabricated using H2-GeH4 and H2-SiH4-GeH4 gases, respectively. Furthermore, 2.8 µm thick Ge is deposited at 550oC using H2-GeH4 gas. Thickness is measured by cross section SEM and spectroscopic ellipsometry. TDD is determined by Secco defect etching technique. Strain and relaxation of Ge and SiGe layers are measured by XRD reciprocal space mapping. Distribution of the MD and the TD are measured by cross section TEM. In the case of direct Ge growth on Si (Fig. 1a), MDs are formed at interface between Ge and Si. TDs are spreading into the Ge layer. Some of the TDs are long and extending to surface. These MD and TD formations are due to the lattice mismatch between Ge and Si. On the other hand, in the case of Ge sample grown on ×20 Si0.3Ge0.7 / Ge SL (Fig. 1b), most of MDs are formed at interface between 100 nm-thick Ge buffer and Si substrate. Additionally high density of TDs are observed in the Ge buffer and the SL layer. In the SL layer, lower TDD is observed in the upper part compared to that in the deeper part. At the interface between upper 2.8 µm thick Ge and the SL layer, MD and high density of TDs toward lateral direction is observed indicating relaxation. TDD in the 2.8 µm thick Ge layer seems to be lower compared to that in Fig. 1a). In the case of direct Ge growth on Si, TDD of ~7.5×108 cm-2 is obtained (Fig. 2). The TDD is comparable to previously reported results (2). By depositing 2.8 µm thick Ge on Si0.2Ge0.8 SL, TDD is decreased to ~5.4×108 cm-2. With decreasing Ge concentration of SiGe layer of the SL, decrease of TDD is observed until 40%. However, by replacing SiGe layers to mono-layers of Si, increased TDD is observed, which might be due to too high strain at interface between Si and SiGe. Figure 3 shows TDD of 2.8 µm thick Ge deposited on Si0.2Ge0.8/Ge SL with different Si0.2Ge0.8 and Ge thickness combination without changing periodicity of the SL. Lower TDD is observed when the 2.8 µm thick Ge is deposited on the SL with higher Si0.2Ge0.8 thickness. Possible reason is higher degree of relaxation of the SL layer. In Fig. 4, TDD of 2.8 µm thick Ge deposited on SLs of various lattice parameters are shown. By reducing lateral lattice parameter of the SiGe/Ge SL by increasing SiGe thickness or Si concentration, TDD decreases. The reduction of the TDD is fitting to one line for both cases. These results indicate that higher plastic relaxation of the SL occurs on the Ge buffer due to increased compressive strain of SiGe in the SL, and the TDD reduction of the Ge on the SL may be caused by similar mechanism of reverse graded buffer. By introducing SiGe/Ge SL, multiple effect of the reverse graded buffer may be expected. Reference (1) S. Lischke et al. Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) , (2014) 29 (2) Y. Yamamoto et al Solid-State Electron. 60 (2011) 2 (3) Y. Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 (4) Y. Yamamoto et al. Jpn. J. Appl. Phys. 59, SGGK10 (2020) Figure 1

The oxygen precipitates formed in Czochralski (CZ) silicon wafers in consequence of the thermal treatment were investigated since many decades. The main reason why so much effort was directed towards these defects was the impact which they have on integrated circuits and properties of silicon wafer itself. Oxygen precipitates can increase the resistivity of CZ silicon, change the wafer strength and cause warpage of the wafers. It was also demonstrated that metal impurities can be effectively trapped at oxygen precipitates in the process of gettering, what is a huge advantage. All these features of the oxygen precipitates require the control of precipitation in the production process of silicon devices. However, this cannot be optimally executed if the features of oxygen precipitates like their composition are not fully known. In spite of the wide knowledge of oxygen precipitation, the composition of oxygen precipitates SiO x still remains under ongoing discussion. This is due to the different x values varying from x=1 to x=2 which can be found in the literature. In this work, we look on the current stage of the investigation on the composition of oxygen precipitates obtained with the help of different techniques. Moreover, we present our recent investigation on the composition of oxygen precipitates carried out by means of energy dispersive X-ray spectroscopy (EDX), electron energy loss spectroscopy (EELS) and Fourier transform infrared spectroscopy (FTIR). The FTIR spectra measured at liquid helium temperature will be compared with the spectra simulated on the basis of experimental results obtained by scanning transmission electron microscopy (STEM). The EDX gives direct information about the composition of oxygen precipitates. However, the analysis of the EDX spectrum requires a special calibration. This is due to the limitation of EDX for light elements like oxygen. The intensity of characteristic X-rays of oxygen depends on the thickness of TEM lamellae. Therefore, in this work we measured a thermally grown SiO2 layer at different thickness of TEM lamellae in order to determine the influence of the lamellae thickness on the intensity of oxygen characteristic X-rays. After doing this, we measured the composition of oxygen precipitates located at very thin TEM lamellae. The results shown that x is in the range between 1.8 and 1.9 (1). To make sure that the EDX results are correct EELS measurements were carried out. EELS is a complementary method to EDX. It allows to avoid the limitation of EDX in the measurement of the composition of oxygen precipitate especially in the case if the precipitate does not go through the TEM lamellae. Deconvoluting the characteristic plasmons of Si, SiO2 and suboxides in the electron energy loss spectra we found that the oxygen precipitate consist of SiO2 and it is coated by thin 2-3nm SiO layer (2). Finally, we investigated the composition of oxygen precipitates by FTIR. The absorption band of oxygen precipitates were observed in FTIR spectra measured at liquid helium temperature. The position and the shape of the bands fit very well to the simulated spectra. The simulation of the spectra was conducted on the basis of the effective medium theory (EMT) where we considered SiO2 spheroids coated by SiO layers embedded in a Si matrix. In summary, the composition of oxygen precipitates was investigated by EDX, EELS and FTIR whereby the first two methods are direct methods and the latter one is an indirect method. All methods delivered similar results. Hence, we can conclude that the oxygen precipitates consist of a SiO2 core which is coated by an SiO layer. References 1D. Kot, G. Kissinger, M. A. Schubert, M. Klingsporn, A. Huber, and A. Sattler, Phys. Status Solidi RRL 9, 405 (2015). 2G. Kissinger, D. Kot, M. Klingsporn, M.A. Schubert, A. Sattler, T. Müller, ECS J. Solid State Sci. Technol. 4 (9), N124-N129 (2015).

In a previous work, we found that both the interface between an oxide precipitate and the surrounding silicon matrix and the interface between a silicon substrate and a thermal oxide layer are of the same nature [1]. In both cases, between SiO2 existing in the center of the precipitate and in the oxide layer and Si of the matrix and the substrate a suboxide region of 2-3 nm exists. These results were obtained by electron energy loss spectrometry (EELS) carried out by scanning transmission electron microscopy (STEM). In the low loss region, it is possible to distinguish between Si, SiO, and SiO2 which all exhibit different maxima of the plasmon loss energy. By deconvolution, the local composition of the phase can be determined with the help of reference spectra of the three components. The stoichiometry of the oxide precipitates (SiO x ) was debated for a long time and application of different methods on different samples containing oxygen precipitates resulted in different values for x ranging from 1 to 2. Recently, it was demonstrated by applying several direct and indirect methods that the oxide precipitates consist of SiO2 [2]. Inspired by the results in Ref. 1 and 2, a layer model was proposed explaining the different values for x for oxide precipitates of different geometry [3]. Especially, for plate-like precipitates with a large surface the lower x values could be explained. Now the question came up if the width of the interface between Si and SiO2 is constant for all growth temperatures because from interface physics it could be expected that its width increases with temperature. Another point is, if the thickness of oxide layer or oxide precipitates plays a role. For this reason, we again used thermal oxide layers on (100) silicon of different thickness grown at different temperature to investigate the composition profile across the interface. We also compared the results with profiles from plate-like oxide precipitates grown at different temperatures. A scanning transmission electron microscope (STEM) FEI Tecnai Osiris equipped with tools for energy dispersive X-ray spectroscopy (EDX) analysis and EELS was used to analyze the interface and composition of a plate-like precipitates located at a very thin place of the lamella prepared from the sample by grinding, polishing, and ion milling. The profiles of the x values across the interfaces of the oxide layers and the precipitates were determined from the deconvolution of the Si, SiO, and SiO2 EELS spectra. The results of these investigations demonstrate that the stoichiometry of SiO2 (x=2) cannot be reached if the oxide layer thickness is lower than 10 nm for thermal oxides grown at 900 °C. The lower the thickness of the layer is the lower is the maximum x value. This is due to an interface layer of equal maximum slope for all oxide layers. The slope was obtained from fitting by sigmoid functions. Such interface layers were also found for the oxide precipitates but the maximum slope is lower. It was found to increase with increasing diffusion length of interstitial oxygen. The maximum of the x profiles also depends on the thickness of the plate-like oxide precipitates. The results will be discussed with respect to the phase separation process leading to precipitation of interstitial oxygen in silicon. References [1] G. Kissinger, D. Kot, M. Klingsporn, M.A. Schubert, A. Sattler, T. Müller, ECS J. Solid State Sci. Technol. 4 (9), N124-N129 (2015). [2] D. Kot, G. Kissinger, M. A. Schubert, M. Klingsporn, A. Huber, and A. Sattler, Phys. Status Solidi RRL 9, 405 (2015). [3] J. Vanhellemont, Phys. Status Solidi RRL 9, 597 (2015).

We investigate the distribution of Sn in GeSn nano-heteroepitaxial clusters deposited at temperatures well exceeding the eutectic temperature of the GeSn system. The 600 °C molecular beam epitaxy on Si-patterned substrates results in the selective growth of GeSn nano-clusters having a 1.4 ± 0.5 at% Sn content. These nano-clusters feature Sn droplets on their faceted surfaces. The subsequent deposition of a thin Ge cap layer induced the incorporation of the Sn atoms segregated on the surface in a thin layer wetting the nano-dots surface with 8 ± 0.5 at% Sn. The presence of this wetting layer is associated with a relatively strong photoluminescence emission that we attribute to the direct recombination occurring in the GeSn nano-dots outer region.

Alignment control of three dimensional (3D) SiGe nanodot arrangements is investigated using a reduced pressure chemical vapor deposition system. Several cycles of SiGe layers with 30% Ge content and Si spacers are deposited by SiH4-GeH4 at 550 °C and SiH4 or SiH2Cl2 at 700 °C, respectively, to form a 3D SiGe nanodot structure. By using SiH4 as a precursor for the Si spacer deposition, SiGe nanodots are aligned at staggered positions resulting in a body-centered tetragonal (BCT) structure, because a checkerboard mesa structured Si surface is formed and the next SiGe nanodot formation occurs at the concave region to reduce surface energy. On the other hand, after planarizing the Si surface with checkerboard structure by chemical mechanical polishing (CMP), the new SiGe nanodot formation occurs directly above the embedded SiGe nanodot located nearest to the Si surface (dot-on-dot). The driving force seems to be local tensile strain formed at the Si surface above the embedded SiGe nanodot. By using SiH2Cl2 as precursor for the Si spacer deposition, a smooth Si surface can be realized on BCT SiGe nanodot structures without CMP process resulting in a vertically aligned SiGe nanodot formation. The local tensile strain formation in Si above SiGe nanodots is confirmed by nano beam diffraction analysis.

The results of this work have shown that for microelectronic applications, gettering at dislocations is less important and oxygen precipitates are the main getter sink for Cu. Sufficient gettering of Cu in samples contaminated with low Cu concentration requires a higher density and larger oxygen precipitates compared to samples contaminated with high Cu concentration. It is demonstrated that the getter efficiency depends on the contamination level of the samples and getter test with low contamination level must be applied for microelectronic applications. Furthermore, a getter test for 3D chip stack technologies was developed. It was shown that although the wafers are thinned to a thickness of 50 μm their getter efficiency seems to be higher than for wafers of the original thickness. This is assumed to be due to the higher Cu concentration in the thinner wafers which can be gettered easier. It is also demonstrated that BMDs can getter Cu impurities even if the temperature does not exceed 300 °C. The getter efficiency tends to be higher if the samples are stored under day light and not in the dark.

Lateral solid phase epitaxy (L-SPE) in non-doped or in-situ B-doped amorphous- (a-) SiGe deposited on SiO 2 patterned Si(100) wafers by in-situ postannealing in reduced pressure chemical vapor deposition system was investigated for possible heterojunction bipolar transistor (HBT) base link resistivity improvement. Using Si 2 H 6 as Si precursor gas, an epitaxial and amorphous layer was grown on the mask window and on the SiO 2 area, respectively. By inserting a-Si buffer underneath, the deposited a-SiGe surface became smoother. After the L-SPE process, an improved L-SPE length was observed due to suppressed random nucleation on SiO 2 . The L-SPE length increased with increasing postannealing time and saturated due to random poly-grain formation on the SiO 2 . At the same L-SPE time, increased L-SPE length was observed at higher temperature and at higher Ge concentration. With increasing B concentration in the a-SiGe, the L-SPE length firstly increased. However, after reaching 2 × 10 19 atom/cm 3 , the L-SPE length reduced again down to the undoped case. These results of L-SPE process might have potential to improve dynamic performance of SiGe HBT by reducing the base link resistivity by widening the monocrystalline region around bipolar window.

In this work, we investigated the stoichiometry of oxygen precipitates in Czochralski silicon wafers. The thickness dependence of the Cliff–Lorimer sensitivity factor for the silicon/oxygen system was determined and applied for the investigation of the stoichiometry of oxygen precipitates by EDX. The results show that both plate-like oxygen precipitates and a transitional form between plate-like and octahedral precipi- tates consist of SiO2. This was confirmed by EELS low loss spectra where the typical spectrum for amorphous SiO2 was observed. Moreover, the absorption band of plate-like precipitates at 1227 cm–1 was found in the low temperature FTIR spectrum. It was demonstrated that this band can only be simulated by the dielectric constants of amorphous SiO2. (© 2015 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

A CMOS compatible AlN/SiO2/Si3N4/Si(100) surface acoustic wave (SAW) device has been fabricated and will be compared with standard AlN/SiO2-based devices. The presented filter demonstrates high potential for CMOS integrated high-frequency SAW devices. The filter insertion loss could be improved to −12.8 dB. The device exhibits high crosstalk suppression of −50 dB on a standard Si-substrate (10 $\Omega $ cm). X-ray diffraction, (scanning) transmission electron microscopy, and energy dispersive X-ray spectroscopy studies correlate the signal quality with $c$ -axis orientation of aluminum nitride films on interdigitated transducer finger electrodes. Finite-element method simulations are in good agreement with the electric measurements and show typical Rayleigh particle displacement.

One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2–3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0151509jss] All rights reserved.

Dislocation generation and propagation during flash lamp annealing for 20 ms was investigated using wafers with sawed, ground, and etched surfaces. Due to the thermal stress resulting from the temperature profiles generated by the flash pre-existing dislocations propagate into the wafer from both surfaces during flash lamp annealing. A dislocation free zone was observed around 700 μm depth below the surface of a 900 μm thick sawed wafer. The dislocation propagation can be well described by a three-dimensional mechanical model. It was further demonstrated that in wafers being initially free of dislocations no dislocations are generated during flash lamp annealing. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0151507jss] All rights reserved.

Self-ordered three-dimensional body-centered tetragonal (BCT) SiGe nanodot structures are fabricated by depositing SiGe/Si superlattice layer stacks using reduced pressure chemical vapor deposition. For high enough Ge content in the island (>30%) and deposition temperature of the Si spacer layers (T > 700 °C), we observe the formation of an ordered array with islands arranged in staggered position in adjacent layers. The in plane periodicity of the islands can be selected by a suitable choice of the annealing temperature before the Si spacer layer growth and of the SiGe dot volume, while only a weak influence of the Ge concentration is observed. Phase-field simulations are used to clarify the driving force determining the observed BCT ordering, shedding light on the competition between heteroepitaxial strain and surface-energy minimization in the presence of a non-negligible surface roughness.

The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO2 based memristive cells is studied. An extensive characterization of HfO2 based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between the deposition condition and the precursor chemistry with the resulting physical cells characteristics.

On the way to integrate lattice mismatched semiconductors on Si(001) we studied the Ge/Si heterosystem with the aim of a misfit dislocation free deposition that offers the vision to integrate defect-free alternative semiconductor structures on Si. Periodic Ge nano-structures (dots and lines) were selectively grown by chemical vapor deposition on Si nano-islands on silicon on insulator substrate with a thin (about 10 nm) SiGe buffer layer between Si and Ge. The strain state of the structures was measured by grazing incidence and specular diffraction using laboratory-based X-ray diffraction technique. The SiGe improves the compliance of the Si compared to direct Ge deposition, prevents plastic relaxation during growth, and allows elastic relaxation before Ge is deposited on top. As a result, an epitaxial growth of Ge on Si fully free of misfit dislocations was achieved.

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0071411jss] All rights reserved.

One way to further increase performance and/or functionality of Si micro-and nanoelectronics is the integration of alternative semiconductors on silicon (Si). We studied the Ge/Si heterosystem with the aim to realize a Ge deposition free of misfit dislocations and with low content of other structural defects. Ge nanostructures were selectively grown by chemical vapor deposition on periodic Si nanoislands (dots and lines) on SOI substrate either directly or with a thin (about 10 nm) SiGe buffer layer. The strain state of the structures was measured by different laboratory-based x-ray diffraction techniques. It was found that a suited SiGe buffer improves the compliance of the Si compared to direct Ge deposition; plastic relaxation during growth can be prevented, and fully elastic relaxation of the structure can be achieved. Transmission electron microscopy confirms that the epitaxial growth of Ge on nanostructured Si is free of misfit dislocations.

Two getter tests were carried out in order to study the getter efficiency of oxygen precipitates in silicon samples contaminated with low and high Cu concentration. The samples were pre-treated by RTA followed by annealing in the temperature range between 700 °C and 1000 °C for various times in order to establish different concentrations and different sizes of oxygen precipitates in the samples. From the analysis of the results of the normalized inner surface and the gettering efficiency, it was deduced that in highly contaminated samples Cu precipitates more easily at dislocations than at the surface of oxygen precipitates. Contrarily, in the samples contaminated with low Cu concentration the presence of dislocations does not improve the getter efficiency. Cu precipitates were found at the edge of a plate-like precipitate in a sample with low Cu concentration.

Selective epitaxial growth of Ge on nanostructured Si islands on silicon-on-insulator substrates is investigated by X-ray diffraction and transmission electron microscopy to prove the compliance effect between the materials and the structural perfection, especially under the use of a thin SiGe buffer layer., On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III–V and II–VI materials.

We present a photonic BiCMOS process enabling for monolithically integrated Si-based transceiver front-ends towards single-wavelength 400 Gb/s data rate by combining segmented Mach-Zehnder-Interferometer modulators and high-speed germanium photo detectors with high-performance electronics.

The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO2 matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

The influence of RTA pre-treatments on the morphology of oxygen precipitates in silicon wafers as deduced from haze getter tests was confirmed by FTIR and TEM investigations. Based on the results of the getter tests, the ratio between the density of plate-like and octahedral precipitates was calculated for RTA pre-treated silicon samples.

The selective epitaxial growth of germanium on nano-structured periodic silicon pillars and bars with 360 nm periodicity on Si(001) substrate is studied to evaluate the applicability of nano-heteroepitaxy on the Ge–Si system for different fields of application. It is found that SiO 2 used as masking material plays the key role to influence the strain situation in the Si nano-islands. To analyze this in detail, X-ray diffraction techniques in combination with theoretical simulations based on the kinematical X-ray scattering from laterally strained nano-structures and finite element method (FEM) calculations of the strain field are applied. The oxide related strain in the Si scales about linearly with the thickness of the SiO 2 mask, but FEM simulations supposing a homogeneous stress distribution in the oxide are not sufficient to describe the local strain distribution in the nano-structures. It is demonstrated that the Ge lattice relaxes completely during growth on the Si nano-islands by generation of misfit dislocations at the interface, but a high structural quality of Ge can be achieved by suited growth conditions.

The solid phase epitaxy (SPE) of undoped amorphous Si (a-Si) deposited on SiO2 patterned Si(001) wafers by reduced pressure chemical vapor deposition (RPCVD) using a H2–Si2H6 gas system was investigated. The SPE was performed by applying in-situ postannealing directly after deposition process. By transmission electron microscopy (TEM) and scanning electron microscopy, we studied the lateral SPE (L-SPE) length on sidewall and mask for various postannealing times, temperatures and a-Si thicknesses. We observed an increase in L-SPE growth for longer postannealing times, temperatures and larger Si thicknesses on mask. TEM defect studies revealed that by SPE crystallized epi-Si exhibits a higher defect density on the mask than at the inside of the mask window. By introducing SiO2-cap on the sample with 180 nm Si thickness following postannealing at 570 °C for 5 h, the crystallization of up to 450 nm epi-Si from a-Si is achieved. We demonstrated the possibility to use this technique for SiGe:C heterojunction bipolar transistor (HBT) base layer stack to crystallize Si-buffer layer to widen the monocrystalline region around the bipolar window and to improve base link resistivity of the HBT.

Dislocation networks are one of the most principle sources deteriorating the performances of devices based on lattice-mismatched heteroepitaxial systems. We demonstrate here a technique enabling fully coherent germanium (Ge) islands selectively grown on nanotip-patterned Si(001) substrates. The silicon (Si)-tip-patterned substrate, fabricated by complementary metal oxide semiconductor compatible nanotechnology, features ∼50-nm-wide Si areas emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy growths result in Ge nanoislands with high selectivity and having homogeneous shape and size. The ∼850 °C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 atom % Ge). Nanotip-patterned wafers result in geometric, kinetic-diffusion-barrier intermixing hindrance, confining the major intermixing to the pedestal region of Ge islands, where kinetic diffusion barriers are, however, high. Theoretical calculations suggest that the thin Si/Ge layer at the interface plays, nevertheless, a significant role in realizing our fully coherent Ge nanoislands free from extended defects especially dislocations. Single-layer graphene/Ge/Si-tip Schottky junctions were fabricated, and thanks to the absence of extended defects in Ge islands, they demonstrate high-performance photodetection characteristics with responsivity of ∼45 mA W(-1) and an Ion/Ioff ratio of ∼10(3).

Solid-phase epitaxy (SPE) of in situ As-doped amorphous Si (a-Si) deposited on SiO 2 /Si 3 N 4 patterned Si (1 0 0) wafers by reduced pressure chemical vapour deposition (RPCVD) using a H 2 –Si 2 H 6 gas system was investigated. The SPE was performed by applying in situ postannealing directly after deposition process. On the one hand, we studied the lateral SPE (L-SPE) length of As-doped Si on mask and their crystal quality by TEM/SEM characterisation for various postannealing temperatures (700–1000 °C for 60 s). We observed increase in L-SPE growth and decrease of dislocation density for higher postannealing temperatures. On the other hand, L-SPE length was also investigated for different postannealing times (0–120 min at 575 °C) and As concentrations. At these conditions the L-SPE length has increased with increasing postannealing time. For both, higher and lower annealing temperature region, crystallization has been inhibited for higher As concentrations. After modifying As-doping level, we were able to crystallize up to 500 nm of a-Si on mask to epi-Si by combination of 575 °C and 1000 °C postannealing.

A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of 1.7 V along with high-voltage HBTs (fT = 50 GHz,fmax = 130 GHz, BVCEO = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

Technologies of group IV semiconductor fabrication enable new artificial materials such as superlattice and nanodot structures (1). In particular, three dimensional (3D) ordered SiGe or Ge structures are promising materials to improve quantum dot lasers that can be integrated into existing CMOS platforms (2). In order to control regularly ordered nucleation sites, usually pre-patterning of the substrate is required. In the case of 3D stacking of Ge nanodots on Si substrates, the Ge nanodots tend to grow vertically aligned, due to the elastic strain field of the buried Ge nanodots (3). In a previous study, we reported a self-ordered body-centered tetragonal (BCT) SiGe nanodot formation using reduced pressure (RP) CVD, by repeating SiGe and Si layer stack deposition (4). By repeating several cycles of the SiGe and Si layer stack deposition, checkerboard Si mesas are formed on embedded SiGe dots and next SiGe dots are formed in concave region between the Si mesas. In this study we discuss the influence of Si surface roughness on the Ge nanodot formation and present a self-ordered 3D Ge nanodot formation. 3D Ge nanodot layer stack fabrication is carried out by using a single wafer RPCVD system. Standard Si (100) wafers are used. After H2 bake in the reactor, GeH4 is injected at 550°C to form Ge nanodots. Then a Si cap is deposited using H2-SiH4 at 600°C followed by H2-SiH2Cl2 at 700°C. In order to investigate the influence of surface roughness and strain on the Ge nanodot formation, a checkerboard Si mesa with ~7 nm height is fabricated by BCT Si0.6Ge0.4 nanodot layer stacks (4) for selected samples. Surface morphology is measured by AFM and SEM. Alignment of the Ge nanodots is measured by cross section SEM and TEM. Periodicity is measured by X-ray diffraction. By GeH4 exposure at 550°C Ge nanodots (Diameter: ~50, height: 2 nm) with ~6×1010 cm-2 were randomly formed on the Si surface. By postannealing at 600°C, migration of the Ge nanodots occurs resulting in larger Ge nanodots (Diameter: ~60 nm, height: 5 nm) and lower density (~1.5×1010 cm-2) as shown in Fig. 1. On the other hand, in the case of the checkerboard mesa structured Si surface fabricated by BCT Si0.6Ge0.4 nanodot underneath (RMS: 1.2 nm) (Fig. 2a), Ge nanodots are formed in concave region (Fig. 2b). This phenomenon is also observed for SiGe nanodot (4). The position of the Ge nanodot formation seems to be determined by a balance of strain field over embedded SiGe dots and surface energy. In this case, surface energy reduction seems to be more dominant compared to strain at the Si surface transferred from embedded Si0.6Ge0.4. In Fig 3, a cross section STEM image of 6 layers of Ge nanodot with Si spacer layer stack on the staggered aligned SiGe nanodot is shown. The Ge nanodots are vertically aligned. As shown in Fig. 2b, the first Ge nanodots are formed in the concave regions of the Si surface, therefore the first Ge nanodots are aligned to embedded SiGe nanodots underneath. By depositing a Si cap layer on the first Ge nanodots, a smoother Si surface (RMS: 0.5 nm) is formed compared to the initial checkerboard structure. By following GeH4 exposure, a second Ge nanodot formation occurred on the embedded Si surface. The aligned Ge nanodot formation seems to be driven by the tensile strain field at the Si surface above embedded Ge nanodots, because of a smooth Si surface. In Fig. 4a and 4b, nano beam diffraction (NBD) images of out-of-plane and in-plane strain distribution of the vertically aligned Ge nanodot structure are shown, respectively. The positions of the Ge nanodots are visible by higher vertical lattice parameter (Fig. 4a). In the Si part, smaller vertical lattice parameters are observed above the Ge nanodots compared to other area, indicating that the Si on the Ge nanodot is tensile strained. In the lateral lattice parameter distribution (Fig. 4b), only a periodic strain variation is visible, but to identify the position of the Ge nanodot is not possible, indicating that the 3D Ge nanodot stack is pseudomorphically grown. These NBD results support the assumption of Ge nanodot alignment discussed in Fig. 3. In this study we demonstrated self-ordered and vertically aligned Ge nanodot layer stack fabrication. Reference (1) K. L. Wang et al., Mat. Sci. in Semicond. Proc. 8 (2005) 389 (2) G. Capellini et al., Appl. Phys. Lett. 82 (2003) 1772 (3) Y. Nakaumura et al., Nanotechnology 21 (2010) 095305 (4) Y. Yamamoto et al., Nanotechnology 28 (2017) 485303 Figure 1

Silicon (Si)-based group IV materials form the backbone of our digital society, being found in every smartphone and tablet. They, however, lack the possibility to efficiently emit and detect light, because of their indirect bandgap. A truly Si-compatible direct bandgap material allows merging of state-of-the-art CMOS technology on-chip with photonic components to tackle bottlenecks of modern electronics by radically reducing the required power consumption or increasing the available data bandwidth [1]. Alloying the group IV elements germanium (Ge) and tin (Sn) has turned out to be a viable solution, as a direct bandgap semiconductor – even suitable for lasing – is formed for relaxed epilayers with Sn incorporation above ∼9 at.% [2]. The value of the bandgap can further be controlled by adding Si into GeSn, which can be exploited for carrier confinement inside heterostructures [3]. In this contribution, we discuss the epitaxy of various Sn-based group IV alloys. Different heterostructure designs combine direct bandgap active layers, ternary barriers and a GeSn buffer technology. In Figure 1a, a TEM micrograph of a SiGeSn/GeSn/SiGeSn double heterostructure (DHS) is presented, overlapped with the elemental distribution taken by energy-dispersive X-Ray spectroscopy (EDX). A Sn incorporation of roughly 14.5 at.% ensures a direct bandgap inside the active region. Another approach facilitates direct bandgap GeSn multi quantum wells (MQW), sandwiched between SiGeSn barriers. Atom Probe Tomography (APT) allows to obtain precise elemental distribution within this complex heterostructure stack, as is demonstrated in Figure 1b. Techniques such as temperature-dependent photoluminescence are used to compare the optical properties of the grown heterostructures. Moreover, the impact of quantum confinement on MQW emission is revealed, backed up by bandstructure calculations. Optically pumped microdisk resonators are formed to demonstrate lasing from different types of heterostructures, as shown in Figure 1c. As depicted in the inset, the superiority of MQW structures over DHSs (and bulk GeSn layers) is demonstrated, leading to an order of magnitude reduced lasing thresholds at cryogenic temperatures. In the next step of integrated light emitters, carriers need to be injected electrically, rather than optically. We will show first experiments on epitaxially grown p-i-n heterostructure diodes. In Figure 1d, incorporation of phosphorus and boron for the formation of n- and p-doped carrier injection layers is shown by SIMS. We will further point towards possible improvements that may pave the way towards future energy efficient opto-electronic integrated circuits (OEICs). [1] L. Vivien, Computer technology: Silicon chips lighten up, Nature. 528 (2015) 483–484. [2] S. Wirths, R. Geiger et al., Lasing in direct-bandgap GeSn alloy grown on Si, Nat. Photonics. 9 (2015) 88–92. [3] N. von den Driesch et al., Advanced GeSn/SiGeSn Group IV Heterostructure Lasers, Adv. Sci. (2018). doi:10.1002/advs.201700955. Figure 1

With the introduction of the Czochralski method for growing of silicon single crystals oxygen in silicon became an issue with positive and negative impact on silicon devices. On the one hand the oxygen strengthens the wafers against slip dislocation formation, on the other hand precipitating oxygen in the device active area can degrade the device performance. However, oxygen precipitates in the bulk are beneficial because they act as gettering sinks for metallic impurities and thus can improve the device performance. Therefore, oxygen is a major issue in silicon defect engineering. Extensive research on oxygen precipitation started in the seventies of the 20th century and it is still ongoing because new tools become available which offer new possibilities of characterization, higher resolution and lower detection limits. In the field of modeling, the tremendous advances of computer technique and software during the last decades made it possible for a much broader community to run larger models and to make predictions being much more sophisticated. The challenges of defect engineering in silicon device technology changed over the years. In the eighties, two or three step heat treatments were applied to out-diffuse the interstitial oxygen from the device active area followed by nucleation and growth of oxygen precipitates. This procedure is very time consuming. In the nineties, a new RTA based method was discovered. Vacancy profiles, which controlled the spatial distribution of oxygen precipitation in the wafers, were generated by high temperature RTA treatment. During this method, the oxygen does not diffuse out. Because intrinsic point defects are very fast diffusors, a good adjustment to the following device process has to be made. Today, one of the major requirements of high end silicon device technology is void-free silicon because with ongoing decreasing feature size voids became a major yield decreasing problem. There are several solutions to this issue like the growth of void-free silicon crystals and void dissolution in silicon wafers by heat treatment at very high temperature. Both methods are strongly connected with oxygen precipitation. Growth of nearly void-free silicon often leads to radial inhomogeneities of the concentrations of intrinsic point defects [1, 2]. The challenge of defect engineering is to create a radially homogeneous concentration of oxygen precipitates. The ongoing increase of wafer diameter imposes additional problems to oxygen precipitation. If the density of oxide precipitates becomes too high, overlay problems in mask alignment occur [3]. This requires new adjustments of oxygen precipitation. The low feature size in addition to the large wafer diameter asks for low thermal budget processing. A new problem arises because the oxygen precipitates need a certain surface and density to be able to getter enough metallic impurities. Examples from our own recently published results about ab initio calculation for understanding of the initial stages of oxygen precipitation [4], EELS investigation of the stoichiometry of oxygen precipitates [5], the gettering mechanism of Cu at oxygen precipitates [6], and N-doping for the homogeneous oxygen precipitation during high temperature annealing in wafers optimized with respect to voids [1, 2] will be presented. In summary, it can be said that oxygen in silicon remains an ongoing issue. Control of oxygen precipitation becomes more and more demanding for high end device technologies. Oxygen precipitation is not yet fully understood but the current developments of diagnostic methods allow new insights. [1] G. Kissinger, G. Raming, R. Wahlich, T. Müller, 300 mm Czochralski silicon wafers optimized with respect to voids with laterally homogeneous oxygen precipitation, Physica B 407, 2993 (2012). [2] G. Kissinger, G. Raming, R. Wahlich, T. Müller, Nitrogen doped 300mm Czochralski silicon wafers optimized with respect to voids with laterally homogeneous internal getter capabilities, Mat. Sci. Forum 725, 221 (2012). [3] K. Izunome, Advanced silicon wafers for leading-edge semiconductor devices, Proceedings of the 6th Int. Symposium on Advanced Science and Technology of Silicon Materials (JSPS Symposium), Nov. 19-23, 2012, Kona, Hawaii, USA, pp. 9-13. [4] G. Kissinger, J. Dabrowski, T. Sinno, Y. Yang, D. Kot, A. Sattler, Ab initio calculations and rate equation simulations for vacancy and vacancy-oxygen clustering in silicon, J. Cryst. Growth 468, 424 (2017). [5] G. Kissinger, M. A. Schubert, D. Kot, T. Grabolla, Investigation of the composition of the Si/SiO2 interface in oxide precipitates and oxide layers on silicon by STEM/EELS, ECS J. of Solid State Sci. and Technol. 6, N54 (2017). [6] G. Kissinger, D. Kot, M. Klingsporn, M. A. Schubert, A. Sattler, T. Müller, Investigation of the copper gettering mechanism of oxide precipitates in silicon, ECS J. of Solid State Sci. and Technol. 4, N124 (2015).

A microelectronic biosensor was subjected to in vivo exposure by implanting it in the vicinity of m. trapezii (Trapezius muscle) from cattle. The implant is intended for the continuous monitoring of glucose levels, and the study aimed at evaluating the biostability of exposed semiconductor surfaces. The sensor chip was a microelectromechanical system (MEMS) prepared using 0.25 µm complementary metal–oxide–semiconductor CMOS/BiCMOS technology. Sensing is based on the principle of affinity viscometry with a sensoric assay, which is separated by a semipermeable membrane from the tissue. Outer dimensions of the otherwise hermetically sealed biosensor system were 39 × 49 × 16 mm. The test system was implanted into cattle in a subcutaneous position without running it. After 17 months, the device was explanted and analyzed by comparing it with unexposed chips and systems. Investigations focused on the MEMS chip using SEM, TEM, and elemental analysis by EDX mapping. The sensor chip turned out to be uncorroded and no diminishing of the topmost passivation layer could be determined, which contrasts remarkably with previous results on CMOS biosensors. The negligible corrosive attack is understood to be a side effect of the semipermeable membrane separating the assay from the tissue. It is concluded that the separation has enabled a prolonged biostability of the chip, which will be of relevance for biosensor implants in general.