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In this paper, we propose an effective neural network algorithm to perform singular value decomposition (SVD) of a cross-correlation matrix between two data streams. Different from traditional algorithms, the newly proposed algorithm can extract not only the principal singular vectors but also the corresponding principal singular values. First, a dynamical system is obtained from the gradient flow, which is obtained from optimization of a novel information criterion. Then, based on the dynamical system, a stable neural network algorithm, which can extract the left and right principal singular vectors, is obtained. Moreover, by satisfying orthogonality instead of orthonormality, we are able to extract the normalization scale factor as the corresponding singular value. In this case, the principal singular triplet (principal singular vectors and the corresponding singular value) of the cross-correlation matrix can be extracted by using the proposed algorithm. What’s more, the proposed algorithm can also be used for multiple PSTs extraction on the basis of sequential method. Then, convergence analysis shows that the proposed algorithm converges to the stable equilibrium point with probability 1. Last, experiment results show that the proposed algorithm is fast and stable in convergence, and can also extract multiple PSTs efficiently.

Generalized eigenvalue decomposition has many advantages when it is applied in modern signal processing. Compared with other methods, neural network model-based algorithms provide an efficient way to solve such problems online. Generalized feature extraction algorithms based on neural network models have been described in the literature. However, the majority of the existing algorithms can only extract the principal generalized eigenvector(s) or eigensubspace. To extract principal and minor generalized eigenvectors from two vector sequences, in this paper, two different information criteria are proposed, and a unified algorithm for the extraction of multiple components in a parallel way by simply altering the sign is derived based on these information criteria, which is feasible for generalized principal and minor component analysis. Moreover, all the corresponding principal and minor generalized eigenvalues can be extracted simultaneously because the desired equilibrium point depends on these values. Thus, the proposed algorithm can perform multiple generalized eigenpair extraction. The proposed algorithm possesses four properties: unification, self-stability, parallel extraction and generalized eigenpair extraction, that few of the existing algorithms can encompass. The global convergence and self-stability property of the proposed algorithm are proved through the Lyapunov method and ordinary differential equation method, respectively. The proposed algorithm has a fast convergence speed, high precision and strong tracking ability. Finally, numerical examples and applications are explored to further demonstrate the efficiency of the proposed algorithm.

In recent years, field-programmable gate array (FPGA) devices have attracted a lot of attentions due to the increasing performance they provide thanks to technology scaling, besides their high flexibility through in-field reprogramming and/or partial reconfiguration capability. However, when such devices are to be deployed in safety- and mission-critical applications such as avionic and space applications, it is mandatory to verify the reliability of the device in the target environment where radiation effect is considered as one of the major sources of faults in the system. For static random access memory (SRAM)-based FPGA devices, the SRAM cells holding the configuration data for the circuit implemented on the devices are highly susceptible against single-event upset (SEU) induced by charged particle striking the device and one single SEU in the configuration memory may corrupt the implemented circuit design causing system misbehavior. In this paper, we present the radiation test data on Xilinx Kintex-7 SRAM-based FPGA using ultrahigh energy heavy-ion test beam for the first time available to third-party radiation test in CERN.

SRAM-based field programmable gate arrays (FPGAs) are widely used in mission-critical applications, such as aerospace and avionics. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, single event transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose a workflow for evaluating the behavior of SETs in SRAM-based FPGAs. The method is able to compute the propagation-induced pulse broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. Besides, we developed an accurate look-up table (LUT) layout model able to effectively predict the kinds of the SETs induced by radiation-particle and to accurately mimic the phenomena of the SET generation and propagation. The proposed methodology is applicable to any recent technology to provide the SET analysis, necessary for an efficient mitigation technology. The experimental results achieved from a set of benchmark circuits mapped on a 28-nm SRAM-based FPGA and compared with the fault injection experiments demonstrate the effectiveness of our technique.

General Purpose Graphics Processing Units (GPGPUs) have been extensively used in the last decade as accelerators in high demanding applications, such as multimedia processing and high-performance computing. Nowadays, these devices are becoming popular even in safety-critical applications, such as in autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of transient faults, such as those produced by radiation effects. Among those effects, Single Event Upsets (SEUs), which are the focus of this paper, can cause application misbehaviors, which may lead to catastrophic consequences. In this work, we first describe how we extended the capabilities of an open-source VHDL GPGPU model (FlexGrip) and developed a new version named FlexGripPlus to study and analyze the effects of SEUs in a GPGPU in a much more detailed manner. We also performed extensive fault injection campaigns using FlexGripPlus, which allowed identifying the most critical effects within the GPGPU architecture. We finally focused on the scheduler controller since it represents a module that is specific to the GPGPU architecture and showed that it has different levels of SEU sensibility depending on the affected location. Moreover, the results of additional analyses varying the number of parallel execution units in the system are presented, demonstrating the correlation between the number of execution units in a GPGPU and the system reliability.

The partial least squares (PLS) method has been widely used in quality-related industrial process monitoring because of its ability to extract quality-related information. Generally, online quality monitoring data cannot be obtained in real time, and in this case, updating the online monitoring model is a serious challenge. In this paper, an online monitoring dynamic PLS (OMD-PLS) model that uses the relation between time-delay process data and time-delay quality data is proposed. To accurately monitor the quality-related and process-related fault data, we also propose an online monitoring dynamic concurrent PLS (OMDC-PLS) model based on OMD-PLS, which has the ability to detect slight deviations. Furthermore, an alarm-parameter alarm method based on the OMDC-PLS model is proposed and effectively reduces the false alarm rate. Finally, numerical simulations and the Tennessee Eastman process are used to illustrate the effectiveness of the proposed methods.

With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development.

The robust guaranteed cost consensus problem of high-order discrete-time linear multi-agent systems (MASs) with parameter uncertainties and time-varying delays is studied, and a linear consensus protocol of it is designed. Norm-bounded uncertainties and polytopic uncertainties are considered. First, the idea of robust guaranteed cost control is introduced into consensus problems for the MASs, where a cost function is defined based on state errors among neighbouring agents and control inputs of all the agents. Second, by constructing suitable Lyapunov functions and using the stability theory of discrete-time linear systems, two sufficient linear matrix inequality conditions are derived to insure that high-order discrete-time linear MASs with the two types of parameter uncertainties and time-varying delays reach robust guaranteed cost consensus. At the same time, two upper bounds of the guaranteed cost function are also given. Third, convergence results are given as final consensus values of the MASs with parameter uncertainties and time-varying delays. Finally, two numerical comparisons are given to illustrate the correctness and availability of the theoretical results.

In recent years, topics around machine learning and artificial intelligence (AI) have (re-)gained a lot of interest due to high demand in industrial automation applications in various areas such as medical, automotive and space and the increasing computational power offered by technology advancements. One common task for these applications is object recognition/classification whose input is usually an image taken from camera and output is whether an object is present and the class of the object. In industrial pipeline, this task could be used to identify possible defects in products; in automotive application, such task could be deployed to detect pedestrians for Advanced Driver-Assistance Systems (ADAS). When the task is safety-critical as in automotive application, the reliability of the task implementation is crucial and has to be evaluated before final deployment. On the other hand, Field Programmable Gate Array (FPGA) devices are gaining increasing attention in the hardware acceleration part for machine learning applications due to their high flexibility and increasing computational power. When the SRAM-based FPGA is considered, Single Event Upset (SEU) in configuration memory induced by radiation particle is one of the major concerns even at sea level. In this paper, we present the fault injection results on a Convolutional Neural Network (CNN) implementation on Xilinx SRAM-based FPGA which demonstrate that though there exists built-in redundancy in CNN implementation one SEU in configuration memory can still impact the task execution results while the possibility of Single Event Multiple Upsets (SEMU) must also be taken into consideration.

In recent years, three-dimensional IC (3D IC) has gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation and achievable clock frequencies. However, the reliability of 3D ICs regarding soft errors induced by radiation is not investigated yet. In this work, we propose a method for evaluating the sensitivity of 3D ICs to Single Event Transient induced by Heavy Ions. The flow starts with identifying the characteristics of the generated transient pulses with respect to the radiation profile and 3D layout of the design. Secondly, our method provides a Dynamic Error Rate using a Simulation-based Fault Injection environment. Experimental results achieved applying the approach on a 15nm 3D configurable Look-Up-Table (LUT) designed on two tiers demonstrated the feasibility of the method, showing the vulnerability characterization of four different functional configurations using eight different types of heavy ions.

Partial least square (PLS) is a multivariate statistical analysis method which can distinguish the quality-related and quality-unrelated spaces. Modification of PLS (MPLS) is an improved algorithm for PLS. However, MPLS has the disadvantages of large amount of calculation in batch modeling and cannot overcome the dynamic disturbance in process monitoring. In order to solve this problem, we propose an adapt recursive modified latent structure (AR-MPLS) algorithm, which uses recursive structure to extend to the dynamic domain. Finally, we use the Tennessee-Eastman process to verify the effectiveness of the proposed algorithm in the dynamic domain.

In the time-varying industrial process, the quality of the product is crucial. The existing batch partial least squares (PLS) monitoring model can effectively monitor quality-related faults. In process monitoring, in order to overcome time-varying disturbances, the monitoring model needs to update regularly. How to update the monitoring model efficiently is a serious problem. This paper proposes a recursive concurrent projection to latent structures (RCPLS) algorithm, which can update models more efficiently with historical model parameters and new data, and can also provide better quality-related fault monitoring results than static concurrent projection to latent structures (CPLS). The updated computational quantities of the RCPLS model and the CPLS model are compared through the Tennessee Eastman Process (TEP). The effectiveness of the RCPLS algorithm is verified, and a comprehensive comparison of the quality-related fault detection capabilities of RCPLS and CPLS is performed. The results show that RCPLS can significantly reduce the computational burden and increase monitoring effectiveness.

An adaptive Nesterov acceleration gradient (NAG) algorithm is first developed to extract single generalized principal component (GPC) corresponding to the largest eigenvalue of a stationary sample autocorrelation matrix pencil. A deflation technique enables the proposed algorithm to extract the higher-order GPCs. The proposed algorithm enjoys the advantages of a lower computational load and a highly modular structure for efficient implementation. Simulation results are given to demonstrate the effectiveness of the proposed algorithm for extracting multiple generalized principal components.

General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video processing thanks to their powerful parallel architecture. In the last years, GPGPUs have been considered also for safety-critical applications, such as autonomous and semi-autonomous car driving systems. New GPGPU devices include an increasing number of parallel cores in order to increase throughput and performance. This increment in the number of cores and the requirements in terms of power consumption force designers to use aggressive semiconductor technologies.Nevertheless, those new devices can be seriously affected by radiation effects, modeled as Single Event Upsets (SEUs). SEUs could generate unexpected operation effects in the applications which could be unacceptable for the safety-critical ones. This work analyzes the SEU effects resorting to an open-source model of a GPGPU based on the Nvidia’s G80 architecture and aims at complementing previous analysis based on radiation experiments

Commercial SRAM-based FPGAs are widely used in aerospace applications thanks to their limited costs and high performances. Dynamic Partial Reconfigurability (DPR) allows to rewrite sections of the configuration memory of these devices while they are normally working. This is a powerful feature which provides advantages in terms of area, power consumption and flexibility. Moreover, DPR plays the main role in the recovery from faults that may occur in the configuration memory of the device when it operates in a radiation environment. Indeed, ionized particles which strike electronic devices, may cause various types of events. The Single Event Transient (SET) is a well-known phenomenon, which affects sensitive nodes causing transitory voltage spikes that can be sampled by a memory element, causing a fault. In this paper, an evaluation methodology for the errors caused by SETs during the reconfiguration of the configuration memory in SRAM-based FPGAs is presented. The evaluation methodology includes the fault model evaluation and the development of a fault injection and error evaluation workflow. The illustrated methodology has been applied on a physical device implementing a benchmark design and the obtained results are reported.

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.

General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applicationssuch as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field.Functional tests adoptingSoftware-based Self-test(, orSBST)are an effective solution since they providebenefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to knownmethods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions.This paper focusesOonone of the most relevant module consists on the scheduler corewhich is in charge of managing different scalar computational cores and the different executed threads.At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we providesome guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.

SRAM-based FPGA devices manufactured in FinFET technologies provide performances and characteristics suitable for avionics and aerospace applications. The estimation of error rate sensitivity to harsh environments is a major concern for enabling their usage on such application fields. In this paper, we propose a new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation. Experimental results provide a comparison between radiation test campaigns, which demonstrates the feasibility of the proposed solution.

Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-Programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.

Due to the decreasing feature sizes of VLSI circuits, radiation induced Single Event Transients (SETs) are increasingly dominating the event ratio on modern VLSI devices. In particular, Flash-based FPGAs are characterized by the main concern of radiation-induced voltage glitches or SETs in the combinational logic. Transient pulses can be sampled by a storage element and can propagate through the circuit up to the outputs and leading to an error. In this paper, we propose a complete implementation flow including sensitivity analysis, fault tolerant mapping and fault tolerance-oriented place and route for the effective design of SET tolerant circuits on Flash-based FPGAs. In details, the proposed method allows accurate measurement of the transient pulse source induced by radiation particles and estimation of the SET error rate on the overall circuit. Besides the developed method provides a netlist mapping and place and route tool for the selective mitigation of SET effects. The proposed method has been applied to an industrial design oriented to the Euclid European Space Agency mission including more than ten different modules. The obtained results show an improvement of the total filtering capability of around 43 times with respect to the original netlist without affecting the timing constraints of the circuit.

Due to rapid technology scaling, electronic devices are becoming more susceptible against soft errors induced by radiation particles, which is a serious challenge for aerospace applications. Meanwhile Field Programmable Gate Array (FPGA) devices have been attracting attention in safety- and mission-critical applications in recent years with the increasing performance and flexibility they provide. Among different types of FPGAs according to the device technology, the SRAM-based FPGA has a higher sensitivity against soft errors as SRAM cell, which is used for storing the configuration data of the circuit design implemented and mapped on the FPGA, is one of the most sensitive devices against radiation induced soft errors. Hence, to guarantee the usage of SRAM-based FPGAs in safety critical environments, the design mapped on it requires an effective verification and validation procedure. Radiation test is one of the verification methods regarding the effects of radiation induced soft errors. In this paper, we present an automated setup for monitoring the soft errors during the radiation test and we compared the measurement obtained from radiation test with the one provided by analytical tools. The experimental results we gained demonstrated the feasibility of the proposed measurement platform.

Hybrid error-detection techniques combine software techniques with an external hardware module that monitors the execution of a microprocessor. The external hardware module typically observes the control flow at the input or at the output of the microprocessor and compares it with the expected one. This paper proposes a new hybrid technique that monitors the control flow at both points and compares them to detect possible errors. The proposed approach does not require any software modification to detect control-flow errors. Fault-injection campaigns have been performed on an LEON3 microprocessor. The results show full control-flow error detection with no performance degradation and small area overhead. A complete solution can be obtained by complementing the proposed approach with software fault-tolerance techniques for data errors. This work was supported in part by the Spanish Government under Contract TEC2010-22095-C03-03.

In this paper, we propose a methodology for executing simulation using analytical models for the execution of SET propagation on System-on-a-Chip implemented on Flash-based FPGAs. Analysis performed on EUCLID-based circuit design demonstrated its effectiveness.

The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.

When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.

In this paper we combine a set of software-based fault tolerance techniques with a hardware module that monitors the trace port, and explore from an experimental point of view the fault coverage against soft errors in COTS processors that can be achieved. The costs in terms of performance and memory are also evaluated. Fault injection results show fault coverage is superior to the state-of-the-art techniques with lower performance and memory overheads.

As microprocessors are increasingly used in safety-critical applications, there is a growing demand for effective fault-tolerance techniques that can mitigate the effects of soft errors while reducing intrusiveness and minimizing the impact on performance and power consumption. To this purpose, approaches that are based on monitoring the microprocessor operation through an external interface in a non-intrusive manner have recently been proposed. In this paper we focus on the use of the trace interface for on-line monitoring. This interface provides detailed information about the instructions executed by the processor and can be reused to support error detection and correction in several ways, including multi-processors in hardware redundancy, time redundancy and control-flow checking.

General Purpose Graphics Processing Units GPGPUs are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.

Technology scaling enables the Field Programmable Gate Arrays (FPGAs) provide increasing computing power while remain low power consumption. Together with the high flexibility for application design and deployment, FPGAs have become popular even in safety- and mission-critical applications. Meanwhile, Commercial Off-The-Shelf (COTS) components are often used in system design to reduce time-to-market and development cost. In this paper, we are proposing a new method for the analysis and mitigation of Single Event Upsets (SEUs) on SRAM-based FPGAs. The method is based on an analytical analyzer algorithm able to accurately estimate the application error rate; furthermore, the same developed algorithm is able to implement mitigation rules. We present the radiation experiment results for analysis and mitigation of Single Event Upsets (SEUs) in an ARM-based SoC implemented on Xilinx Virtex-V FPGA demonstrating the feasibility of the analysis tool and the effectiveness of the mitigation method.

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

Flash-based Field Programmable Gate Arrays (Flash-based FPGAs) are becoming more and more interesting for safety critical applications due to their re-programmability features while being non-volatile. However, Single Event Transients (SETs) in combinational logic represent their primary source of critical errors since they can propagate and change their shape traversing combinational paths and being broadened and amplified before sampled by sequential Flip-Flops. In this paper the SET sensitivity of circuits implemented in Flash-based FPGAs is mitigated with respect to the working frequency and different FPGA routing architecture. We outline a parametric routing scheme and placement and routing tools based on an iterative partitioning algorithm able to generate high performance circuits by reducing the wires delay and reducing the SET sensitivity. The efficiency of the proposed tools has been evaluated on a Microsemi Flash-based FPGA implementing different benchmark circuits including a RISC microprocessor. Experimental results demonstrated the reduction of SET sensitivity of more than 30% on the average versus state-of-the-art mitigation solutions and a performance improvement of about 10% of the nominal working frequency.

Agro-ecosystem plays a crucial role in conserving biodiversity, sustaining ecosystem functions and processes, and maintaining land productive capacity. In order to effectively manage agro-ecosystem, the planners and government agencies are increasingly seeking better tools and techniques. In this paper, we describe the development of a Web-based resources and environment information system (FREIS), which helps to set up agricultural policy to improve productivity level and resource utility efficiency in terms of yield stability evaluation model. The system design involved four steps, the first was to set up a system platform for FREIS, then a spatial database was developed for analysis, after this the evaluation model was established, and lastly a Webbased interface with analysis tools was developed using client-server technology. FREIS provided a valuable technical scheme of the intelligent and comprehensive agricultural information management. The potential of a Webbased information system for agro-ecosystem management and challenges for its development was discussed.