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To resolve the problem that the iterative closest point (ICP) algorithm commonly used in knee joint replacement surgery registration had low registration accuracy and was easy to fall into local optimal solutions. An improved registration method based on feature point clouds was proposed. First, the Harris-3D algorithm was used to extract the feature point cloud of the three-dimensional model of the knee joint. Optical tracking system (OTS) was used to collect the point cloud of the corresponding area of the sawbone. Then, the Sample Consensus Initial Alignment (SAC-IA) algorithm was used to perform coarse registration on two point clouds. The ICP algorithm was used to make the registration matrix converge to an optimal solution. The k-d tree was used to find neighboring points to accelerate the iterative process. Finally, the simulation of the registration method was taken to prove the feasibility of the method. The accuracy of the knee joint surgery navigation registration experiment was carried out with the knee joint femur model as the object. Result shows that the error of the proposed registration algorithm is 2.12mm, while the error of the ICP algorithm is 6.30mm, which verifies the effectiveness of this method.

FDSOIs with SiGe channel have drawn significant attention due to their advantages in uniaxial strain, higher mobility and better reliability over conventional Si channel MOSFETs. Fabrication of the SiGe channel is based on selective epitaxial growth of low Ge fraction SiGe layer as well as the subsequent high-temperature oxidation of this layer on SOI substrate. It is found that the edge profile of epitaxial SiGe layer on SOI have strong impact on the terminal channel morphology. By optimizing the process of epitaxial SiGe layers, the SiGe channel with flat profile is demonstrated after oxidation process.

As short channel effect turns into a major constraint for traditional bulk silicon devices when CMOS technology scales down to 22nm and beyond, fully depleted silicon on insulator (FDSOI) devices becomes more popular in integrated circuit manufacture. The selective SiGe epitaxial is applied for FDSOI PMOSFET as raised source and drain to enhance hole mobility, whereas a defect, SiGe shrinkage, that SiGe non-growth on boundary of STI and AA can kill device yield. In this paper, an optimized Siconi pre-clean process and a novel Si-nucleation layer are proposed to improve the SiGe shrinkage, thereby boosting the device performance.

Metal hard mask TiN was induced as patterning film due to less ULK damage, but TiN tiny particle can make metal line open which is unacceptable. In this paper, the ramp mode of DC power during TiN deposition process was analyzed for tiny particle reduction. TiN as-dep defect scan results showed that DC power with slower ramp rate at ignition and pump down step can reduce tiny particle obviously. According to hard mask AEI defect scan results, metal open defect related with TiN film cannot be found.

Embedded SiGe as locally strained Si technology has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas. However, selective epitaxy of SiGe will be increasingly challenging as germanium concentrations increase. The emerging problems include poly line SiGe residue, poly top SiGe residue and NMOS area SiGe residue, which are three major killers for device yield. In this paper, these three defects are detailed investigated, the formation mechanisms are discussed and the proper solutions are suggested.

We consider the problem of sequential, blind source separation in some specific order from a mixture of sub- and sup-Gaussian sources. Three methods of separation are developed, specifically, kurtosis maximization using (a) particle swarm optimization, (b) differential evolution, and (c) artificial bee colony algorithm, all of which produce the separation in decreasing order of the absolute kurtosis based on the maximization of the kurtosis cost function. The validity of the methods was confirmed through simulation. Moreover, compared with other conventional methods, the proposed method separated the various sources with greater accuracy. Finally, we performed a real-world experiment to separate electroencephalogram (EEG) signals from a super-determined mixture with Gaussian noise. Whereas the conventional methods separate simultaneously EEG signals of interest along with noise, the result of this example shows the proposed methods recover from the outset solely those EEG signals of interest. This feature will be of benefit in many practical applications.

A class of second-order statistics-based algorithms consisting of the offline BSE, online BSE algorithms, and they are proposed for extracting stationary and nonstationary signals. Within our algorithm, the new cost functions were given by exploiting the prosperities of signals, and a steepest descent update method of parameter-free adaptive steps-size was proposed to obtain optimal extracted weighted vector. Simulation results for stationary and nonstationary show that the proposed algorithms have the ability to restore original signals one by one, and its superior performances to the higher-order statistics-based BSE algorithm. Moreover, the steepest descent update method of parameter-free adaptive steps-size has the following merits: no parameters to be adjusted manually, low computational cost and no additional preprocessing requirements.

Benefiting from the new 193nm lithography, a narrow tip with width of 100 nm can be fabricated on IME's MPW platform. Based on the new capability, we optimized the suspended coupler and realized the state-of-the-art coupling loss less than −1.3 dB/facet with cleaved single mode fiber. A uniformity of 0.4 dB across wafers has also been confirmed, the best performance to our knowledge realized in public-available silicon photonics platform.

The core-network suffers from inflexible and expensive equipment. Service chaining is a common but important problem of network management in Gi-LAN. The requirements of business agility drive the service architecture to services flexibility and scalability. To address these challenges, SDN centralized control and the NFV concept of CT reconstruction with IT virtualization technology are used to enable a reform in the mobile core network and the Gi-LAN service field. In this paper, following the technical trend of 5G, we propose the Cloud-ICT Convergence Service Architecture to construct an open and elastic digital information ecosystem. This architecture is a solution that provides flexibility in managing infrastructure and uses virtualization to dynamically orchestrate service chains on demand. The information ecosystem constructed in this architecture can provide the functional convergence of IT&CT services in addition to the traditional cellular network functions.

In this article, we proposed a novel method based on principal component analysis and support vector machines was presented for fault diagnosis of three-phase rectifiers, in which the principal component analysis of fault signal is used to extract the features corresponding to various fault, then fault types are identified through the pattern recognition classifier based on support vector machines. The simulation result of fault diagnosis of a thyristor in a three-phase full-bridge controlled rectifier shows that the method can make an accurate identification of fault types as well as the location of the fault elements for power electronics circuits, and it has an excellent performance for noise robustness and calculation complexity. Therefore, it is quite practically valuable in the solution to the fault problems for power electronics rectifiers.

Based on Wigner–Ville distribution similarity, a method of fault diagnosis is proposed for power electronics circuits. After setting up the module time–frequency matrices of Wigner–Ville distribution for all fault signals, the similarities between the module time–frequency matrices of the fault signal and the former standard are then calculated, thus arriving at the diagnosis according to the principle of maximum similarity. The simulation result of fault diagnosis of a thyristor in a three-phase full-bridge-controlled rectifier shows that the method can accurately identify the fault types as well as the location of the fault elements for power electronics circuits, and it has an excellent performance for noise robustness and calculation complexity. Therefore, it is quite practically valuable in the solution to the fault problems for power electronics circuits.

By taking the coupling between the non-neighbourhood waveguides into account, the coupling characteristic of three waveguide arrays is analysed. The strong coupling equation of three waveguides is dealt with Laplace transform and LU decomposition. The general field evolution equation is obtained by inversion of the Laplace transform. The results show that the self-imaging conditions (Talbot effect) do not satisfy in general. The theoretical predictions are in good agreement with the BPM simulations.

SiGe epilayer is extensively used as stressor in source/drain regions in PMOS. However, it is a big challenge to form germanosilicide with low contact resistivity due to poor thermal stability at high temperature. Therefore, silicon cap deposited on SiGe is applied to reduce contact resistance. In static random access memory (SRAM) area, silicon cap profile is apt to be un-conformal due to SiGe pattern effect. In this paper, the effect of silicon source, etching gas, doping gas and temperature on Si cap profile was investigated. Finally conformal silicon cap was obtained on SiGe epilayer with relatively high growth rate, which could reduce contact resistance.

This article applies the improved ant colony algorithm to the fuzzy c-means clustering, which overcomes sensitivity to initialization of fuzzy clustering method(FCM). This article improves the shortcomings which the traditional genetic algorithm and the ant colony algorithm work step-by-step, makes the mix algorithm work in the entire cluster’s process, simultaneously, puts the a swarm degree function in the ant colony algorithm, enhanced the ant algorithm search of the overall situation, increase the algorithm traversal the optimization capacity.

This paper gave a particular description of a tracking and concentration system for solar energy utilization. A Multi-glasses Concentration and Tracking Photovoltaic System is designed. A research on the racking and concentration system for solar energy utilization was made. A tracking system based on the theory that solar can be gathered depending on plane mirror reflecting was set up. And an implement project of racking and concentration system for solar energy utilization was put forward. Hardware and software of the racking and concentration system for solar energy utilization was designed. Include of: the design of logic circuit control module, the design of AC-electromotor driver module the design of temperature detecting module. The results of the kind debugging showed, the controller designed to meet the requirements.

A low power and low phase noise phase-locked loop (PLL) design for low voltage (0.8 V) applications is presented. The voltage controlled oscillator (VCO) operates from a 0.5 V voltage supply, while the other blocks operate from a 0.8 V supply. A differential NMOS-only topology is adopted for the oscillator, a modified precharge topology is applied in the phase-frequency detector (PFD), and a new feedback structure is utilized in the charge pump (CP) for ultra-low voltage applications. The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power. In addition, several novel design techniques, such as removing the tail current source, are demonstrated to cut down the phase noise. Implemented in the SMIC 0.13 μm RF CMOS process and operated at 0.8 V supply voltage, the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz. The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply. The occupied chip area of the PFD and CP is 100 × 100 μm2. The chip occupies 0.63 mm2, and draws less than 6.54 mW from a 0.8 V supply.